Virtual Memory for Microcomputers (MMU Comparison)

Virtual Memory for Microcomputers Four New Memory-Management Chips Pave the Way

Stephen Schmitt 2890 Sandhill Rd. Mason, MI 48854

Not too long ago, a microcomputer one answer. Virtual memory is an NS16082 is another interesting MMU system with 32K bytes of memory automatic system for controlling very that merits analysis.] Finally, I will was considered a luxury. Because big memories. But special hardware discuss some implications and ap memory was very expensive, you functions are essential for building plications of virtual memory in took great pains to squeeze, pack, such a system. And now, single-chip microcomputer systems. and cram programs into the small memory-management units (MMUs) amount of memory that you could af have been developed to provide these Program Folding ford. Today, however, you can buy capabilities for microcomputers. Almost every computer system has 256K bytes for less than $500. And In the first part of this article, I will several types of memory devices that new 16- and 32-bit microcomputers introduce some of the basic concepts differ in speed and storage capacity. feature directly addressable storage A fundamental tenet of computer spaces that are 100 to 10,000 times technology states that memory price larger than those found in 8-bit archi Virtual memory is a is directly related to its speed. Storage tectures. Like the pauper who just powerful concept. It hierarchies thus usually represent an became rich, how do you handle this allows you to consider effective compromise between a vast wealth? large, slow, inexpensive memory and Another drastic change in the main memory to be a small, expensive one with high ac microcomputer world deals with soft very large-much larger cess speed. Familiar examples of this ware. Multitasking operating sys than its actual physical are systems with relatively small tems, high-level languages, and flexi size. amounts of fast RAM (random-access ble business software have become read/write memory) and larger, popular. The problem is now more slower, and cheaper disk-storage complex: How do we take advantage of virtual memory. Next, I'll compare devices. of both the increased hardware power and evaluate four MMU chips that Although the cost benefit of such a and the new complex software? have recently become available: configuration is substantial, the effi Virtual-memory techniques offer Intel's iAPX 286, Motorola's cient management of this structure MC68451, and Zilog's Z8010 and presents a challenge. The movement Z8015. [This survey does not include About the Author of data between these two hierarchy Stephen Schmitt has worked for Hewlett the National Semiconductor NS16082 levels should be minimal; otherwise, Packard and also taught at Michigan Techno MMU for the NS16032 microproces the access time for the slow memory · logical University. He now doing a review of is sor. Because of its fairly recent in will predominate over the speed of a version of the Ada programming language troduction, the part was not the fast memory. In a typical two for microcomputers. evaluated for the review. The level system, main memory (MM) is

April 1983 © BYTE Publications :210 Inc 1000 to 5000 times faster than the gram logic is simpler and is focused by a program. The user does not have magnetic disks used for secondary on problem solutions, not critical to estimate memory allocation prior storage. Thus, disk accesses should be resource management. to execution. as infrequent as possible if we are to The objective of virtual memory is • Manual folding is eliminated and take advantage of the high speed of straightforward: to permit programs replaced, in part, by high-speed hard the main memory. with very large address spaces to run ware. Thus, programming costs tend Another problem is that the at MM speeds. In virtual systems, to be lower. relatively small size of the main main memory serves as a window (or • Programs execute correctly regard memory in most systems limits pro group of windows) onto the entire ad less of actual main-memory size. But gram size. An excessively large pro dress space held in secondary mem note that the execution speed may be gram must be broken into parts; each ory. If the window is big enough, and affected if the fast store is too small to piece is loaded into main memory if it accurately reflects the active part meet average memory requirements. prior to its processing turn and of total memory, the technique works • Relocation and task switching are returned to disk after execution. This extremely well. enhanced indirectly. technique is called folding or overlay The reason for this is that programs • Multiprogramming environments ing, and the task of folding programs tend to access small portions of mem have greater flexibility. The problem is usually a job for the programmer. ory over fairly long periods of com of deciding the optimal placement of The problem is that the mechanics of puter time. This is called clustering or programs in a fixed-size memory is defining separate program parts and locality of reference. Code loops and reduced. More programs can execute adding code to control data transfer manipulations of a data structure are concurrently because only the active between main and secondary mem examples of clusters or programs with portion of each occupies main mem ory are usually cumbersome tasks. good locality. A virtual system must ory. While this may induce less effi Also, the additional folding code detect and maintain in main memory cient use of the total addressable clouds program logic. Compilers and only the working set of a program, space, more effective use of the main linkers can simplify the task, but you memory is achieved. must still design the overlay frame Address space in a work. typical virtual system Having outlined the motivation for Despite these difficulties, however, ranges from 16 virtual storage, we are ready to ex folding operations are common. In plore basic components of system megabytes to 64 fact, the word processor I'm using to design. The memory-control process write this article applies the concept gigabytes, enough to must be transparent to normal opera twice. First, the program is too big to handle very ambitious tion and relatively efficient. On face fit completely into memory and is programming projects. value, you might doubt if reasonable divided into three overlays. Second, performance is possible, but research only a portion of my large text file into virtual-memory behavior clearly that is, those locations with high ac resides in memory at a given time demonstrates the concept's potential tivity. As activity gradually shifts to the rest is stored on disk. (see reference 2). I hope to show that other memory regions, these areas of As you can imagine, manual fold some practical systems can also have secondary storage are automatically ing consumes considerable time and a remarkably simple design. effort (as much as 25 to 40 percent of accessed and brought into main mem ory. As you might imagine, a high programming costs). But there is a Virtual-Memory Design: rate of secondary-storage access will way we can take advantage of the Basic Concepts benefits of large, sophisticated pro severely degrade performance. This is known as thrashing. Virtual storage systems require a grams without spending a tremen mixture of specialized hardware- and dous amount of time manually fold Benefits software-control policies. I will focus ing them to fit into small memory on architectural features that in spaces. Let's examine the benefits of virtual-memory management. Fore fluence virtual-memory operation. most, it removes the limit on program An understanding of intended ap Virtual Memory: Definition size imposed by main-memory size. plications should aid our analysis of Computer facilities that automati Address space in a typical virtual MMU products later. cally fold programs and data between address space system ranges from 16 megabytes to A computer's (AS) is two or more memory levels are called 64 gigabytes-large enough, I dare the legal range of addresses that can virtual-memory systems. Virtual say, to handle even the most am be generated by its instruction set . memory is a powerful concept. With bitious programming project! And The maximum size of this is deter it, you can consider main memory to virtual systems offer other advan mined by the number of bits in the be very large, mu.ch larger than its ac logical tages: processor's address register. A tual physical size. Intermediate files, address is a memory specification overlays, and many file-access proce • Main memory is allocated automat used by the central processor. Physi dures are no longer necessary. Pro- ically according to the demands made cal addresses, on the other hand,

212 April 1983 © BYTE Publications lnc LOGICAL ADDRESS MA IN PAGE OFFSET MEMORY 4 7 ADDRESS PAGE 0 I I I � MAP UN IT P6 I I 5 PHYSICAL + I ADDRESS 4 88 PAGING ASSOCIATIVE MAP TABLE 110 SECONDARY PHYSICAL- ;STORA GE PAGE ADDRESS u ID BASE WP EN ADDR ESS PAGE 0 � 6 I 0 I I '-to 4 0 I I I ' PI I I I ;EJ5 O I I I 6 I l 5 � PAGE 7 I FAULT 63 � t ITO MICROPROCESSORI

Figure 1: The associative mapping scheme for virtual-memory systems. The central processing unit specifies a memory location with a two-part logical address that in cludes a page field and an offset field. The page field provides the value used for search ing the map table. All cells in the table are searched in parallel. If a match is fo und, the selected cell's physical-address-base field is added to the offset field. A page fault occurs when there is no match. In this simple diagram, the second cell matches and translates the logical address. The attribute fields in the above map table are WP

(write-protected), EN (valid main-memory page; EN = 0 only when main memory is not full), and U (used; recent page access has occurred).

describe actual locations in the main tion, the system must be able to trans memory. In most systems, logical and late that part's logical address into its physical addresses are one and the present physical address in main same (as, for example, in 8-bit memory. This is known as the map microcomputers). With a virtual ping process. Both these processes, system, however, the size of the AS page-fault detection and mapping, can be significantly larger than main are fundamental to every instruction memory. The AS may be thought of step. They must therefore be per as occupying a contiguous area in formed by high-speed hardware. secondary storage; and logical ad A page fault stops execution of the dresses no longer correspond exactly current activity that the central pro to actual physical RAM locations. cessor is performing (e.g., fetching an In a virtual system, main memory instruction or processing operand contains changing portions of AS. At data) until the absent memory is various times, an instruction may ad brou ht into MM. A page fault is g dress a part of the AS that is not con similar to an interrupt except that it tained in main memory. This is may occur partway through instruc known as a page fault. A virtual tion processing. Thus, special pro memory system must be able to cessing logic is needed to handle par detect a page fault and move the tially executed instructions (consider desired part of the AS into main the problems associated with restart memory. Then, when that part is sub ing a MOVE BLOCK instruction). sequently addressed by an instruc- In a virtual system, memory can be

Circle on Inquirycard ...... 297 LOGICAL AOORESS MA IN PAGE OFFSET MEMORY ADDRESS PAGE 7 0 I I I � MA P UNI T 1 15 PO PHYSICAL �EJ + ADDRESS MAP REGISTERS I PHYSICAL PA1/0GING ADDRESS BASE p u SECONDA RY STORA GE ADDRESS PAGE :1�----� -+--t-----11 : I : I 0 P1 1 15� EJO 56 � 7 I PAGE 63 \ FAULT � J ITO MICRDPROCESSORI

Figure 2: The mapping-by-address (or mapping-by-register, MBR) scheme for virtual memory systems. This is similar to associative mapping except that each map cell is a register that refers to a page in secondary storage. In this simple example, the page field in the logical address refers to register 7, which in turn refers to page 0 in main memory.

If register 1 had been accessed instead, a page fault would have occurred (P = 0). Page 1 would then be placed into main memory, probably in the space now occupied by page

7, because page 7 has not been accessed recently (U = 0) . divided into either pages or segments. In the examples, logical-address fields A paged policy divides memory (both are composed of two parts: a page AS and MM) into equal-size blocks. field and an offset field. The logical The rationale for pages relates to the page number is translated into a clustering principle. Memory activity physical location by the map unit. occurs in scattered parts or clusters of Adding the offset field to this location the AS. By organizing storage into forms the complete physical address. pages, you can "break out" the busy A simplistic memory model will be sections and place them in main mem used to show the basic operations of ory. Paging, like disk blocking, also each technique. implies a smaller number of data Associative mapping is shown in transfers between disk and main figure 1. The logical-address page memory. field is compared, in parallel, to all Segments are merely pages of page entries in the map table. If an en variable size. Segments can closely try matches, its corresponding physi model program units because code cal-page address is combined with the modules and data structures vary in offset value to form the complete size (as do clusters). Trade-offs exist physical address. A page-fault condi between page and segment organiza tion is raised when no match occurs. tions. I'll discuss these later. For now, The problem with associative maps is you can ignore the distinction and that they are expensive. High-speed call both pages. register memory with integrated com Several mapping schemes exist for parative logic is needed; translation virtual systems. Figures 1 through 3 has to be fast and transparent. The illustrate three common techniques. associated map has to be as large as

Circle 298 on Inquirycard .--.. the number of MM page frames. If LOGICAL ADDRESS you change the size of main memory, SEGMENT OFFSET you have to change the map size ac MA IN cordingly. Associative mapping MEMORY works best for systems with a large number of AS pages and a moderate ADDRESS0 ....-----, sized, fixed main store. MA P UNI T ISE GMENT Figure 2 illustrates mapping by ad dress or mapping by register (MBR). SEGMENT In this technique, the logical-address 3 page field refers to an array of high N l---_, speed registers. These registers hold PRT I I status and physical-address informa L ____ J tion. Mapping by address is analo PRT BASE OPTIONAL gous to indirect memory addressing CACHE except that the registers permit very high processing speeds. Page faults PRT CELL are detected when the addressed PHYSICAL register's "present" bit is clear. The ADDRESS problem is that every page in the AS BASE SIZE P U SK requires a corresponding map reg ister. Fortunately, the economy of I I conventional registers offsets the I I mapping array size. Note that the SIZE ERROR 1 PAGE I ITO MICROPROCESSOR) FAULT mapping hardware is unaffected by � ITO MICROPROCESSOR)� changes in MM size. For relatively small address spaces, mapping by ad Figure 3: The segment map table scheme for segmented virtual-memory systems. In this dress is quite attractive. mapping scheme, information on each segment of a program in secondary storage is The last technique I'll present ap kept in a program reference table (PR T) in main memory. The location of the PRT is plies to segmented systems. Figure 3 stored in a PRT Base register. In this simple example, the segment field in the logical ad defines the operational details. This dress is added to the contents of the PRT Base register (N). This refers to a map cell at design is based on the Burroughs Cor location N + 1. In this map cell is a physical-address base that is added to the offset to obtain the desired address in main memory. Note that bounds-checking can easily be poration BSSOO mainframe. This ap done by comparing the offset with the size field. Also, note that things can be speeded proach gives you more flexibility, but up by placing the most active map cells in a small associative cache memory. The at is slightly more complex and neces tribute field SK indicates a stack segment (i.e., the offset orientation is reversed). sitates additional hardware (for the

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full) the MMU _ Keeping copies of the most active PRT entries in this high-speed Table 1: A summary of the control and status information-used by virtual-memory buffer greatly increases mapping mapping units. Most mapping schemes use a subset of these different attribute fields. speed. Besides translating addresses, map ping units also provide other func tions. They hold information to aid memory management and data pro tection. Table 1 is a list of informa tion found in various mapping sys tems. Each virtual system uses a subset of these items, determined by the particular mapping scheme used and the memory-control functions. Up to now, attention has centered on the hardware aspects of virtual --THRASHING systems. Now, let's consider the AREA memory-management and software PAGE FAULT requirements for virtual systems. RATE Paging Policies As mentioned previously, a mim mal amount of secondary-storage ac cess is central to a virtual system's viability. Figure 4 shows a graph of disk activity versus main-memory PROGRAM size allocated to a program. From the MAIN-MEMORY SIZE ADDRESS graph, we see that given enough main SPACE memory, disk access approaches zero. However, a primary aim of vir Figure 4: A graph showing how the page-fault rate (i. e., the rate of accesses to pages tual memory is to provide a huge ad not present in main memory) is related to the size of main memory. The operating pqint dress space while minimizing expen is the memory size sufficient to hold a program's most frequently accessed routines-its sive main memory. To satisfy both working set. Adding memory past this point has little effe ct on the page-fault rate. Of conditions, you must operate at a course, as the needs of a program change, the operating point will shift. point just below the "knee" of the

220 April 1983 © BYTE Publications Inc curve (labeled operating point). The tive page that is next referenced the locality principle states that the furthest into the future. Even though amount of MM needed at any given totally impractical, it is a benchmark time is but a small portion of AS. for comparing other techniques. Hence, if you keep the active cluster or working set in memory, thrashing Page-Replacement Algorithms and main-memory needs are mini Virtual-system performance is very mized. much dependent on the page-replace Sounds simple, doesn't it? Alas, a ment technique that is used. Because few minor problems "gum up" mat the process selects departing pages, it ters. For openers, measuring a indirectly determines the pages re system's working set is a dynamic maining in main memory. If the algo process. The size and contents of a rithm closely models a system's actual working set change rapidly. Keeping working-set memory demand, few track of working sets involves con page swaps will result. Algorithms siderable time, resources, and prob usually base removal choices on prior lems. Just how is this working set reference activity, because the local determined? At what times do we ity principle implies that past change the working set to reflect behavior approximates future needs locality movement? What happens (at least over short time periods). when several programs are running Here I will discuss four specific or there is program I/07 All these page-replacement algorithms: Least problems are handled by a paging recently used (LRU). Clock, Gener policy. alized working set (WS), and WS Basically, a paging policy does Clock. three things: The LRU Algorithm • Fetching-decides when to transfer This page-replacement policy is pages from secondary storage to main conceptually related to the optimal memory algorithm. Instead of selecting the • Placement-determines which MM page with the furthest time until next page frame should hold the fetched access, you pick the page whose last page reference occurred longest ago. If not • Replacement-when main memory used for a long time, the probability is full, chooses which MM page frame that the page will soon be referenced should be replaced by the fetched is small. When a page fault happens, page you scan the map cell for each page and replace the page having the In regard to fetching, research has smallest (oldest) virtual time. found that demand paging is general To implement LRU, the memory ly best. When a page fault takes management hardware must support place, you fetch the desired page from two features: a virtual time register in secondary storage. The placement the map unit and the ability to update decision is resolved automatically by the page access time during address mapping hardware. The last issue, translation. The time register should

Start with a Model II floppy system and however, choosing which page to be wide enough to ensure sufficient grow into a hard disk. Since all P&T replace, is the hard part. The replace resolution. In addition, the necessity CP/M systems are fully compatible, 2 ' you will have no conversion worries. ment policy affects how well we ad of associating a time stamp with Special note: P&T hard disk systems dress the other concerns mentioned allow you lhe user lo configure logical every memory reference dictates drive assignments to your specifications. above. high-speed logic and added map com Write for more details. Page-replacement techniques, plexity. Prepaid VISA, M/C, or COD orders accepted. All prices FOB Goleta and subject to change. which determine the set of main The LRU algorithm works well. Its memory pages, are all approximation performance is much better than that algorithms. This is so because you of an arbitrary replacement policy or can't calculate the best page to many other paging policies. But remove without some future knowl because LRU is a global policy, it can edge of which page will be required. exhibit anomalies in multitasking sys The optimal algorithm (OPT), or tems. For example, global LRU tends Belady's algorithm, replaces the ac- to save pages of the task last executed

222 April l983 © BYTE Publications Inc and favors jobs with smaller locality; when a clean, not recently used page according to empirical studies. WS is low-priority tasks and large programs is found, and the pointer is left at the so named because it approximates the may experience reduced throughp�t. chosen page. A replaceable page is working-set locality model. In WS, Computer systems using LRU in not processed if accessed before the any page referenced within a specified clude the , CDC Star-100 and the disk transfer. time (designated as is regarded as a 9) Multics drum-to-disk control. Micro Studies indicate that the Clock al member of the working set. Real computer MMU parts lack the hard gorithm closely simulates LRU re working sets of course have variable ware mechanisms needed for a "pure" placement, and the hardware needed durations, but if the WS time-control LRU policy. is inexpensive. As implied above, value is properly chosen, a real (9) only 2 flag bits per cell are required working-set model can be closely ap The Clock Algorithm (changed and used). Software com proximated. This algorithm is a variation of the plexity and overhead are small. Cal I will briefly highlight WS opera LRU algorithm. Main-memory pages culations are trivial and the average tion (see reference 1 for details). The are logically ordered in a circular list. number of scans per page fault is a WS policy defines a working set (W) You can envision each page as a unit fraction of total map size. Many suc to be those pages of the AS that have marking of a clock face. A pointer or cessful mainframe systems, including been referenced within the previous e hand always points to the last page the IBM 370 and Multics, use Clock time units. In order to determine replaced. On a page fault, you ad algorithms. However, you should when a page (p) in main memory is vance the pointer clockwise to the note that deficiencies of LRU apply no longer in W, and thus is replace succeeding page. Then you check and equally to Clock. The technique of able, we need two things: (1) a pro clear that page's used bit. If the bit fers a simple mechanism and good ef cedure to calculate a time value (L) was set (i.e., the page was used ficiency; but, as you shall see, other equal to the owning task's current recently), scanning continues; other paging algorithms exhibit even better execution time (ET) minus the last ref wise, the frame is not recently used performance characteristics. erence time for every AS page, and replaceable. If the replaceable LREF(p), and (2) a scan mechanism to page has been changed (or dirty), you The Algorithm check for values of L greater than or WS must schedule it for transfer back to This page-replacement algorithm equal to Calculating L can be done e. secondary memory. Scanning stops represents the most practical policy with page-frame counter registers. When the page is accessed, its counter register is cleared. Then, at fixed in tervals, a global broadcast pulse in crements all the counters. The scan operation can run at various times (e.g., at fixed intervals or when a WEWRO TE ll-IEBOOK page fault occurs). Pages marked as replaceable become part of the avail 0N 1WO WAY RADIO. able pool (AP). The page-replace ment algorithm merely selects some Read all about it. How Two -Way Radio page from the AP and replaces it. If canAND help just aboutIT any 'S businessFREE.lower the AP is empty, the system must sus costs and increase profits via more pend a task to free pages. efficient use of people and vehicles. Although WS accurately models Plus, how to choose the right radio dynamic-memory demands, the com from Johnson's complete line of putational overhead and extra hard mobile communications equip ware support it requires diminish the ment. American made by the algorithm's viability. Space for the All two-way pioneer not only chal LREF(p) field can effectively double page-table size. Moreover, the lenging but pacing the industry. counter mechanism is relatively ex backed by a year's All full 100% t'Jj pensive. Scanning requires inspection warranty on parts and labor. · all �0HNs 111 of each map cell at regular intervals, Phone toll-free 800-328-5727 122. 0 Ext. and AP maintenance adds more con (InMinn eso� 800-742-5685 122.) Or write trol functions. On the plus side, the Ext. Johnson Radio Products Division, Wa seca, local scope of WS enforces more con MN56093, for your free copy. sistent multitasking management. And pure WS simulations perform better than other policies. Research :19.dt'P�u�2�� systems have implemented practical ThE[�CHALLENGER] WS schemes and observed substantial 224 April 1983 © BYTE PubliationsInc Circle 461 on inquiry card. improvements over Clock tech every AS page average number of frames examined niques. The parameter e allows you ethe available pool (AP) is per page fault compares favorably to "tune" a virtual system for dif eliminated with WS. And to implement WS ferent applications. Also, investiga Clock, you need minimal map hard tions have found that use of the con This algorithm organizes page frames ware: a used bit, a dirty bit, an LREF stant value e deviates less than 10 in a circular list like Clock. The clock field, and a task ID descriptor. percent from an optimal WS. pointer identifies the page replaced WS is technically appealing, but during the last scan. When a page Multitasking and Load Control design difficulties detract from its ad fault occurs, the scan advances clock In a multitasking system, virtual vantages. Like LRU, classical WS is wise to the next page. The used bit is memory management must coincide impractical for microcomputer ap checked and cleared. If the bit was with general resource-sharing plication. But the next technique set, you reset the page's LREF(p) to policies. The probiem is that in a surveyed approaches WS perfor the owning task's accumulated execu dynamic multiprocessing environ mance and is feasible for microcom tion time (ET). Otherwise, if the used ment, wide variations in program

puters. bit is clear and if L = ET - LREF(p) ming level and memory demand oc e you remove the page from cur. Every active task consumes a > =. ' The WS-Clock Algorithm W. If dirty, a replaceable page is portion of total memory (in both MM WS-Clock combines the best prop scheduled for disk transfer and not and AS). At some point, adding erties of Clock and WS. Additionally, replaced. Scanning halts when you . another task will push MM demand · the new strengths offset some prob encounter a clean, replaceable page. past the ideal operating point in lems of the separate procedures: WS-Clock approximates WS re figure 4 and trigger the onset of placement, and W for the two policies thrashing. Left unchecked, through • the extra scanning required by WS becomes equivalent when the task ex put diminishes rapidly. Accordingly, is replaced by a simple Clock mech ecutes for units of time. Perfor you must either prevent the "over 8 anism mance differences appear negligible commitment" of memory or • WS-Clock is a local policy and can be ignored. Thus, WS-Clock recognize the condition and make • LREF(p) registers are needed only approaches WS behavior with a sig corrective adjustments. This is done for main-memory pages, not for nificantly simpler mechanism. The by a load-control policy.

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Educational BOX 16115. IRVINE. 927 13·61 15 Microcomputer P 0. CA Syatema 17141 553-11133 EMS 226 April 1983 © BYTEPublications Inc Circle 251 on Inquiry card. Circle 156 on Inquiry cerd. the MTOR and reload the mapping Memory Structure hardware. A VS(n) system gives you, Function or in effect, several virtual machines, Characterist ic Segments Fixed Pages each using the same ·physical re Flexibility + Can model pages, has more - Lessens "tuning" options, sources, running concurrently. VS(n) design options, promotes trade-off exists between protection, data sharing, efficient 1/0 blocking systems also give you improved and so on and memory waste system integrity and data protection. Hardware - Cost and complexity fairly + Lower cost, simpler hardware requirements high Page Size VS(1) systems + Better security + Simpler design An important design consideration VS(n) systems + Segments are mandatory for 0 Not applicable is block memory structure. If you VS(n) designs select a fixed-page structure, you Mapping unit Map-register - More space needed for size + Minimal must determine the number and size size fields of page frames. Secondary storage Table size + Fewer frames needed if 0 Larger pages result in transfers data in fixed-size units. segments are large memory waste Hence, for efficient paging memory Memory frames should be an integer multiple management overhead - Extra logic needed to close + Placement simple of a disk block. Big pages reduce disk "holes" and to manage overhead and map hardware. On the extra attributes other side of the coin, however, a Allocation + Make segments the desired 0 More complex, but no main large number of small pages lowers size memory waste policy page-fault rates and increases the Protection + Superior-facilitated by extra - Pages do not correspond to attribute fields program "objects" number of locality sets. Some com Sharing + Direct support - Much harder promise is in order. My research in 1/0 efficiency 0 Depends on segment size + Facilitated by relating page dicates that lK- to 4K-byte pages are size to disk block size considered optimal. Memory usage A segmented address space reflects Internal + None - Some main memory wasted programming features such as scope fragmentation rules, data encapsulation, modulari External 0 Can reclaim with "garbage + None fragmentation collection" ty, and so on. Pages, being constant in size, usually waste some memory, Page-fault rate + Lower rate 0 Depends on page size a condition termed internal fragmen tation Table 2: A comparison of the relative strengths and weaknesses of segmented and (e.g., aSK-byte program takes fixed-page memory organizations. The + /- column indicates approximate merit: two pages in a system with 4K-byte ( +) good; (-) poor; (0) okay or does not apply. pages-3K bytes are unused). Al though segments avoid this problem, they are prey to a form of waste Load control is sensitive to page-re address space as a shared resource called external fragmentation. placement strategy. Local strategies divided among the several active jobs Because variable-size units are estimate each task's independent or whether each process is provided a allocated, program termination memory needs and allocate sufficient separate AS. The first class, termed leaves holes of unused space. You main storage to hold the locality set. VS(l), extends the idea of a conven must close up these areas periodically Global page-replacement strategies tional operating system where super to provide sufficient space for large discriminate in favor of the most re visor, system resources, and user segments. Consequently, the pro cent task's memory set and can lead tasks occupy one large address space. cedures to reclaim these holes add to to thrashing. Software compatibility with non operating overhead. In general, virtual systems is a major benefit of segmented schemes offer more flexi this system. System complexity is System Design: Issues and Options ble designs while page organizations minimized and a single mapping table make for easier memory manage Virtual memory reflects a com can define AS structure. ment. Table 2 summarizes trade-offs' posit� of hardware, resource manage between page and segment organiza ment, and programming processes. VS(n) tions. We now turn our attention to alterna VS(n) systems give each executing Many other topics related to vir tives that can affect overall micro task a unique AS. To support this fea tual memory have not been covered: computer system design. ture, every job has its own mapping operating-system interaction, l/0 table. Typically, a mapping-table considerations, page locking for non VS(l) origin register (MTOR) points to the swappable memory, disk-access A fundamental system decision is mapping table of a running task. properties, and more-the subject is · whether you treat the large virtual When switching tasks, you change rather deep. However, the topics

228 April 1983 © BYTEPublicotions Inc to extend the address space of limited MEMORY-MANAGEMENT UNITS address machines (e.g., the HP-1000 FUNCTIONAL Intel Motorola Zilog Zilog · or DEC PDP-11 minicomputers). CHARACTERISTICS iAPX 286 MC68451 Z8010 Z8015/PMMU Address-translation 0-1 .5 p.s 100 ns 60 ns 70 ns A Survey of MMU Chips delay (10 MHz) Supports multiple No Yes Yes Yes The main thing we'll look for when MMUs? examining these MMU products is No. of MMUs needed to 2 Depends on how well they implement virtual map address space MM size No. of unique address Unlimited 256 8 8 memory concepts. We'll review four spaces possible (no. products: 2ilog's 28010 and 28015, of users) the Motorola MC68451, and Intel's VS(n) support? Yes Partial No No Priority levels 4 0 0 0 iAPX 286 processor /MMU. The User/supervisor No, uses Yes Yes Yes 2ilog chips are to be used primarily modes available? priority with the 28003 16-bit microprocessor levels for virtual storage. The MC68451 Data· sharing? Yes Yes Limited No MMU control method Special 1/0 1/0 110 MMU is designed to work with the instructions program program program soon-to-be-released MC68010 pro Fault restart data None Limited Moderate Extensive Control and status cessor. Finally, the iAPX 286 rep attribute names resents a combination of both an (dash indicates not 8086-compatible processor and an in supported) tegral memory-management unit. Present CPU I p The 28010, MC68451, and iAPX A Ref Ref Used u Dirty M Chg Chg 286 feature segmented-memory archi Write-protected WP RD RD tectures. The 28015, however, is de w Read-protected R signed specifically for a fixed-page Executable code E Exc Exc Shared AST virtual-memory system. All four Stacked memory ED DIRW DIRW units support a 16-megabyte 110 access DMAI physical-address space. Logical Overflow warning DIRW DIRW Virtual time LREF address spaces range from 8 mega Task ID (Yes) (Yes) (Yes) (Yes) bytes for the 2ilog chips to a whop Fix F ping 1 gigabyte in the iAPX 286. Enable E Valid Tables 3 and 4 compare the basic Table 3: A comparison of 'the functional characteristics of the four surveyed properties of these chips on a point memory-management units. by-point basis. As the tables show, there's quite a bit of diversity. For each MMU, I'll point out its unique covered should give you the perspec virtual system's large address space characteristics, operation, and pro tive to analyze the capabilities of the makes allocation less of a concern. gramming details. Later I'll describe new memory-management units for • Program relocation-Relocation some applications for virtual microcomputer virtual-memory hardware permits a program to load memory. systems. anywhere in physical memory with out changing the logical addresses. The Zilog Z8010 Memory Management Systems that swap tasks to disk may The 28010 was one of the first The need for a memory-manage need to relocate a program when it's single-chip MMU devices on the ment unit (MMU) derives from two reloaded. market. As a consequence, it has a concerns: efficient control of large • Protection-This prevents inadver few flaws that have been corrected on memories and support for multipro tent or unauthorized destruction of newer products. In fact, virtual mem cessing environments. We can sum data. Also, one task cannot interfere ory appears to have been an after marize the major goals of memory with another's operation. thought for this chip because you will management as follows: • Data sharing-Controlled access to need extra hardware to handle the common data or code. 28000 microprocessor's page-fault • Memory allocation-Allocation •Multitasking-Several tasks can procedure. Still, the product does policies determine what portions of logically occupy main memory dur have good protection features, and it memory are committed to particular ing a given time frame. directly supports a supervisor mode tasks. Address translation allows you for operating-system functions. to treat physically separate blocks as Virtual memory is just one of Another virtue is its fast translation logically contiguous. Dynamic several approaches to memory man time. allocation, which adds memory dur agement. Another approach is The 28000 architecture defines ing execution, is a valuable feature. A dynamic mapping, a technique used logical addresses for 128 segments, Text continued on page 234 April 1983 © BYTE Publications 230 Inc segment size. The segment-size MEMORY-MANAGEMENT UNITS resolution may not reflect program PHYSICAL Intel Motorola Zilog Zilog modularity (studies indicate that me CHARACTERISTICS iAPX 286 MC68451 Z8010 Z8015/PMMU dian module size is about words). SO No. of pins 68 64 48 48 More important, the number of pages Integrated processor? Yes No No No (8086) it can handle may be insufficient for Dimensions (mm) 24 by 24 22 by 81 15 by 51 15 by 51 working-set purposes. Although you IC process HMOS HMOS NMOS NMOS can share data, utility is minimal. 1 5 1 5 Powe r (W) 3 1 . . Compatible processors Many of the benefits of a segmented Model Integral MC68010 Z8001/3 Z8003/4 design are not fully realized. Clock rates (MHz) 8, 10 4, 6, 8, 10 4, 6, 10 4, 6, 10 The Clock page-replacement policy Cost per unit (10 MHz) $237 $1 11 $383 $137 Logical addresses would probably work well with the Virtual size 1 gigabyte 16 megabytes 8 megabytes 8 megabytes 28010. Without an LREF field and Address width (bits) 32 24 23 23 strong multiuser support, WS-Clock . Memory structure Segment or page? Seg.ment Segment Segment Page is likely to be inefficient. Poor sharing Size field (bits) 16 1imit 16 mask 81imit NA and task switching make a VStn) Size range 1 byte - 256 bytes - 256 bytes - 2K bytes design impractical. Time required for 64K bytes 16 megabytes 64K bytes Resolution 1 byte Power of 2 256 blocks Adjustable MMU programming and the page Page boundary 1 byte 256 bytes 256 bytes 2K bytes fault recovery procedure is partially Map organization Segment Associative Mapped by Associative offset by translation speed. I can't see (mapping scheme) map table lookup address lookup Maximum no. of pages the 28010 finding much use outside of or segments per MMU 16,384 32 64 64 systems with few users or nonvirtual Map cell width (bits) 6'4 72 32 32 environments. Physical-address base field width (bits) 24 16 16 13 Attribute field (bits) 8 8 8 7 No. of high-speed The Zilog Z8015 registers 4 32 64 64 The 28015 is most notable for its MMU address- 24-b t 16-bit 16-bit 13-bit i paged-memory strategy. Although generation unit adder logical adder concatenation Global control-register 1 byte 4 bytes 3 bytes 3 bytes markedly different in mapping and set (7 bits) logical block structure, most of its Global status-register 0 (status 18 bytes 6 bytes 9 bytes features · borrow heavily from the set pushed on stack for 28010 design. Protection, program faults) ming, and multiprocessing com ,I ponents are virtually identical. This Table 4: A comparison of the physical characteristics of the four surveyed memory- MMU's main selling point is the . management units. All four have the same physical-memory limit: 16 megabytes. simplified allocation and storage mechanism inherent in a paged system. Also, several mistakes found and the 28010 has 64 map regi�ters. If tern to dynamically extend segments in the 28010 are corrected in the you use the mapping-by-address tech during execution, making allocation 28015. nique, y_ou will need two MMUs to procedures easier to implement. The 28015 employs an associative map AS. The user/supervisor flag Programming the MMU is accom lookup mapping scheme. Each 28015 can be used as an extra addressing bit plished through 22 special 1/0 in MMU chip can map 64 pages, each to increase memory size to the full 16 structions. By placing the MMU into 2K bytes in length. Thus, each unit megabytes. With this type of command mode, you can manipulate directly maps 128K bytes. Up to 64 organization, four MMU chips are map cells and global status registers units can be grouped together, giving necessary (i.e., 128 segments in two in a manner similar to programming you a total of 4096 page frames (8 separate address spaces). DMA or peripheral controllers. megabytes)-ample room for system You can assign four protection at 28000 instructions permit you to send expansion. tributes: read�only, data/ code, sys a block of commands and data to If you don't like 2K-byte pages, tem reserved, and l/0 enable. If you speed up the process. simple wiring alterations allow dif do sophisticated l/0 processing, Provisions for virtual memory are ferent size options. Page attributes you'll appreciate the l/0 flag. An marginal at best. Only three attribute are the same as a 28010's except that other feature, the direction and warr1- flags aid paging policies: present, ac l/0 enable is omitted-too bad, it's a ing (DIRW) attribute, indicates the cessed, and changed. Up to eight handy feature. Translation time is orientation for a stack segment. separate users are possible, but this about 15 percent slower. When set, offsets can be negative. requires additional MMUs and exter As with the 28010, you should DIRW also provides a warning if you nal hardware. The 28010's limited stick to the Clock replacement algo are accessing the last 256 bytes of the number of segments has two major rithm and a VS(1) design. The MMU segment. The warning allows the sys- drawbacks. First, it discourages small supplies all the information necessary

234 April l983 © BYTE Publications Inc · to recover from a page fault; extra triguing methods to build the . func several logical-address page values hardware is not required. The in tions that constitute a virtual can map to a single cell entry. creased number of page frames is memory scheme. Each map cell contains a user-space noteworthy: you can achieve a higher Like the Z8015, the MC68451 relies number and associated mask. A valid degree of multitasking, and it is easier on associative mapping. Address memory reference must match the ac to expand storage. But with the translation takes place in two stages tive processor user number. The Z8015's fixed-page policy, you consisting of an address range and masking function allows a range of sacrifice some degree of flexibility. user-space comparison. A clever tech user numbers (or just one) to use the Adequate support for virtual memory nique accomplishes both lookup and same segment; sharing among users and system security yield the com segment bounds-checking in one fell becomes almost a trivial task. ponents of a virtual microcomputer. One worrisome point is the map On top of all this, you cari use the table size. You get merely 32 map Motorola's excellent Z8015 to implement dynamic map cells per MMU, and physical limita ping for the Z8004, the 16-bit-address MC6845 1 furnishes tions restrict you to a total of eight version of the Z8000 processor. the horsepower to MMU devices (or 256 cells). You need construct a serious more than that. Also, the MMU The Motorola MC68451 design is complex; it has too many in virtual computer Motorola has come up with an ex ternal registers and multiple MMU cellent memory-control product. The system. coordination is complicated. You MC68451 furnishes the horsepower have your work cut out for you pro to construct a serious virtual com swoop . Normally, logical page gramming this hardware. puter system. In combination with numbers and each map cell's page Status registers contain used and the MC68000, which I think is the number are compared bit-wise for a changed bits to aid virtual paging best 16-bit microprocessor around, match. Instead, the MC68451 routines. But there's no provision for the MC68451 is quite impressive. employs a mask field that selects an LREF attribute. Curiously, some Before getting too worked up, how which address bits to check against a bits cause an interrupt to be generated ever, I should mention that I do have map cell's page number. The mask ef whenever reference is made to the a few reservations about the device. fectively turns some of these bits into segment. The purpose of this feature Despite this, the MMU uses some in- "don't cares." The end result is that eludes me-maybe it's for debugging.

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8384 • P.O. Box • La Hercules St. 425 Mesa, CA 92041 f:!.i Your Assurance of Value and Service. k!i f��"'""'?�\�� 51� l'id �d ft � 1983 © BYTE Publications Inc Circle 127 on Inquiry card. Circle 75 on Inquirycard. April 235 Circle 422 on Inquiry card.

Protection and data typing are prac ment descriptors (called a cache). If tically nonexistent. You can only you reference a map cell held in one write-inhibit segments. Any distinc of these registers, there's no Specials of tion between code and data or user translation-time penalty . and supervisor happens at the pro Because the iAPX 286, like the • Atari 400 with 32K . . the Month. S239 cessor level -this makes security less 8086, uses segment registers, your • Atari 1200XL Computer effective. program must load these registers with 64K ...... S695 The MC68451's multiuser facilities prior to memory access. Only • 32K RAM Board for and fast context switching make WS branching instructions allow you to Atari 400/800 . s ...... 50 Clock a possible paging strategy . But specify a full 32-bit virtual address. • TSI Marketing Combo you must build an extra data struc Segment-register management has Special Includes Com #l ture to hold reference times to sup two negative aspects: segment modore 64 Computer and port this approach. Though the control code clutters a program and 1530 Datassette MC68451 is short on facilities to fully net translation time grows. Compilers Recorder ...... SSJS protect data resources, you are com normally solve the first problem. The • TSI Marketing Combo pensated by more features for virtual time problem is more of a nuisance. Special #2 Includes Com memory . Also, its architecture The iAPX 286 features excellent modore 64 Computer and 1541 Disk Drive delivers functions conducive to VS(n} virtual-memory support. Map cells ... s759 designs. have 16 undefined bits that you can

tori r::ornpuler w1th 4RK P0rn $489 use for several purposes. For in A 8CYl $409 The Intel iAPX 286 Alan �I() DISk Dnve stance, 12 to 14 bits would be suffi Alrm 4()() with I�K $210 The Intel iAPX 286 constitutes a cient for an LREF field. You could tan $140 A V1s1 \ale C>X50�9 complete virtual-memory processor also allocate a fix bit to lock special $155 C:>mmodore VlC-?0 that I believe supplies the best fea pages into MM (e.g., a supervisor Commodore M $459 ::o mmodore Dotasselle Recorder $69 tures available in the microcomputer kernel program or an LOT table). C0mmndore $349 world today. What I consider most 15111 Disk Dnve Used and segment present bits are amazing is the fact that the memory supplied, but a changed bit is notice control unit is practically identical to ably absent. CALL FOR OTHER LOW a Burroughs BSSOO mainframe sys The Intel product represents a PRICES ON ADDmONAL tem -a highly t0uted segmented ar superb tool for building virtual mem ITEMS NOT USTED chitecture. Benefits are numerous and ory. Drawbacks are minor: small problems sparse. To summarize, I'll Remarkable-Microcomputer cache size, the need · for segment Printouts with Real Character. list the principal advantages: register management, and no changed SMITH-CORONA(>) TP-1™ bit. And the device is easy to pro Daisy Wheel Printer • it has an integrated processor I gram. Instead of an 1!0 program to MMU design using the 8086 micro operate a separate MMU, you do sim SAVE S pmcessm, one 0f the. most popular ple loads and stores of memory. The OUR S300 PRICE 16-bit processors, making it compati iAPX 286's integrated approach, its 5 5 ble with existing software numerous features, and its regular Matnx 9 $420 0kldola 82A Dol Pnnler • it has a gigantic (1-gigabyte) ad design comprise an impressive com not $375 Gemim 100 rPS Mnlri> Pnn!Pr dress space puting engine.

wrlh $320 • memory segments can· be sized with .Amdec Colm l Monrlnr ;,o• mrl Mnnllor wJI�l Snunrl $315 NE('Cl2 7074 rotor a resolution of 1 byte, making it ideal Evaluation NEC M 0 nor h : n me JB1201 Mnmtor for pmgram modules Which MMU should you choose? wilh Sotmd $169 • it features advanced data-protec The answer depends on various fac tion measures: four priority levels tors. Above all else, the companion DISPLAYPHONE "A Telephone Computer Terminal in One" and several data attributes microprocessor sways this decision. & • it can completely support WS Get a system with a processor you S Ciock and VS(n) designs like-it influences your software and ?M �E operating-system selections. Perfor SL9Q5 Sold Nationally fnr 5 The iAPX 286's local data table mance requirements and intended ap J39 (LOT) register points to a map table p,lications are important. Is the TSI Marketing residing in MM. There's also a global multitasking level a factor? Do you 1560TEANECK RD. equivalent 0f this (GOT) for shared want the flexibility of segmentation TEANECK, NEW JERSEY 07666 (201) 837-0032 segments. You can define up to or the simplicity of paging? What

Cash Check . Money Order 16,384 active segments per user. The software policies or peripheral com TERMS Of SAl E Visn Credit Card OMaslrdeersr cNm d . nnde i e nts Add 4% lnr number of users is almost boundless. ponents fit your needs? Table 5 com J R s d Adrl 6% <;.:JlesTax SHIPPING AND HANDl.INC.; tor FHst 31bs Four fast internal processor registers pares the MMU products. The Fl\lS S 40 for Fnch AdrlPo•.md S30 0Fycess S hippmg C h nrges Additionrtl hold the most recently accessed seg- Will P.e Refunded evaluation offers a yardstick for

April 1983 l-36 © SYTF. Publk>tions In< sor-based computer systems. The MEMORY-MANAGEMENT UNITS memory-management units I've re OVERALL Intel Motorola Zilog Zilog viewed here lay the foundation by RATI NGS iAPX 286 MC68451 Z8010 Z80151PMMU supplying the essential hardware Virtual-memory features Excellent Good Poor Average Support for the Clock components. page-replacement Some people claim that virtual algorithm Excellent Excellent Good Excellent Support for the WS-Ciock memory fails to provide good perfor algorithm· Excellent Good Poor Poor mance. I disagree. A carefully de VS(n) architecture Excellent Good Poor NA signed unit, properly tuned (e.g., Device features and with the proper parameter for the performance e Translation speed Excellent Poor Good Average WS-Clock algorithm), should actual Address space Excellent Good Poor Average ly improve a system's operation. Block resolution Excellent Good Average NA Mapping strategy Good Excellent Average Excellent MMUs, sophisticated microproces Companion processor sors, and simple management policies Popularity Excellent Good Average Average collectively supply the elements that Architectural design Average Excellent Good Good Multiuser capability Excellent Excellent Average Average make virtual systems viable and in Design flexibility Good Good Average Poor evitable. A wider range of advanced Expansion potential NA Good Average Good applications becomes feasible. Protection features Excellent Average Good Good Ease of programming Excellent Average Good Good Which MMU is the best is not total Hardware requirements Excellent Good Poor Good ly clear. Obviously, the iAPX 286 of Complexity (board level) Excellent Good Poor Average fers some outstanding features. How Page-fault overhead Good Excellent Poor Poor ever, your intended applications and Table 5: An overall comparison of the four memory-management units surveyed in software considerations should figure this article. This evaluation highlights the differences between each MMU and gives prominently when you make your you an idea of the application possibilities. determination. A big memory space presents a new analyzing p·otential applications. You could run in the separate logical software frontier. With these new can draw your own conclusions on address spaces concurrently. Think of MMU devices, it will soon be possible how well each device addresses it, CP/M for one user, Xenix for an to have the processing power of a virtual-memory concepts. other, Oasis-16 over there. The IBM mainframe in the size of a desktop. • 370/VM (virtual machine) applies New Horizons this approach with good success. Virtual memory opens up a whole Virtual microcomputers give you References new world for microcomputer sys many other unique software avenues. 1 . Carr, R. and J. Hennessy. tems. The expanded address space ac Consider the memory needs of a 1K "WSCLOCK-A Simple and Effective commodates traditional large-scale by 1K-byte color graphics system. Algorithm for Virtual Memory Manage· software applications: database-man With various shades and colors, you ment." Proceedings of the 8th Sym agement systems, sophisticated oper will quickly consume 1 megabyte of posium on Operating Systems Prin ciples, ACM, Vol . 15, No. 5, December ating systems, and complex high memory. And how about the trend 1981, pp. 87-95. level-language translators. Moreover, toward integrated business environ 2. Denning, P. "Working Sets Past and some unique applications of virtual ments? Word processing, report gen Present." IEEE Transactions on Soft· memory exist for microcomputer eration, spreadsheet analysis, elec ware Engineering , Vol. SE-6, No. 1, systems. tronic filing, etc., collectively take a January 1980, pp. 64-84 . Virtual storage streamlines data sizable amount of storage. 3. Easton, M. and P. Franaszek. "Use Bit base operations. For example, you When will virtual microcomputers Scanning in Replacement Decisions." IEEE Transactions on Software don't have to use complex file-access be avaiJable? They are right now. · Engineering, Vol. C-28, No. 2, February techniques to locate data. A 1-giga Altos Computer Systems, Integrated 1979, pp. 133-141 . byte address space defines an enor Business Computers (IBC), and 4. · Hellerman, H. and T. Conroy. Computer mous amount of information. Ap Plexus all feature virtual systems de System Performance. New York: plications can be much bigger and signed around the Motorola McGraw-Hill, 1975. retrieval time much faster. MC68000 processor. IBM has been 5. Intel iAPX 286 Preliminary Users Manual. Santa Clara, CA: Intel Corpora A VS(n) design has very exciting looking at the iAPX 286 with some in tion, 1981 . terest, and its future microcomputer implications for microcomputers. 6. Motorola MC68451, Advance Informa You may have observed the trend systems should prove interesting. The tion. Austin, TX: Motorola Inc., 1981. among microcomputer vendors to of trend is just beginning. 7. Z80 15 Paged Memory Man{igement fer a choice of several of the leading Unit, Product Specification . Campbell, operating systems with their hard Conclusion CA: Zilog Inc., 1981 . ware. With a VS(n) organization, Virtual memory will play vital 8. Zilog 1982183 Data Book. Campbell, CA: a Zilog Inc., 1982. several different operating systems role in the evolution of microproces-