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Evolution of Defenses Against Transient-Execution Attacks

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Evolution of Defenses Against Transient-Execution Attacks Evolution of Defenses against Transient-Execution Attacks Claudio Canella Sai Manoj Pudukotai Dinakarrao Graz University of Technology, Austria George Mason University, USA [email protected] [email protected] Daniel Gruss Khaled N. Khasawneh Graz University of Technology, Austria George Mason University, USA [email protected] [email protected] ABSTRACT The initial discovery of transient-execution attacks, i.e., Melt- Transient-execution attacks, such as Meltdown and Spectre, exploit down and Spectre, became one of the most complex and largest performance optimizations in modern CPUs to enable unauthorized industry-wide embargos as processors from various manufacturers access to data across protection boundaries. Against these attacks, turned out to be affected. As a result, many attacks variants were we have noticed a rapid growth of deployed and proposed counter- discovered, but more noticeable is the proliferation of countermea- measures. In this paper, we show the evolution of countermeasures sures from both industry and academia. Given the large number and against transient-execution attacks by both industry and academia the rapid growth of both adopted and proposed countermeasures, since the initial discoveries of the attacks. We show that despite a systematic view is required to understand the scope of current the advances in the understanding and systematic view of the field, defenses and facilitate the evaluation of future defenses. the proposed and deployed defenses are limited. In this paper, we show how the landscape of countermeasures against transient-execution attacks evolved since the initial discov- KEYWORDS eries of the attacks. We build our systematization based on a con- current 6-phase generalization of transient-execution attacks [16]. Transient-execution attacks, Meltdown, Spectre, LVI We systematically describe hardware- and software-based coun- ACM Reference Format: termeasure advances from both industry and academia. Beyond Claudio Canella, Sai Manoj Pudukotai Dinakarrao, Daniel Gruss, and Khaled previous work [18, 99], our systematic view does not only cover N. Khasawneh. 2020. Evolution of Defenses against Transient-Execution Spectre and Meltdown defenses but also LVI defenses. We show Attacks. In Great Lakes Symposium on VLSI 2020 (GLSVLSI ’20), September that despite the advances in the understanding and systematic view 7–9, 2020, Virtual Event, China. ACM, New York, NY, USA,6 pages. https: of the field, the proposed and deployed defenses are limited. //doi.org/10.1145/XXXXXX.XXXXXX Outline. First, we briefly discuss background in Section2. The paper then gives a systematic overview of countermeasures for 1 INTRODUCTION Spectre (Section3), Meltdown (Section4), and LVI (Section5). We Transient execution enables unauthorized access to data across conclude in Section6. security protection boundaries. Transient execution refers to the execution of instructions that will eventually get squashed, i.e., 2 BACKGROUND their execution results will not be committed to the architectural Out-of-order and speculative execution. To increase perfor- state. Nonetheless, transient execution can leave a trace in the mance, modern CPUs rely on features like speculative and out- microarchitectural state, e.g., the cache state. Therefore, transient- of-order execution. With speculative execution, CPUs try to predict execution attacks utilize the execution of transient instructions to the outcome of a potential control-flow change to start the ex- access secret data, e.g., a password, and leave a secret-dependent ecution of the likely path instead of stalling. For that, the CPU trace in the microarchitectural state that can be recovered later provides various predictors that together comprise the Branch Pre- using non-transient execution. These attacks can be classified into diction Unit (BPU) [18]. Out-of-order execution allows executing three main classes, namely Meltdown, Spectre, and Load Value later instructions that are ready to be executed due to the operands Injection (LVI), based on the nature of the transient execution and being available in advance, but still requires to retire them in order. the attack direction. Spectre is based on misprediction in the victim Recently, these optimizations have resulted in various transient- domain, Meltdown is based on faults and assists in the attacker execution attacks [18, 55, 60]. domain, and LVI is based on faults and assists in the victim domain. Transient-execution attacks. Transient-execution attacks exploit modern CPUs performance optimizations to enable unauthorized Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed access to data across protection boundaries. According to a con- for profit or commercial advantage and that copies bear this notice and the full citation current generalization of transient-execution attacks, these attacks on the first page. Copyrights for components of this work owned by others than ACM consist of 6 distinct phases [16]: Phase 1 (preparation): preparing the must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a micro-architecture to enter transient execution, Phase 2 (misspecu- fee. Request permissions from [email protected]. lation): triggering transient execution using a trigger instruction, GLSVLSI ’20, September 7–9, 2020, Virtual Event, China Phase 3 (access): accessing data of interest, Phase 4 (encoding): encod- © 2020 Association for Computing Machinery. ACM ISBN 978-1-4503-7944-1/20/09...$15.00 ing data of interest in the microarchitecture state, Phase 5 (leakage): https://doi.org/10.1145/XXXXXX.XXXXXX end of transient window, i.e., the architectural changes are reverted and the pipeline is flushed, and Phase 6 (decoding): decoding the efficient alternative. Due to its probabilistic nature, randpoline does microarchitectural state to the architectural state. not fully mitigate Spectre-BTB but only reduces success and leak- age rates of attacks. Linux and Windows use retpoline on affected 3 SPECTRE COUNTERMEASURES machines by default [24, 43]. A countermeasure can try to break any phase of a Spectre at- Hardware-based defenses. Both Intel and AMD described fencing- tack [16]: preparation, misspeculation, access, encoding, leakage, based solutions [4, 47]. However, they also both introduced new decoding. However, targeting different phases has different effects architectural features to constrain speculative execution on the on security. As the following discussion also shows, mitigating all microarchitectural level including instructions for synchronization Spectre attacks in practice likely will remain an open problem in barriers for data (DSB) and instructions (ISB), broader speculation the foreseeable future [62]. barriers (CSDB)[8], new registers to restrict speculative execution and instructions to restrain control-flow (cfp) and data value (dvp) 3.1 Preparation Prevention (Phase 1) prediction, and cache prefetches (cpp)[7]. Even more broadly, both serialize sb Phase 1 prepares the microarchitecture, e.g., the cache or branch Intel (with ) and ARMv8.5-A [7] (with ) introduced predictors, for the attack. Defenses targeting this phase usually generic speculative execution barriers. do not prevent this step entirely but only eliminate the attacker’s On future CPUs with Control-flow Enforcement Technology influence on the victim domain. However, some variants do notre- (CET) capabilities, retpoline might trigger false positives in the CET quire any preparation or run in-place, making it hard to distinguish defenses [43]. Therefore, these CPUs implement enhanced IBRS, a malicious training from benign execution. hardware defense for Spectre-BTB [43]. Intel [43] also provided a microcode update against Spectre-RSB to stop speculation. How- 3.1.1 Industry. To prevent mistraining, the industry, e.g., Intel ever, on Skylake and newer architectures, the RSB may fall back to and AMD, extended ISAs with a mechanism for controlling in- the BTB, re-enabling Spectre-BTB attacks via return instructions. direct branches [4, 44]. Indirect Branch Restricted Speculation To prevent this, the RSB is stuffed with the address of a benign (IBRS) prevents unprivileged code from influencing the predic- gadget when entering the kernel [43]. tion of privileged code. Single Thread Indirect Branch Prediction (STIBP) restricts sharing of branch prediction mechanisms across hyperthreads. The Indirect Branch Predictor Barrier (IBPB) pre- 3.2.2 Academia. Academia helped identifying limitations of the vents code that executes before it from affecting the prediction of deployed serializing countermeasures [82]. Furthermore, they pro- code following it. Some ARM CPUs implement specific controls posed techniques to reduce the overhead of such defenses. that invalidate the branch predictor, which should be used during Software-based defenses. Schwarz et al. [82] showed that lfence context switches [8]. Linux enabled those by default [52]. instructions only stop execution units from running subsequent For Spectre-STL, ARM introduced new barrier instructions and operations. Thus, fetch and decode still work, potentially leaking control registers to prevent the re-ordering of loads and stores [8]. data through the power-up of AVX functional units, the TLB, or Likewise, Intel [44] and AMD [3]
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