A Detailed Power Model for Field Programmable Gate Arrays
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Optimization of Combinational Logic Circuits Based on Compatible Gates
COMPUTER SYSTEMS LABORATORY STANFORD UNIVERSITY STANFORD, CA 94305455 Optimization of Combinational Logic Circuits Based on Compatible Gates Maurizio Damiani Jerry Chih-Yuan Yang Giovanni De Micheli Technical Report: CSL-TR-93-584 September 1993 This research is sponsored by NSF and DEC under a PYI award and by ARPA and NSF under contract MIP 9115432. Optimization of Combinational Logic Circuits Based on Compatible Gates Maurizio Damiani * Jerry Chih- Yuan Yang Giovanni De Micheli Technical Report: CSL-TR-93-584 September, 1993 Computer Systems Laboratory Departments of Electrical Engineering and Computer Science Stanford University, Stanford CA 94305-4055 Abstract This paper presents a set of new techniques for the optimization of multiple-level combinational Boolean networks. We describe first a technique based upon the selection of appropriate multiple- output subnetworks (consisting of so-called compatible gates) whose local functions can be op- timized simultaneously. We then generalize the method to larger and more arbitrary subsets of gates. Because simultaneous optimization of local functions can take place, our methods are more powerful and general than Boolean optimization methods using don’t cares , where only single-gate optimization can be performed. In addition, our methods represent a more efficient alternative to optimization procedures based on Boolean relations because the problem can be modeled by a unate covering problem instead of the more difficult binate covering problem. The method is implemented in program ACHILLES and compares favorably to SIS. Key Words and Phrases: Combinational logic synthesis, don’t care methods. *Now with the Dipartimento di Elettronica ed Informatica, UniversitB di Padova, Via Gradenigo 6/A, Padova, Italy. -
Logic Optimization and Synthesis: Trends and Directions in Industry
Logic Optimization and Synthesis: Trends and Directions in Industry Luca Amaru´∗, Patrick Vuillod†, Jiong Luo∗, Janet Olson∗ ∗ Synopsys Inc., Design Group, Sunnyvale, California, USA † Synopsys Inc., Design Group, Grenoble, France Abstract—Logic synthesis is a key design step which optimizes of specific logic styles and cell layouts. Embedding as much abstract circuit representations and links them to technology. technology information as possible early in the logic optimiza- With CMOS technology moving into the deep nanometer regime, tion engine is key to make advantageous logic restructuring logic synthesis needs to be aware of physical informations early in the flow. With the rise of enhanced functionality nanodevices, opportunities carry over at the end of the design flow. research on technology needs the help of logic synthesis to capture In this paper, we examine the synergy between logic synthe- advantageous design opportunities. This paper deals with the syn- sis and technology, from an industrial perspective. We present ergy between logic synthesis and technology, from an industrial technology aware synthesis methods incorporating advanced perspective. First, we present new synthesis techniques which physical information at the core optimization engine. Internal embed detailed physical informations at the core optimization engine. Experiments show improved Quality of Results (QoR) and results evidence faster timing closure and better correlation better correlation between RTL synthesis and physical implemen- between RTL synthesis and physical implementation. We elab- tation. Second, we discuss the application of these new synthesis orate on synthesis aware technology development, where logic techniques in the early assessment of emerging nanodevices with synthesis enables a fair system-level assessment on emerging enhanced functionality. -
Characterization Quaternaty Lookup Table in Standard Cmos Process
International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 02 Issue: 07 | Oct-2015 www.irjet.net p-ISSN: 2395-0072 CHARACTERIZATION QUATERNATY LOOKUP TABLE IN STANDARD CMOS PROCESS S.Prabhu Venkateswaran1, R.Selvarani2 1Assitant Professor, Electronics and Communication Engineering, SNS College of Technology,Tamil Nadu, India 2 PG Scholar, VLSI Design, SNS College Of Technology, Tamil Nadu, India -------------------------------------------------------------------------**------------------------------------------------------------------------ Abstract- The Binary logics and devices have been process gets low power and easy to scale down, gate of developed with an latest technology and gate design MOS need much lower driving current than base current of area. The design and implementation of logical circuits two polar, scaling down increase CMOS speed Comparing become easier and compact. Therefore present logic MVL present high power consumption, due to current devices that can implement in binary and multi valued mode circuit element or require nonstandard multi logic system. In multi-valued logic system logic gates threshold CMOS technologies. multiple-value logic are increase the high power required for level of transition varies in different logic systems, a quaternary has and increase the number of required interconnections become mature in terms of logic algebra and gates. ,hence also increasing the overall energy. Interconnections Some multi valued logic systems such as ternary and are increase the dominant contributor to delay are and quaternary logic schemes have been developed. energy consumption in CMOS digital circuit. Quaternary logic has many advantages over binary logic. Since it require half the number of digits to store 2. QUATERNARY LOGIC AND LUTs any information than its binary equivalent it is best for storage; the quaternary storage mechanism is less than Ternary logic system: It is based upon CMOS compatible twice as complex as the binary system. -
A Reduced-Complexity Lookup Table Approach to Solving Mathematical Functions in Fpgas
A reduced-complexity lookup table approach to solving mathematical functions in FPGAs Michael Low, Jim P. Y. Lee Defence R&D Canada --- Ottawa Technical Memorandum DRDC Ottawa TM 2008-261 December 2008 A reduced-complexity lookup table approach to solving mathematical functions in FPGAs Michael Low Jim P. Y. Lee DRDC Ottawa Defence R&D Canada – Ottawa Technical Memorandum DRDC Ottawa TM 2008-261 December 2008 Principal Author Original signed by Michael Low Michael Low Defence Scientist, Radar Electronic Warfare Approved by Original signed by Jean-F. Rivest Jean-F. Rivest Head, Radar Electronic Warfare Approved for release by Original signed by Pierre Lavoie Pierre Lavoie Chief Scientist, DRDC Ottawa © Her Majesty the Queen in Right of Canada, as represented by the Minister of National Defence, 2008 © Sa Majesté la Reine (en droit du Canada), telle que représentée par le ministre de la Défense nationale, 2008 Abstract …….. Certain mathematical functions, such as the inverse, log, and arctangent, have traditionally been implemented in the digital domain using the Coordinate Rotation Digital Computer (CORDIC) algorithm. In this study, it is shown that it is possible to achieve a similar degree of numerical accuracy using a reduced-complexity lookup table (RCLT) algorithm, which is much less computationally-intensive than the CORDIC. On programmable digital signal processor (DSP) chips, this reduces computation time. On field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs), this reduces the consumption of hardware resources. This paper presents the results of a study in which three commonly-used functions, i.e. inverse, log, and arctangent functions, have been synthesized for the Xilinx Virtex-II family of FPGAs, using both the RCLT and CORDIC implementations. -
Basic Boolean Algebra and Logic Optimization
Fundamental Algorithms for System Modeling, Analysis, and Optimization Edward A. Lee, Jaijeet Roychowdhury, Sanjit A. Seshia UC Berkeley EECS 144/244 Fall 2011 Copyright © 2010-11, E. A. Lee, J. Roychowdhury, S. A. Seshia, All rights reserved Lec 3: Boolean Algebra and Logic Optimization - 1 Thanks to S. Devadas, K. Keutzer, S. Malik, R. Rutenbar for several slides RTL Synthesis Flow FSM, HDL Verilog, HDL Simulation/ VHDL Verification RTL Synthesis a 0 d q Boolean circuit/network 1 netlist b Library/ s clk module logic generators optimization a 0 d q Boolean circuit/network netlist b 1 s clk physical design Graph / Rectangles layout K. Keutzer EECS 144/244, UC Berkeley: 2 Reduce Sequential Ckt Optimization to Combinational Optimization B Flip-flops inputs Combinational outputs Logic Optimize the size/delay/etc. of the combinational circuit (viewed as a Boolean network) EECS 144/244, UC Berkeley: 3 Logic Optimization 2-level Logic opt netlist tech multilevel independent Logic opt logic Library optimization tech dependent Generic Library netlist Real Library EECS 144/244, UC Berkeley: 4 Outline of Topics Basics of Boolean algebra Two-level logic optimization Multi-level logic optimization Boolean function representation: BDDs EECS 144/244, UC Berkeley: 5 Definitions – 1: What is a Boolean function? EECS 144/244, UC Berkeley: 6 Definitions – 1: What is a Boolean function? Let B = {0, 1} and Y = {0, 1} Input variables: X1, X2 …Xn Output variables: Y1, Y2 …Ym A logic function ff (or ‘Boolean’ function, switching function) in n inputs and m -
The Basics of Logic Design
C APPENDIX The Basics of Logic Design C.1 Introduction C-3 I always loved that C.2 Gates, Truth Tables, and Logic word, Boolean. Equations C-4 C.3 Combinational Logic C-9 Claude Shannon C.4 Using a Hardware Description IEEE Spectrum, April 1992 Language (Shannon’s master’s thesis showed that C-20 the algebra invented by George Boole in C.5 Constructing a Basic Arithmetic Logic the 1800s could represent the workings of Unit C-26 electrical switches.) C.6 Faster Addition: Carry Lookahead C-38 C.7 Clocks C-48 AAppendixC-9780123747501.inddppendixC-9780123747501.indd 2 226/07/116/07/11 66:28:28 PPMM C.8 Memory Elements: Flip-Flops, Latches, and Registers C-50 C.9 Memory Elements: SRAMs and DRAMs C-58 C.10 Finite-State Machines C-67 C.11 Timing Methodologies C-72 C.12 Field Programmable Devices C-78 C.13 Concluding Remarks C-79 C.14 Exercises C-80 C.1 Introduction This appendix provides a brief discussion of the basics of logic design. It does not replace a course in logic design, nor will it enable you to design signifi cant working logic systems. If you have little or no exposure to logic design, however, this appendix will provide suffi cient background to understand all the material in this book. In addition, if you are looking to understand some of the motivation behind how computers are implemented, this material will serve as a useful intro- duction. If your curiosity is aroused but not sated by this appendix, the references at the end provide several additional sources of information. -
Gate Logic Logic Optimization Overview
Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles- or any text in boolean algebra Introduction We could design at the level of irsim - Think about transistors as switches - Build collections of switches that do useful stuff - Don’t much care whether the collection of transistors is a gate, switch logic, or some combination. It is a collection of switches. But this is pretty complicated - Switches are bidirectional, charge-sharing, - Need to worry about series resistance… MAH, AEN EE271 Lecture 5 2 Logic Gates Constrain the problem to simplify it. • Constrain how one can connect transistors - Create a collection of transistors where the Output is always driven by a switch-network to a supply (not an input) And the inputs to this unit only connect the gate of the transistors • Model this collection of transistors by a simpler abstraction Units are unidirectional Function is modelled by boolean operations Capacitance only affects speed and not functionality Delay through network is sum of delays of elements This abstract model is one we have used already. • It is a logic gate MAH, AEN EE271 Lecture 5 3 Logic Gates Come in various forms and sizes In CMOS, all of the primitive gates1 have one inversion from each input to the output. There are many versions of primitive gates. Different libraries have different collections. In general, most libraries have all 3 input gates (NAND, NOR, AOI, and OAI gates) and some 4 input gates. Most libraries are much richer, and have a large number of gates. -
AC Induction Motor Control Using the Constant V/F Principle and a Natural
AVR494: AC Induction Motor Control Using the constant V/f Principle and a Natural PWM Algorithm 8-bit Microcontrollers Features • Cost-effective and flexible 3-phase induction motor drive • Interrupt driven Application Note • Low memory and computing requirements 1. Introduction Electrical power has been used for a long time to produce mechanical motion (either rotation or translation), thanks to electromechanical actuators. It is estimated that 50% of the electrical power produced in the United States is consumed by electrical motors. More than 50 motors can typically be found in a house, and nearly as many in a car. To preserve the environment and to reduce green-house effect gas emissions, gov- ernments around the world are introducing regulations requiring white goods manufacturers and industrial factories to produce more energy efficient appliances. Most often, this goal can be reached by an efficient drive and control of the motor speed. This is the reason why appliance designers and semiconductor suppliers are now interested by the design of low-cost and energy-efficient variable speed drives. Because of their high robustness, reliability, low cost and high efficiency (≈ 80%), AC induction motors are used in many industrial applications such as • appliances (washers, blowers, refrigerators, fans, vacuum cleaners, compressors …); • HVAC (heating, ventilation and air conditioning); • industrial drives (motion control, centrifugal pumps, robotics, …); • automotive control (electric vehicles) However, induction motors can only run at their rated speed when they are connected to the main power supply. This is the reason why variable frequency drives are needed to vary the rotor speed of an induction motor. The most popular algorithm for the control of a three-phase induction motor is the V/f control approach using a natural pulse-width modulation (PWM) technique to drive a voltage-source inverter (VSI), as shown on Figure 1-1. -
Binary Search Algorithm Anthony Lin¹* Et Al
WikiJournal of Science, 2019, 2(1):5 doi: 10.15347/wjs/2019.005 Encyclopedic Review Article Binary search algorithm Anthony Lin¹* et al. Abstract In In computer science, binary search, also known as half-interval search,[1] logarithmic search,[2] or binary chop,[3] is a search algorithm that finds a position of a target value within a sorted array.[4] Binary search compares the target value to an element in the middle of the array. If they are not equal, the half in which the target cannot lie is eliminated and the search continues on the remaining half, again taking the middle element to compare to the target value, and repeating this until the target value is found. If the search ends with the remaining half being empty, the target is not in the array. Binary search runs in logarithmic time in the worst case, making 푂(log 푛) comparisons, where 푛 is the number of elements in the array, the 푂 is ‘Big O’ notation, and 푙표푔 is the logarithm.[5] Binary search is faster than linear search except for small arrays. However, the array must be sorted first to be able to apply binary search. There are spe- cialized data structures designed for fast searching, such as hash tables, that can be searched more efficiently than binary search. However, binary search can be used to solve a wider range of problems, such as finding the next- smallest or next-largest element in the array relative to the target even if it is absent from the array. There are numerous variations of binary search. -
Deep Learning for Logic Optimization Algorithms
Deep Learning for Logic Optimization Algorithms Winston Haaswijky∗, Edo Collinsz∗, Benoit Seguinx∗, Mathias Soekeny, Fred´ eric´ Kaplanx, Sabine Susstrunk¨ z, Giovanni De Micheliy yIntegrated Systems Laboratory, EPFL, Lausanne, VD, Switzerland zImage and Visual Representation Lab, EPFL, Lausanne, VD, Switzerland xDigital Humanities Laboratory, EPFL, Lausanne, VD, Switzerland ∗These authors contributed equally to this work Abstract—The slowing down of Moore’s law and the emergence to the state-of-the-art. Finally, our algorithm is a generic of new technologies puts an increasing pressure on the field optimization method. We show that it is capable of performing of EDA. There is a constant need to improve optimization depth optimization, obtaining 92.6% of potential improvement algorithms. However, finding and implementing such algorithms is a difficult task, especially with the novel logic primitives and in depth optimization of 3-input functions. Further, the MCNC potentially unconventional requirements of emerging technolo- case study shows that we unlock significant depth improvements gies. In this paper, we cast logic optimization as a deterministic over the academic state-of-the-art, ranging from 12.5% to Markov decision process (MDP). We then take advantage of 47.4%. recent advances in deep reinforcement learning to build a system that learns how to navigate this process. Our design has a II. BACKGROUND number of desirable properties. It is autonomous because it learns automatically and does not require human intervention. A. Deep Learning It generalizes to large functions after training on small examples. With ever growing data sets and increasing computational Additionally, it intrinsically supports both single- and multi- output functions, without the need to handle special cases. -
A ' Microprocessor-Based Lookup Bearing Table
NASA Technical Paper 1838 A'Microprocessor-Based Table Lookup Approach . for Magnetic Bearing Linearization . -. Nelson J. Groom and, James B. Miller .- MAY 1981 NASA .. TECH LIBRARY KAFB, NM NASA Technical Paper 1838 A Microprocessor-BasedTable Lookup Approach for. Magnetic BearingLinearization Nelson J. Groom and James B. Miller LarrgleyResearch Ceuter Hatnpton,Virgilria National Aeronautics and Space Administration Scientific and Technical Information Branch 1981 SUMMARY An approach forproduci ng a linear transfer chlar acteristic between force command and force output of a magnetic bearing actuator without flux biasing is pres.ented. The approach is mlcroprocessor based and uses a table 'lookup to generatedrive signals for the magnetiCbearing power driver. An experimental test setup used to demonstrate the feasibility of the approach is described, and testresults are presented. The testsetup contains bearing elements simi- lar to those used in a laboratory model annular momentum control device (AMCD) . INTRODUCTION ,. This paper describes an approach for producing a lineartransfer charac- teristic between the force command and force output of a magneticbearing actuator. The approach, which is microprocessor based and uses a table lookup to generate drive signals for the magneticbearing actuator power driver, was investigated for application to a laboratory model annular momentum control device (AKD) . The laboratory model (described in ref. 1 ) was built to inves- tigate potential problem areas in implementing the AMCD concept and is being used aspart ofan AKD hardware technology development program. The basic AMCD concept is that of a rotating annular rim,suspended by a minimum of three magneticbearing suspension stations and driven by a noncontacting elec- tromagneticspin motor. -
Design and Implementation of Improved NCO Based on FPGA
Advances in Computer Science Research (ACSR), volume 90 3rd International Conference on Computer Engineering, Information Science & Application Technology (ICCIA 2019) Design and Implementation of Improved NCO based on FPGA Yanshuang Chen a, Jun Yang b, * School of Information Science and Engineering Yunnan University, Yun'nanKunming650091, China a [email protected], b, * [email protected] Abstract. A numerically controlled oscillator (NCO) is used to generate quadrature controllable sine and cosine waves and is an important part of software radio. The traditional NCO module is implemented based on the lookup table structure, which requires a large amount of hardware storage resources inside the FPGA. Therefore, the CORDIC algorithm is used to implement the NCO module, and the output accuracy is improved by improving the CORDIC algorithm. At the same time, the FPGA technology is characterized by strong reconfigurability, good scalability, low hardware resources. The module is designed with Verilog HDL language. Finally, the NCO model based on FPGA design has the characteristics of low hardware resource consumption and high output precision. The model was simulated by Modelsim and downloaded to the target chip verification of Altera DE2's EP2C35F672C6. The digitally controlled oscillator met the design requirements. Keywords: Digital controlled oscillator (NCO); CORDIC algorithm; Pipeline structure; FPGA; precision. 1. Introduction The numerically controlled oscillator (NCO) is an important component of the signal processing system [1], and is mainly used to generate orthogonally controllable sine and cosine waves. With the continuous development of modern communication systems, digital control oscillators have been widely used in digital communication, signal processing and other fields as an important part of software radio [2].