130 nm and 90 nm CMOS Technologies 1 Università di Bergamo Dipartimento di Ingegneria Industriale Via Marconi 5, 24044 Dalmine (BG), Italy for Detector Front-end Applications 3 INFN Sezione di Pavia Via Bassi 6, 27100 Pavia, Italy M. Manghisoni 1,3 , E. Baldi 2,3 , L. Ratti 2,3 , V. Re 1,3 , V. Speziali 2,3 , G. Traversi 1,3 2 Università di Pavia Dipartimento di Elettronica [email protected], [email protected], [email protected], [email protected], [email protected], [email protected] Via Ferrata 1, 27100 Pavia, Italy

Introduction Experimental Details

 CMOS commercial technologies of the quarter micron node have been extensively used for the implementation of  studied belong to two standard CMOS processes by STMicroelectronics with 130 nm and

radiation tolerant, low noise, low power readout circuits with very high channel density for analog and digital 90 nm minimum feature size. The oxide thickness tOX is 2.4 and 2.0 nm, and the gate capacitance per 2 processing in pixel and microstrip detectors. unit area C OX is about 14.8 and 17.7 fF/µm respectively.  The IC designers’ effort is presently shifting to 130 nm CMOS technologies, or even to the next technology node, to  In the PMOS and NMOS devices with gate lengths L from 0.13 to 1 µm and gate implement readout integrated circuits for strip and pixel detectors, in view of future HEP applications widths W of 200, 600 and 1000 µm were investigated. In the devices of both polarities (SLHC, Linear Collider, Super B-Factory) . with gate lengths L from 0.10 to 0.7 µm and gate widths W of 200 and 600 µm were characterized. In  In this work the results of noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial both processes, transistors were laid out using a standard open structure configuration. processes are analysed to provide an evaluation of the impact of technology scaling on the analog performances of  The device parameters were characterized at drain currents from several tens of µA to 1 mA, that is, a future generation of front-end chips. The behavior of 1/f and channel thermal noise parameters is studied to the usual operating currents of input MOSFETs in integrated charge-sensitive amplifiers. assess the effects of quality and short-channel phenomena in CMOS processes with different gate oxide thickness and minimum channel length. Experimental Results

Transconductance and Device Operating Region Noise Equations

 Transconductance behavior depends on the The noise performances of a MOS device can be characterized in terms of the gate referred noise voltage spectrum: 100 inversion region where the device is operating. The Weak Inversion Law Strong Inversion Law inversion level of a MOS transistor in saturation 2 2 Kf 1 Se )f( = SW + 100 can be expressed by means of its transconductance C WL f αf NMOS OX ) NMOS efficiency g m/I D as a function of the normalized White noise 1/f noise 1/2 drain current I L/W [1]. D 1/f Slope ( α =1) [1/V] 10 10 f D 130 nm process Channel thermal noise (dominant at low current K = intrinsic process /I f

m 90 nm process  The boundary between weak and strong inversion g density) and noise in parasitic resistors [2] parameter, α = 1/f noise is expressed by I *, located at the intersection of f z Γ slope weak and strong inversion asymptotes: 2 PMOS PMOS SW = 4k BT Γ = αWnγ 1 I* I* gm Z,P 90 Z,N 90 * 2 130 nm process IZ = 2µCOX nV T 1 α ≥ 1 excess noise factor, γ ranging from 1/2 in W/L=1000/0.2 -9 -8 -7 -6 -5 W 10 10 10 10 10 NoiseVoltage Spectrum (nV/Hz I =1 mA, |V |=0.6 V µ=channel mobility, n=coeffcient proportional to the weak inversion to 2/3 in strong inversion D DS I L/W [A] D invers of the subthreshold slope of I as a function of 0.1 D 10 3 10 4 10 5 10 6 10 7 10 8 0.03 V , V =thermal voltage. GS T Noise Measurement Frequency (Hz) 0.025 130 nm process 90 nm process NMOS  Iz* is larger in devices fabricated in 90 nm ⇒ weak W/L=600/0.35 and moderate inversion regions extend to higher 0.02 |V |=0.6 V DS normalized drain currents. Noise voltage spectra were 100 100 ] 0.015 L=0.13 µm ] Id=0.10 mA measured for PMOS and 1/2 1/2 Id=0.25 mA I * [µA] L=0.35 µm z NMOS with different gate Id=1.00 mA 0.01 L=1.00 µm PMOS Process 130 nm 90 nm widths and lengths and at Transconductance [A/V] Transconductance different drain currents for 10 10 0.005 NMOS 0.55 0.75 devices belonging to both the PMOS 0.15 0.20 0 investigated technologies. 0 0.0002 0.0004 0.0006 0.0008 0.001 90 nm process Drain Current [A]  All the investigated devices are operated in weak 1 130 nm process 1 PMOS W/L=600/0.2 NMOS W=1000 µm |V |=0.6 V

Noise VoltageNoise Spectrum [nV/Hz DS Id=250 µA, V =0.6 V NoiseVoltageSpectrum [nV/Hz and moderate inversion region. DS

3 4 5 6 7 8 10 10 10 10 10 10 10 2 10 3 10 4 10 5 10 6 10 7 Analysis of Noise Measurement Results Frequency [Hz] Frequency [Hz]

White noise 1/f noise coefficient K fff White noise

40 250 250 130 nm process 35 For N-channel devices K f is: White noise is evaluated in terms of the NMOS W=1000 µm 90 nm process 90 nm process 30 90 nm process  independent of the drain equivalent noise resistance: NMOS W=600 µm PMOS W=600 µm Ω] Ω]

] 200 200 NMOS W=600 µm V =0.6 V |V |=0.6 V DS DS 25 current.

(alpha-1) 2 I varing from 0.1 to 1 mA L=0.13 µm D S nγ  larger for deviced with W 150 L=0.20 µm 150 Hz 20 L=0.20 µm V =0.6 V R eq = = αW L=0.35 µm -25 DS L=0.35 µm L<0.5 µm in the 130 nm 4k BT gm L=0.50 µm 15 L=0.70 µm L=0.50 µm process and with L<0.2 µm 100 100 L=0.70 µm Kf[J 10 10 in the 90 nm process.  White noise decreases with the increase 5  lower in the 90 nm process 50 50 of I D due to the increase of g m. Equivalent Noise [ Resistance [ Equivalent ResistanceNoise 0 by about a factor of 2. 0 0.2 0.4 0.6 0.8 1 1.2  White noise is not sizably affected by L 0 0 As-drawn Gate Length [ µm] variations since devices are operated in 0 0.2 0.4 0.6 0.8 1 1.2 0 0.2 0.4 0.6 0.8 1 1.2 Drain Current [mA] Drain Current [mA] 120 weak and moderate inversion. 300 300  α ≈ 100 For P-channel devices K is: W 1 is found for all the devices, except 250 250 f Ω] for NMOS with L=0.13 µm in the Ω] ] 130 nm process  dependent of the overdrive 80 200 PMOS 130 nm process where αW≈1.2. 200 (alpha-1) voltage V GS -VTH

Hz 60 150 150

-25  larger for deviced with

L<0.5 µm in the 130 nm 130 nm process 130 nm process 40 100 100 Kf Kf [J 10 process and with L<0.2 µm NMOS L > 0.13 µm PMOS Linear fit Linear fit 20 in the 90 nm process 50

50 Noise[ Equivalent Resistance 90 nm process Equivalent [ ResistanceNoise offset = 6.85 +/- 1.90 offset = 1.82 +/- 2.12 PMOS  lower in the 90 nm process. slope = 1.01 +/- 0.02 slope = 0.97 +/- 0.02 0 0 0 -0.05 0 0.05 0.1 0.15 0.2 0 50 100 150 200 250 300 0 50 100 150 200 250 300 Gate Overdrive Voltage [V] nγ/g [ Ω] nγ/g [ Ω] m m 1/f noise slope

2 130 nm process αf is independent of the drain W=1000 µm PMOS current and of the device 1.5 |V |=0.6 V DS geometry. References

f 1 α αf [1] V. Re, M. Manghisoni, L. Ratti, V. Speziali, G. Traversi, "Survey of noise performances and scaling effects inDeep Submicron Process 130 nm 90 nm 0.5 CMOS devices from different foundries", IEEE Trans. Nucl. Sci. , vol. 52, no. 6, pp. 2733-2740, Dec. 2005. Id=0.10 mA Id=0.75 mA NMOS NMOS 0.85 0.85 Id=0.25 mA Id=1.00 mA [2] G. De Geronimo , P. O'Connor, "MOSFET optimization in deep submicron technology for charge amplifiers", IEEE Trans. Nucl. Id=0.50 mA PMOS 1.19 1.09 0 Sci. , vol. 52, no. 6, pp. 3223-3232, Dec. 2005. 0 0.2 0.4 0.6 0.8 1 1.2 As-drawn Gate Length [ µm]

Frontier Detectors for Frontier Physics , 10 th Pisa Meeting on Advanced Detectors, La Biodola, Isola d'Elba, Italy, May 21-27, 2006.