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Multiplicand) (Multiplier Objectives: 1. Multipliers: 1.1 Multiplication of two 2-bit numbers. 1.2 Combinational circuit of binary multiplier with more bits. 2. Decoders: 2.1) 2x4 decoder (Active-high). 2.2) Active-low decoders. 2.3) Decoders with enable inputs. 2.4) Three-to-eight-line decoder circuit. 2.5) Larger decoder circuit. 2.6) Combinational logic implementation. 1) Multipliers: Multiplication of binary numbers is performed in the same way as multiplication of decimal numbers: 1.1 Multiplication of two 2-bit numbers. B 1 B 0 (Multiplicand) A 1 A 0 (Multiplier) A0 B 1 A0 B0 Partial Product A 1 B 1 A 1 B 0 Possible Carry A0 B 1 A B 0 0 A 1 B 1 A 1 B 0 C C 3 2 C 1 C 0 Final Product (the sum of the partial products) Combinational circuit The multiplication of two bits such as and produces a 1 if both bits are 1; otherwise, it produces a 0, this is identical to an AND operation. The two partial products are added with two half-adder (HA) circuits (if there are more than two bits, we must use full adder (FA)). B 0 B 1 A 0 A 1 HA HA C C 0 C 3 C 2 1 Two-bit by Two-bit binary multilplier 1.2 Combinational circuit of binary multiplier with more bits. For bits multiplier and bits multiplicand, we need: AND gates. -bits adders to produce a product of bits. Example: - Create a logic circuit for B 3 B 2 B 1 B 0 A 2 A 1 A 0 C 6 C 5 C 4 C 3 C 2 C 1 C 0 Answer Solution: So: We need 12 AND gates and 2 four-bit adders to produce a product of seven bits: . B B3 2 B 1 B 0 A 2 A 1 A 0 A B A B 0 0 3 A0 B2 A 0 B 1 0 0 12 AND A B A1 B 2 A B A B Gates 1 3 1 1 1 0 4-bit adder A B A 2 B 3 2 2 A 2 B 1 A 2 B 0 (First adder) 0 A 0 B 3 A B A B 0 2 0 1 A 1 B 3 A1 B 2 A 1 B 1 A 1 B 0 e X 3 X X 1 l 0 2 y b r i r s A B A B A B a A 2 B 3 2 2 2 1 2 0 s o C 4-bit adder P (Second adder) C C C C C C 6 5 4 3 2 1 C 0 Circuit Implementation: B 0 B 1 B2 B3 A 0 A 1 A 2 0 4-bit adder t u p t u y o r r d a n c a m u S 4-bit adder C C C C C 6 C 5 C 4 3 2 1 0 2) Decoders Information is represented in digital system by binary codes. A binary code of bits is capable of representing up to distinct elements of coded information. A decoder is a combinational circuit that covers binary information from input lines to a maximum of unique output lines. The decoders are called line decoders, where (for example BCD-to-seven-segment decoder, decoder). The purpose of the decoders is to generate the (or fewer) minterms of input variables. Decoder is a circuit that allows us to activate an output line by specifying a control word; it is either active-high or active-low. o Active-high sets a particular output to logic 1. While remaining other outputs to logic 0. o Active-low sets a particular output to logic 0, other outputs to logic 1. 2.1) 2x4 decoder (Active-high) 1. ) D 0 s d s r S0 e 2. e o n n i i W D L L 1 l 3. t t 2x4 o u c r t p e t l Decoder 4. n e u o D 2 S O C S ( 1 D 3 Inputs Output Select Lines Output Lines 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 Truth table From truth table: Two inputs are decoded to 4 outputs. Each output represents one of the minterms of the three input variables. For each possible combination (input), there are 3 outputs that are equal to 0 and only one that is equal to 1. S 1 s 1 s 0 s 0 D0 D 1 D2 D3 Decoder Logic Circuit 2.2) Active-low decoders S s s s 1 1 0 0 Inputs Output Select Output Lines Lines D0 0 0 1 1 1 0 D1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 0 1 1 1 D2 Truth table D 3 Active-Low Decoder Logic Circuit AND becomes NAND Complement = = + ; = + ; = + 2.3) Decoders with enable inputs Some decoders include one or more enable inputs to control the circuit operation. A two-to-four line decoder with an enable input constructed with NAND gate is the following: S 1 s 1 s 0 s 0 D Inputs Output 0 Output Lines D1 1 X X 1 1 1 1 D 0 0 0 1 1 1 0 2 0 0 1 1 1 0 1 0 1 0 1 0 1 1 D3 0 1 1 0 1 1 1 E Truth table Active-Low Decoder Logic Circuit with enable input The circuit operates with complemented output and a complemented enable input (Active-Low Enable): then the decoder is enabled. then the decoder is disabled. The enable input may be active with 0 or with a 1 signal. 2.4) Three-to-eight-line decoder circuit inputs outputs 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 X X Y Y Z Z D 0 X Y Z D 1 X Y Z D X Y Z 2 D 3 X YZ D 4 X Y Z D 5 X Y Z D 6 XY Z D 7 XYZ Decoder Logic Diagram 2.5) Larger decoder circuit. Decoders with enable inputs can be connected together to form a larger decoder circuit. To design a line decoder. Using two decoders with enable inputs, we do the following connection: When the top decoder is enable and the other is disable: The bottom decoder outputs are all and the top eight outputs generate minterms to . When the enable condition is reversed, the bottom decoder outputs generate minterms to . X Y 3x8 D D Decoder 0 7 Z E W 3x8 D D Decoder 8 15 E 2.6) Combinational logic implementation: Since, a decoder provides the minterms of input, and any Boolean function can be expressed in sum-of-minterms form, A decoder that generates the minterms of the functions, together with an external OR gate that forms their logical sum, provides a hardware implementation of the function. In this way, any combinational circuit with inputs and outputs can be implemented using line decoder and OR gates. The procedure for implementing a combinational circuit by means of decoders and OR gates requires that the Boolean function for the circuit be expressed as a sum of minterms. Example:-Implementation a full-adder circuit using the decoders. From the truth table of the full adder, we obtain the functions for the sum and carry in sum-of-minterms form: We have 3 inputs: so, we need a three-to-eight line decoder. 0 X 22 1 S 2 3x8 3 21 Y Decoder 4 5 C 20 out Cin 6 7 .
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