Approaches, Strategies, and Implementations of Memory Safety Defenses in Critical and Constrained Embedded Systems Cyril Bresch

Total Page:16

File Type:pdf, Size:1020Kb

Approaches, Strategies, and Implementations of Memory Safety Defenses in Critical and Constrained Embedded Systems Cyril Bresch Approaches, Strategies, and Implementations of Memory Safety Defenses in Critical and Constrained Embedded Systems Cyril Bresch To cite this version: Cyril Bresch. Approaches, Strategies, and Implementations of Memory Safety Defenses in Critical and Constrained Embedded Systems. Micro and nanotechnologies/Microelectronics. Université Grenoble Alpes [2020-..], 2020. English. NNT : 2020GRALT043. tel-03118575 HAL Id: tel-03118575 https://tel.archives-ouvertes.fr/tel-03118575 Submitted on 22 Jan 2021 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. THÈSE Pour obtenir le grade de DOCTEUR DE L’UNIVERSITÉ GRENOBLE ALPES Spécialité : NANO ELECTRONIQUE ET NANO TECHNOLOGIES Arrêtée ministériel : 25 mai 2016 Présentée par Cyril BRESCH Thèse dirigée par Ioannis Parissis, Université Grenoble Alpes et codirigéee par David Hély, Maitre de Conférence, Université Grenoble Alpes et Stéphanie Chollet, Maitre de Conférence, Université Grenoble Alpes préparée au sein du Laboratoire de Conception et d’Intégration des Sys- tèmes (LCIS) dans l’École Doctorale Electronique, Electrotechnique, Automatique, Traitement du Signal (EEATS) Approches, Stratégies, et Implémentations de Protec- tions Mémoire dans les Systèmes Embarqués Critiques et Contraints. Approaches, Strategies, and Implementations of Memory Safety Defenses in Critical and Constrained Embedded Systems. Thèse soutenue publiquement le 16 noctobre 2020, devant le jury composé de: Monsieur AURELIEN FRANCILLON PROFESSEUR, EURECOM - SOPHIA-ANTIPOLIS, Rapporteur Monsieur SEBASTIEN PILLEMENT PROFESSEUR, UNIVERSITE DE NANTES, Rapporteur Madame MARIE-LAURE POTET PROFESSEUR, GRENOBLE-INP, Examinateur Monsieur GIORGIO DI NATALE DIRECTEUR DE RECHERCHE, CNRS DELEGATION ALPES, Président Monsieur ROMAN LYSECKY PROFESSEUR, UNIVERSITE D’ARIZONA, Invité "To my family, and all my friends around the world, for all the love and support." Acknowledgements Acknowledgements The existence of this work would probably require the writing of a second manuscript to thank all the people who supported it. It is thanks to them, over a time span of three amazing years, that I could complete this work. First of all, I would like to thank my thesis’ jury: Mr. Giogio Di Natale, Mrs. Marie- Laure Potet, Mr. Aurélien Francillon, and Mr. Sébastien Pillement for willing to serve on my thesis committee. They carefully attended my defense, listened to my vision regarding my research, evaluated it, recognized it, and finally, awarded me with the degree of doctor. Their insightful comments, suggestions, and challenging questions have helped me make significant improvements to this thesis and beyond. We had memorable discussions and interesting debates during the defense that will contribute to continuing my education as a young researcher. This thesis would not have been possible without the dedication of my thesis directors, David Hély and Ioannis Parissis, as well as my co-supervisor Stéphanie Chollet. I am delighted to have worked with them, they encouraged me to pursue my interests and provided me the freedom and guidance to explore my topic. Besides their scientific support, they have always been there for support and helpful advice. I particularly appreciated Stéphanie’s rigor and her approach regarding my research. She taught me the skills of a professional researcher such as exposing a scientific problem and approaching it from different perspectives. I obviously can’t forget David’s openness, good mood, and support in all my ideas. He approved my desire to go to the United States and collaborate with other researchers. Besides, I will never forget our sparkling meetings, full of ideas and ambitions during these moments. Working with him has been inspiring. I would also like to thank Roman Lysecky, professor at the University of Arizona in Tucson. He hosted me in his research team during my international exchange in the United States. He treated me as one of his Ph.D. students, and I am immensely grateful for his guidance and assistance during my stay in the United States, and after, while collaborating on various research papers. We’ve accomplished a lot and I’m very happy about that. I also want to take this opportunity to thank the SERENE-IoT project, the Laboratoire de Conception et d’Integration des Systèmes (LCIS) Laboratory, the Grenoble EEATS doc- toral school, Grenoble Alpes Cybersecurity Institute, and IDEX for financially supporting this work, the conferences, and all travel. Last but not least, I would like thanks to all my friends, my colleagues, and my lab- mates. I would like to give a special thanks to both Baptiste Pestourie and Luc Perard, my two friends who spent a lot of time with me in Valence. Thank you Soraya Zahouily and Louise Constant for supporting me, even in the most difficult moments. Finally, I would not forget my family for their continuous love and support throughout all these years. i Contents Acknowledgements . .i Table of contents . iii Introduction 1 1 Background 7 1.1 The Memory Safety Issue in Life-Critical Systems . .8 1.1.1 C a prominent programming language in critical systems . .8 1.1.2 The C programming language weaknesses . .9 1.1.3 Critical systems programming rules . 15 1.2 Exploitation Techniques . 17 1.2.1 Control-flow attacks . 17 1.2.2 Data-oriented attacks . 23 1.2.3 Real-world exploits . 24 1.3 Existing Defenses . 26 1.3.1 Control-flow integrity . 27 1.3.2 Heuristic defenses . 40 1.3.3 Software diversity . 43 1.3.4 Data-flow integrity . 46 1.4 State of the Art Synthesis . 55 1.4.1 Control-flow integrity discussion . 55 1.4.2 Heuristic defenses discussion . 56 1.4.3 Software diversity discussion . 57 1.4.4 Data-flow integrity discussion . 58 1.4.5 State-of-the-art discussion . 59 2 Approach 62 2.1 Problem statement . 63 2.1.1 Why critical medical devices are insecure? . 63 2.1.2 Why current defenses are not implemented in medical devices? . 64 2.2 Important memory safety criteria for medical devices . 68 2.3 Approaches . 70 3 SecPump 74 3.1 Motivation . 75 3.2 Open Source Medical Devices . 77 3.3 SecPump . 81 3.3.1 A wireless pump model . 81 3.3.2 SecPump software model . 82 3.3.3 SecPump variants . 88 iii Table of contents 3.4 Security Assessments . 90 3.4.1 Software Threats . 90 3.4.2 Hardware Threats . 91 3.5 Comparison with other works . 93 3.6 Conclusion . 95 4 TrustFlow 98 4.1 Motivation . 99 4.2 Approach . 102 4.2.1 A trusted environment . 104 4.2.2 A secure toolchain . 105 4.3 Implementation . 108 4.3.1 Environment Implementation . 108 4.3.2 Toolchain implementation . 111 4.4 Evaluation . 116 4.4.1 Security evaluation . 116 4.4.2 Environment evaluation . 117 4.5 Discussion . 122 4.6 Comparison with related work . 124 4.7 Conclusion . 126 5 BackGuard 129 5.1 Motivation . 130 5.2 Approach . 133 5.2.1 Protection concept . 134 5.2.2 Security challenges . 136 5.2.3 Implementation challenges . 139 5.3 Implementation . 141 5.3.1 Compiler implementation strategy . 141 5.3.2 Additional passes . 143 5.3.3 Boot sequence . 144 5.4 Evaluation . 146 5.4.1 Security evaluation . 146 5.4.2 Costs . 148 5.5 Discussion . 152 5.6 Comparison with related work . 154 5.7 Conclusion . 156 Conclusion 159 Perspectives 162 Bibliography I List of Figures XV List of Tables XVIII iv Table of contents A Annex 1 : TrustFlow pipeline XX A.1 Trusted memory integration . .XX A.2 Trusted memory controller . XXIII A.3 Data restoration . XXV B Annexe 2 : RISC-V prologue and epilogue insertion XXVII C Annexe 3 : LLVM ARM backend bitmap pass XXX v Introduction Introduction W ith the emerging technologies in several domains such as artificial intelligence, communication, sensors, and processing power, manufacturers are increasingly developing new ubiquitous connected devices identified as the “Internet of Things” –IoT–. According to Forbes [1], the IoT is a fast-growing market that may even double before 2021. As a result, manufacturers see in IoT a genuine business opportunity that encourages them to increasingly release new smart devices over the coming years. The prime purpose of IoT devices is to operate in an environment by collecting, process- ing, and sharing data over the network with other computers without any human-to-human or human-to-computer interaction. From the consumers’ perspective, smart devices are technological innovations that aim at improving their daily life. One of the most common applications example of the “Internet of Things” is the smart home. In a smart home, a user can monitor some equipment such as the lights, the temperature, and the appliances by only using a smartphone. However, the “Internet of Things” is not limited to smart homes. Several sectors [2] such as agriculture, transport, healthcare, and the military are heavily invested in the development of innovative IoT infrastructures to improve their quality of life and quality of service. This thesis unfolds within the European project SERENE-(IoT Secured & EneRgy EfficieNt hEalth-care solutions for IoT market). SERENE-IoT project is labeled within the framework of PENTA, the EUREKA Cluster for Application and Technology Re- search in Europe on NanoElectronics. The project contributes to developing high quality connected care services and diagnostic tools based on advanced smart health-care IoT de- vices. SERENE-IoT leverages the emergence of the "Internet of Medical Things" -IoMT- to prototype new devices, fully manufactured in Europe, that increases the healthcare quality of service for patients remotely followed by caregivers at a much lower cost than the traditional care.
Recommended publications
  • Deciding Memory Safety for Single-Pass Heap-Manipulating Programs
    Deciding Memory Safety for Single-Pass Heap-Manipulating Programs UMANG MATHUR, University of Illinois, Urbana-Champaign, USA ADITHYA MURALI, University of Illinois, Urbana-Champaign, USA PAUL KROGMEIER, University of Illinois, Urbana-Champaign, USA P. MADHUSUDAN, University of Illinois, Urbana-Champaign, USA MAHESH VISWANATHAN, University of Illinois, Urbana-Champaign, USA We investigate the decidability of automatic program verification for programs that manipulate heaps, andin particular, decision procedures for proving memory safety for them. We extend recent work that identified a decidable subclass of uninterpreted programs to a class of alias-aware programs that can update maps. We 35 apply this theory to develop verification algorithms for memory safetyÐ determining if a heap-manipulating program that allocates and frees memory locations and manipulates heap pointers does not dereference an unallocated memory location. We show that this problem is decidable when the initial allocated heap forms a forest data-structure and when programs are streaming-coherent, which intuitively restricts programs to make a single pass over a data-structure. Our experimental evaluation on a set of library routines that manipulate forest data-structures shows that common single-pass algorithms on data-structures often fall in the decidable class, and that our decision procedure is efficient in verifying them. CCS Concepts: • Theory of computation → Logic and verification; Automated reasoning. Additional Key Words and Phrases: Memory Safety, Program Verification, Aliasing, Decidability, Uninterpreted Programs, Streaming-Coherence, Forest Data-Structures ACM Reference Format: Umang Mathur, Adithya Murali, Paul Krogmeier, P. Madhusudan, and Mahesh Viswanathan. 2020. Deciding Memory Safety for Single-Pass Heap-Manipulating Programs. Proc. ACM Program.
    [Show full text]
  • Intra-Unikernel Isolation with Intel Memory Protection Keys
    Intra-Unikernel Isolation with Intel Memory Protection Keys Mincheol Sung Pierre Olivier∗ Virginia Tech, USA The University of Manchester, United Kingdom [email protected] [email protected] Stefan Lankes Binoy Ravindran RWTH Aachen University, Germany Virginia Tech, USA [email protected] [email protected] Abstract ACM Reference Format: Mincheol Sung, Pierre Olivier, Stefan Lankes, and Binoy Ravin- Unikernels are minimal, single-purpose virtual machines. dran. 2020. Intra-Unikernel Isolation with Intel Memory Protec- This new operating system model promises numerous bene- tion Keys. In 16th ACM SIGPLAN/SIGOPS International Conference fits within many application domains in terms of lightweight- on Virtual Execution Environments (VEE ’20), March 17, 2020, Lau- ness, performance, and security. Although the isolation be- sanne, Switzerland. ACM, New York, NY, USA, 14 pages. https: tween unikernels is generally recognized as strong, there //doi.org/10.1145/3381052.3381326 is no isolation within a unikernel itself. This is due to the use of a single, unprotected address space, a basic principle 1 Introduction of unikernels that provide their lightweightness and perfor- Unikernels have gained attention in the academic research mance benefits. In this paper, we propose a new design that community, offering multiple benefits in terms of improved brings memory isolation inside a unikernel instance while performance, increased security, reduced costs, etc. As a keeping a single address space. We leverage Intel’s Memory result,
    [Show full text]
  • “Sok: Eternal War in Memory”
    “SoK: Eternal War in Memory” Presented by Mengjia Yan MIT 6.888 Fall 2020 Overview • Discuss the paper “SoK: Eternal War in Memory” with concrete examples • Recent progress on memory safety • With a focus on hardware/architecture 2 Motivation • C/C++ is unsafe • EveryboDy runs C/C++ coDe • They surely have exploitable vulnerabilities 3 Low-level Language Basics (C/C++/Assembly) 0x00..0000 • Programmers have more control + Efficient OS memory - Bugs - Programming productivity TEXT (code) Global/Static • Pointers DATA • Address of variables (uint64): index of memory location where variable is stored Heap • Programmers need to do pointer check, e.g. NULL, out-of-bound, use-after-free Stack 0xFF..FFFF 4 Low-level Language Basics 0x00..0000 TEXT (code) Heap Stack 0xFF..FFFF 5 Low-level Language Basics TEXT (code) stack 6 Attacks Code Injection Attack Example TEXT (code) int func (char *str) { Shell code: char buffer[12]; strncpy(buffer, str, len(str)); PUSH “/bin/sh” CALL system stack return 1; } int main() { …. func (input); … } 8 Code Injection Attack TEXT (code) TEXT (code) stack stack buffer Shell code … … Return addr Return addr 9 Attacks 10 Return-Oriented Programming (ROP) int func (char *str) { TEXT (code) TEXT (code) char buffer[12]; strncpy(buffer, str, len(str)); stack stack return 1; } …. int main() { buffer …. … … func (input); Return addr Return addr … } 11 Attacks 12 HeartBleed Vulnerability • Publicly DiscloseD in April 2014 • Bug in the OpenSSL cryptographic software library heartbeat extension • Missing a bound check 13 Attacks
    [Show full text]
  • MPTEE: Bringing Flexible and Efficient Memory Protection to Intel
    MPTEE: Bringing Flexible and Efficient Memory Protection to Intel SGX Wenjia Zhao Kangjie Lu* Yong Qi* Saiyu Qi Xi’an Jiaotong University University of Minnesota Xi’an Jiaotong University Xidian University University of Minnesota Abstract code, emerge in today’s market. In particular, Intel has pro- Intel Software Guard eXtensions (SGX), a hardware-based vided SGX in its commodity processors, which supports a se- Trusted Execution Environment (TEE), has become a promis- cure region, namely enclave, to protect the internally loaded ing solution to stopping critical threats such as insider attacks code and data. Given its important and practical protection, and remote exploits. SGX has recently drawn extensive re- SGX has been extensively studied and used in practice. For search in two directions—using it to protect the confidentiality example, SCONE [1] uses it to effectively enhance the secu- and integrity of sensitive data, and protecting itself from at- rity of containers with low overhead. JITGuard [17] leverages tacks. Both the applications and defense mechanisms of SGX it to protect the security-critical just-in-time compiler oper- have a fundamental need—flexible memory protection that ations. SGXCrypter[49] utilizes it to securely unpack and updates memory-page permissions dynamically and enforces execute Windows binaries. There are many other useful appli- the least-privilege principle. Unfortunately, SGX does not pro- cations [35], [34], [31],[6], which confirm the practical and vide such a memory-protection mechanism due to the lack of promising applications of SGX. hardware support and the untrustedness of operating systems. Another line of research is to protect SGX itself from at- This paper proposes MPTEE, a memory-protection mech- tacks.
    [Show full text]
  • Intel® Xeon® E3-1200 V5 Processor Family
    Intel® Xeon® E3-1200 v5 Processor Family Specification Update May 2020 Revision 033 Reference Number: 333133-033US Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at Intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see http://www.intel.com/ content/www/us/en/architecture-and-technology/turbo-boost/turbo-boost-technology.html Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548- 4725 or by visiting www.intel.com/design/literature.htm.
    [Show full text]
  • Sok: Hardware Security Support for Trustworthy Execution
    SoK: Hardware Security Support for Trustworthy Execution Lianying Zhao1, He Shuang2, Shengjie Xu2, Wei Huang2, Rongzhen Cui2, Pushkar Bettadpur2, and David Lie2 1Carleton Universityz, Ottawa, ON, Canada 2University of Toronto, Toronto, ON, Canada Abstract—In recent years, there have emerged many new hard- contribute to lowering power consumption, which is critical ware mechanisms for improving the security of our computer for resource-constrained devices. systems. Hardware offers many advantages over pure software Furthermore, hardware is the Root of Trust (RoT) [48], as approaches: immutability of mechanisms to software attacks, better execution and power efficiency and a smaller interface it bridges the physical world (where human users reside) and allowing it to better maintain secrets. This has given birth to the digital world (where tasks run as software). To securely a plethora of hardware mechanisms providing trusted execution perform a task or store a secret, the user trusts at least part of environments (TEEs), support for integrity checking and memory the computer hardware. safety and widespread uses of hardware roots of trust. Dedicated hardware security support has seen its prolif- In this paper, we systematize these approaches through the lens eration since the early days of computers. It can take a of abstraction. Abstraction is key to computing systems, and the interface between hardware and software contains many abstrac- straightforward form as discrete components to assist the tions. We find that these abstractions, when poorly designed, can CPU, ranging from the industrial-grade tamper-responding both obscure information that is needed for security enforcement, IBM Cryptocards (e.g., 4758 [37]), Apple’s proprietary secure as well as reveal information that needs to be kept secret, leading enclave processor (SEP [84]) for consumer electronics, to the to vulnerabilities.
    [Show full text]
  • Operating System Support for Run-Time Security with a Trusted Execution Environment
    Operating System Support for Run-Time Security with a Trusted Execution Environment - Usage Control and Trusted Storage for Linux-based Systems - by Javier Gonz´alez Ph.D Thesis IT University of Copenhagen Advisor: Philippe Bonnet Submitted: January 31, 2015 Contents Preface2 1 Introduction4 1.1 Context.......................................4 1.2 Problem.......................................6 1.3 Approach......................................7 1.4 Contribution....................................9 1.5 Thesis Structure.................................. 10 I State of the Art 12 2 Trusted Execution Environments 14 2.1 Smart Cards.................................... 15 2.1.1 Secure Element............................... 17 2.2 Trusted Platform Module (TPM)......................... 17 2.3 Intel Security Extensions.............................. 20 2.3.1 Intel TXT.................................. 20 2.3.2 Intel SGX.................................. 21 2.4 ARM TrustZone.................................. 23 2.5 Other Techniques.................................. 26 2.5.1 Hardware Replication........................... 26 2.5.2 Hardware Virtualization.......................... 27 2.5.3 Only Software............................... 27 2.6 Discussion...................................... 27 3 Run-Time Security 30 3.1 Access and Usage Control............................. 30 3.2 Data Protection................................... 33 3.3 Reference Monitors................................. 36 3.3.1 Policy Enforcement............................. 36 3.3.2
    [Show full text]
  • ERIM: Secure, Efficient In-Process Isolation with Protection Keys (MPK)
    ERIM: Secure, Efficient In-process Isolation with Protection Keys (MPK) AnjoVahldiek-Oberwagner EslamElnikety NunoO.Duarte Michael Sammler Peter Druschel Deepak Garg Max Planck Institute for Software Systems (MPI-SWS), Saarland Informatics Campus Abstract prevent control-flow hijacks [30], which could circumvent Isolating sensitive state and data can increase the security the bounds checks. On x86-64, pointer masking-based SFI and robustness of many applications. Examples include pro- techniques like Native Client [42] incur overheads of up to tecting cryptographic keys against exploits like OpenSSL’s 42% on the execution of untrusted code [30]. Even with Heartbleed bug or protecting a language runtime from na- hardware-supported bounds checks, like those supported by tive libraries written in unsafe languages. When runtime the IntelMPX ISA extension[26], the overheadis up to 30%, references across isolation boundaries occur relatively in- as shown in by Koning et al. [30] and later in Section 6.5. frequently, then conventional page-based hardware isola- Another approach is to use hardware page protection for tion can be used, because the cost of kernel- or hypervisor- memory isolation [9, 10, 13, 32, 33, 34]. Here, access checks mediated domain switching is tolerable. However, some are performed in hardware as part of the address translation applications, such as the isolation of cryptographic session with no additional overhead on execution within a compo- keys in network-facing services, require very frequent do- nent. However, transferring control between components main switching. In such applications, the overheadof kernel- requires a switch to kernel or hypervisor mode in order to or hypervisor-mediated domain switching is prohibitive.
    [Show full text]
  • Securing Intel Sgx Against Side-Channel Attacks Via Load-Time Synthesis
    SECURING INTEL SGX AGAINST SIDE-CHANNEL ATTACKS VIA LOAD-TIME SYNTHESIS A Dissertation Presented to The Academic Faculty By Ming-Wei Shih In Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the School of Georgia Institute of Technology Georgia Institute of Technology December 2019 Copyright © Ming-Wei Shih 2019 SECURING INTEL SGX AGAINST SIDE-CHANNEL ATTACKS VIA LOAD-TIME SYNTHESIS Approved by: Dr. Taesoo Kim, Advisor Dr. Michael Steiner School of Computer Science Security and Privacy Research Georgia Institute of Technology Group Intel Labs Dr. Wenke Lee School of Computer Science Dr. Brendan Saltaformaggio Georgia Institute of Technology School of Computer Science Georgia Institute of Technology Dr. Marcus Peinado Cloud and Infrastructure Security Date Approved: Octobor 23, 2019 Group Microsoft Research To my dear wife, Tiffany, and my family. ACKNOWLEDGEMENTS Foremost, I would like to express my sincere gratitude to my advisor Dr. Taesoo Kim for all the support and guidance he provided to me throughout my Ph.D. study. He has taught me how to conduct research in system security since my first year—when I literally know nothing about how to do so. His solid technical background and logical, critical thinking have always inspired me. I would also like to thank Dr. Marcus Peinado for always providing constructive comments when we collaborated on T-SGX and SGX-Armor. I have learned a lot from working with him. Besides, I would like to thank the rest of my thesis committee: Dr. Wenke Lee, Dr. Michael Steiner, and Dr. Brendan Saltaformaggio for their insightful comments that helped me improve this thesis.
    [Show full text]
  • Lessons Learned from Porting Helenos to RISC-V
    Lessons Learned from Porting HelenOS to RISC-V Martin Děcký [email protected] February 2019 Who Am I Passionate programmer and operating systems enthusiast With a specific inclination towards multiserver microkernels HelenOS developer since 2004 Research Scientist from 2006 to 2018 Charles University (Prague), Distributed Systems Research Group Senior Research Engineer since 2017 Huawei Technologies (Munich), German Research Center, Central Software Institute, OS Kernel Lab Martin Děcký, FOSDEM, February 2nd 2019 Lessons Learned from Porting HelenOS to RISC-V 2 HelenOS in a Nutshell open source general-purpose multiplatform microkernel multiserver operating system designed and implemented from scratch Martin Děcký, FOSDEM, February 2nd 2019 Lessons Learned from Porting HelenOS to RISC-V 4 HelenOS in a Nutshell open source general-purpose multiplatform microkernel multiserver operating system designed and implemented from scratch Custom microkernel Custom user space http://www.helenos.org Martin Děcký, FOSDEM, February 2nd 2019 Lessons Learned from Porting HelenOS to RISC-V 5 HelenOS in a Nutshell open source general-purpose multiplatform microkernel multiserver operating system designed and implemented from scratch 3-clause BSD permissive license https://github.com/HelenOS Martin Děcký, FOSDEM, February 2nd 2019 Lessons Learned from Porting HelenOS to RISC-V 6 HelenOS in a Nutshell open source general-purpose multiplatform microkernel multiserver operating system designed and implemented from scratch Breath-first rather than depth-first
    [Show full text]
  • Memory Corruption Mitigation Via Hardening and Testing
    Memory corruption mitigation via hardening and testing A Dissertation presented by László Szekeres to The Graduate School in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in Computer Science Stony Brook University May 2017 Copyright by László Szekeres 2017 Stony Brook University The Graduate School László Szekeres We, the dissertation committe for the above candidate for the Doctor of Philosophy degree, hereby recommend acceptance of this dissertation Dr. R. Sekar – Dissertation Advisor Professor, Department of Computer Science Dr. Scott Stoller – Chairperson of Defense Professor, Department of Computer Science Dr. Long Lu – Committee Member Assistant Professor, Department of Computer Science Dr. Franjo Ivančić – External Committee Member Staff Software Engineer, Google Adjunct Assistant Professor, Columbia University This dissertation is accepted by the Graduate School Charles Taber Dean of the Graduate School ii Abstract of the Dissertation Memory corruption mitigation via hardening and testing by László Szekeres Doctor of Philosophy in Computer Science Stony Brook University 2017 Despite decades of research, memory corruption vulnerabilities continue to be at the fore- front of today’s security threats. There are two main avenues for automating defenses against these vulnerabilities: (a) develop automated analysis/testing techniques to find these bugs, or (b) develop software transformations that block their exploitation, or at least make them more difficult (hardening). This dissertation explores both of these avenues. The thesis begins with a general model of memory corruption attacks and a systematic analysis of previous hardening techniques. We show that there none of the existing solutions protect against control-flow hijacks in a both effective and efficient manner.
    [Show full text]
  • Efficient Fault Tolerance Using Intel MPX And
    Efficient Fault Tolerance using Intel MPX and TSX Oleksii Oleksenko*, Dmitrii Kuvaiskii*, Pramod Bhatotia*, Christof Fetzer*, Pascal Felber** * Technische Universitat¨ Dresden, Germany ** University of Neuchatel,ˆ Switzerland Abstract—Hardware faults can cause data corruptions during Memory Memory computation, and they are especially harmful if these corruptions happen in data pointers. Existing solutions, however, incur high performance overheads, which is unacceptable for compute- out-of-bound access intensive applications. In this work, we present an efficient fault- tolerance approach against hardware faults by exploiting the new object bounds object bounds extensions to the x86 architecture. In particular, we propose that Intel MPX can be effectively used to detect faults in data pointers, while Intel TSX can provide roll-back recovery against these corruptions. Our preliminary evaluation supports this hypothesis, and we estimate the average overhead to be roughly around 50%. pointer corrupted pointer I. INTRODUCTION Critical components of the software stack such as operating (a) (b) systems, file systems, and databases are written in a low- level language (primarily, in C/C++) for improved performance Fig. 1: The concept of fault detection using MPX: (a) correct state, (b) a fault in pointer causes object bounds violation. and flexibility in memory management. However, the normal program flow can be arbitrarily corrupted by bit-flips in CPU protection and hardware transactional memory. In particu- or RAM during run-time. The resulting corruptions can lead lar, our approach is based on the new generations of Intel to catastrophic consequences; especially, if the corruption architecture—starting Skylake—with respective support for happens in data pointers—as they can cause the loss of the memory protection via MPX [4] and transactional memory whole data structure [1].
    [Show full text]