VITA 56 – a Fabric-Based PMC Replacement Mezzanine Specification
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Product guide Mezzanines VITA 56 – A fabric-based PMC replacement mezzanine specification By David Slaton In 2005, a VSO VITA 56 working group was established to specify a new mezzanine card that could replace the aging PCI Mezzanine Card (PMC) in 6U embedded systems. This mezzanine card, also known as Express Mezzanine Card (EMC), will offer embedded systems an expansion option that supports the latest and future multi-Gigabit serial fabrics and provides greater levels of manageability and serviceability. These include the ability to remove the module from its host through the front panel. In the first half of 2007, the base EMC specification (EMC.0) will be released under VSOy guidelines for trial use. nl Parallel bus on the decline offered many of the features sought for aO “fat pipes” region, and a “common I/O Prior to the advent of serial fabrics such a 6U mezzanine, the VITA 56 workingt options” region. as PCI Express and Serial RapidIO in group started with AdvancedMC. The embedded systems, the parallel PCI bus working group then made substantialin but Because the EMC is seen as a replace- was predominately used to interface necessary changes to creater a module ment for PMC, where a parallel PCI bus single board computer chipsets to vari- more suitable to traditionalP and future was the main I/O channel, the working ous I/O controllers. Although the PCI embedded systems. Table 1 contains group identified PCIe as the first fabric to bus scaled over time to accommodate various subspecificationsle that make up be supported. As part of the base speci- greater I/O bandwidth demands, the limi- the VITA 56 specification. fication, a set of ports on the connector tations of parallel bus technology began g to become a bottleneck. During that time, nVITA Name Industry Name Description the PMC was adapted to support higher- i speed parallel I/O through the VITAS 39 VITA 56.0 EMC.0 Base Specification, Convective-cooled Version effort, which added PCI-X capabilities to r VITA 56.10 EMC.10 Base Specification, Conduction-cooled Version the module. o VITA 56.1 EMC.1 PCIe Signal Protocol on VITA 56 To further extendF the PMC’s life, XMC VITA 56.2 EMC.2 GbE on VITA 56 (VITA 42) was created to provide serial VITA 56.3 EMC.3 Storage on VITA 56 fabric capabilities. This was accom- plished by adding two additional con- VITA 56.4 EMC.4 Serial RapidIO on VITA 56 nectors to the module, one for the serial VITA 56.20 EMC.20 Common Option I/O Routing fabric and another for optional fabric or VITA 56.99 EMC.99 Vendor Part Number List I/O. However, because of the overriding goal of backwards compatibility, XMC Table 1 does not address issues such as front panel module insertion/extraction – which Where we are with VITA 56 is allocated for a PCIe channel (up to improves system serviceability – and poor The VITA 56 working group’s first priority a x4) that is present on all modules. A placement of mounting holes, keying has been to detail the fabric requirements subspecification for PCIe, EMC.1, has pins, and board-to-board connectors on for PCI Express (PCIe), the mechanical been created to detail PCIe use on the the PMC, which hinders high-speed I/O requirements for the module and carrier, ports in the “fat pipes” region. support. Furthermore, there exists today the module/carrier management mecha- a question about the ability of the chosen nism, and general I/O configurations. Mechanically, the EMC maintains the connectors to scale in speed to support The subspecifications that relate to these 10 mm board-to-board spacing first used emerging fabrics, potentially limiting areas are EMC.0, EMC.1, and EMC.20. by the PMC and generally has the same top-end mezzanine performance. The base specification EMC.0 details dimensions and volume (see Figure 1) the mechanical requirements and other but uses a card-edge connector system The VITA 56 working group set out to general requirements for a module and that allows the module to be removed start anew with a module specification carrier. The base specification also defines that would retain the PMC’s physical the port mapping strategy for EMCs, as volume, allowing two modules per shown in Table 2. 6U carrier but providing support for the latest serial fabrics. Realizing that an The base specification defines “ports” existing module specification (Advanced or differential transmit/receive pairs for Mezzanine Card or AdvancedMC) several uses: clocks, a base PCIe channel, Figure 1 VME and Critical Systems ©2007 OpenSystems Publishing. Not for Distribution. Mezzanines Product guide through the front panel. Just like on a Part No. EMC Port Mapping Strategy PMC, the main component side of the module (facing the carrier) has a maxi- CLK1 mum component height of 4.7 mm as CLK2 Clocks does the maximum component height of CLK3 the carrier underneath the module, except near the front panel, where the module is 0 X1 allowed to occupy the full volume. 1 X2 Base PCIe 2 To facilitate module removal, a thumb- screw is included on the module’s front 3 X4 panel and engages a switch on the carrier 4 to indicate the insertion/removal status 5 (Figure 2) so important in the manage- ment of hot-swappable resources. The 6 thumbscrew also serves as a positive 7 retention mechanism by locking into a retention block on the carrier. 8 ly 9 nFat Pipes Ports 1-12 10 O 11 t 12 n 13 ri 14 P 15 16 le 17g Common Options Figure 2 in18 19 The working group has also dealt withS the issue of module management,r balancing 20 Undefined the need for low-cost module develop- Table 2 ment while providing foro the increasing need of systemsF to monitor and con- trol a variety of module parameters. The VITA 56 specification defines Unmanaged PSx# Decoding Modules (UMs) where on-module man- agement resources are not required and PS0D# PS0C# PS0B# PS0A# Meaning Managed Modules (MMs) where the mod- 0 0 0 0 Bus Negotiated via IPMI ule contains a management controller 0 0 0 1 EMC.1a – PCI Express “a” that interacts with a controller on the carrier or elsewhere in the system. 0 0 1 0 EMC.1b – PCI Express “b” 0 0 1 1 EMC.1c – PCI Express “c” To ensure the compatibility of a UM with 0 1 0 0 EMC.2a – GbE “a” the carrier, the specification defines a table of acceptable “fat pipe” configurations. 0 1 0 1 EMC.2b – GbE “b” These configurations are designated by 0 1 1 0 EMC.2c – GbE “c” the carrier through the use of four signals, PS0D#-PS0A# (Table 3). For example, Table 3 a UM may support two independent x8 PCIe links (referred to as “EMC.1b” in the table), as shown in Figure 3. EMC Host EMC Host EMC Host If the module and carrier agree that the x4 x8 x16 designated configuration is supported, a (Base 0-3) PCIe (Base 0-3) PCIe (Base 0-3) PCIe handshaking signal is activated and the (Fat Pipes 1-4) x12 x8 carrier may enable the module. (Fat Pipes 1-12) PCIe (Fat Pipes 5-12) PCIe (Fat Pipes 1-12) MMs negotiate fabric compatibility through an I2C bus using Intelligent EMC.1a EMC.1b EMC.1c Platform Management Interface (IPMI) Figure 3 VME and Critical Systems ©2007 OpenSystems Publishing. Not for Distribution. Product guide Mezzanines request/responses and e-keying methods similar to those used in AdvancedMC switch PCIe management. The VITA 56 specifica- EMC1 tion defines a subset of IPMI commands GbE required to properly enable the mod- ule while minimizing the management switch resources needed on a module. GbE EMC2 PCIe EMC1 EMC2 chipset “As the use of the PMC switch PCIe PCIe fades because of lack of CPU chipset CPU support for parallel PCI buses in chipsets and Figure 4 y peripheral components, l and MicroTCA systems (left side of fabrics andn scalable to accommodate modules like EMC will Figure 4). In such systems, the carrier is higher speed signaling. It also provides an extension of the larger “system” as a managementO for greater system reliability begin to proliferate.” node on a hierarchy (right side of Figuret and hot swapping for increased service- 4), with the modules as simply another ability. As a result, the EMC is poised to extension. Such fabric-based isystemsn be the ubiquitous mezzanine solution for In addition to fabric negotiation, the provide multiple parallel datar paths for future embedded systems. CS VITA 56 specification defines several I/O local data traffic and Pgreater throughput configurations that are supported to allow over traditionalparallel systems. compatible egress of “common” signals David Slaton le is a senior NPI such as Ethernet, Serial ATA, USB, and New mezzanine standard so forth, via the EMC.20 subspecifica- Regardlessg of the topology used in a given design engineer tion. On MMs, these configurations are nfabric-based system, any new module or for GE Fanuc instead negotiated through carrier/module icarrier must be scalable to provide a ser- Embedded Systems I2C transactions, similar to how theS “fat vice life comparable to systems making and has worked pipes” ports are configured. The EMC.20 use of parallel buses such as VME or on embedded sys- r tems design for subspecification also details pertinent CompactPCI. Today, fabric standards routing between moduleso and backplane support data rates of a few Gbps, but 14 years. During the past nine years, connectors on variousF carriers including emerging standards support 10 Gbps or he has worked on VME, CompactPCI, VITA 31.1, 41, 46, and PICMG 2.16.