Digital Electronics ECE 2203
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Logisim Operon Circuits
International Journal of Scientific & Engineering Research, Volume 4, Issue 8, August-2013 1312 ISSN 2229-5518 Logisim Operon Circuits Aman Chandra Kaushik Aman Chandra Kaushik (M.Sc. Bioinformatics) Department of Bioinformatics, University Institute of Engineering & Technology Chhatrapati Shahu Ji Maharaj University, Kanpur-208024, Uttar Pradesh, India Email: [email protected] Phone: +91-8924003818 Abstract: Creation of Logism Operon circuits for bacterial cells that not only perform logic functions, but also remember the results, which are encoded in the cell’s DNA and passed on for dozens of generations. This circuits is coded in JAVA Language. “Almost all of the previous work in synthetic biology that we’re aware of has either focused on logic components and logical circuits or on memory modules that just encode memory. We think complex computation will involve combining both logic and memory, and that’s why we built this particular framework for designing circuits Life Science. In one circuit described in the paper, one DNA sequences have three genes called Repressor, Operator (terminators) are interposed between the promoter (DNA Polymerase) and the output Proteins (Beta glactosidase, permease, Transacetylase in this case). Each of these terminators inhibits the transcription and Translation of the output gene and can be flipped by a different Promoter enzyme (DNA Polymerase), making the terminator inactive. Key words: Logical IJSERGate, JAVA, Circuits, Operon, AND, OR, NOT, NOR, NAND, XOR, XNOR, Operon Logisim Circuits. IJSER © 2013 http://www.ijser.org International Journal of Scientific & Engineering Research, Volume 4, Issue 8, August-2013 1313 ISSN 2229-5518 1. Introduction The AND gate is obtained from the E6 core module by extending both ends with hairpin M olecular Logic Gates Coding in Java modules, one complementary to input Language and circuits are designed in oligonucleotide x and the other Logisim complementary to input oligonucleotide y. -
The Equation for the 3-Input XOR Gate Is Derived As Follows
The equation for the 3-input XOR gate is derived as follows The last four product terms in the above derivation are the four 1-minterms in the 3-input XOR truth table. For 3 or more inputs, the XOR gate has a value of 1when there is an odd number of 1’s in the inputs, otherwise, it is a 0. Notice also that the truth tables for the 3-input XOR and XNOR gates are identical. It turns out that for an even number of inputs, XOR is the inverse of XNOR, but for an odd number of inputs, XOR is equal to XNOR. All these gates can be interconnected together to form large complex circuits which we call networks. These networks can be described graphically using circuit diagrams, with Boolean expressions or with truth tables. 3.2 Describing Logic Circuits Algebraically Any logic circuit, no matter how complex, may be completely described using the Boolean operations previously defined, because of the OR gate, AND gate, and NOT circuit are the basic building blocks of digital systems. For example consider the circuit shown in Figure 1.3(c). The circuit has three inputs, A, B, and C, and a single output, x. Utilizing the Boolean expression for each gate, we can easily determine the expression for the output. The expression for the AND gate output is written A B. This AND output is connected as an input to the OR gate along with C, another input. The OR gate operates on its inputs such that its output is the OR sum of the inputs. -
LOGIC GATESLOGIC GATES Logic Gateslogic Gates
SCR 1013 : Digital Logic Module 3:Module 3:ModuleModule 3: 3: LOGIC GATESLOGIC GATES Logic GatesLogic Gates NOT Gate (Inverter) AND Gate OR Gate NAND Gate NOR Gate Exclusive-OR (XOR) Gate Exclusive-NOR (XNOR) Gate OutlineOutline • NOT Gate (Inverter) Basic building block • AND Gate • OR Gate Universal gate using • NAND Gate 2 of the basic gates • NOR Gate Universal gate using 2 of the basic gates • Exclusive‐OR (XOR) Gate • Exclusive‐NOR (XNOR) Gate NOT Gate (Inverter)NOT Gate (Inverter) • Characteriscs Performs inversion or complementaon • Changes a logic level to the opposite • 0(LOW) 1(HIGH) ; 1 0 • Symbol • Truth Table Input Output 1 0 0 1 NOT Gate (Inverter)NOT Gate (Inverter) • Operator – NOT Gate is represented by overbar • Logic expression AND GateAND Gate • Characteriscs – Performs ‘logical mul@plica@on’ • If all of the input are HIGH, then the output is HIGH. • If any of the input are LOW, then the output is LOW. – AND gate must at least have two (2) INPUTs, and must always have 1 (one) OUTPUT. The AND gate can have more than two INPUTs • Symbols OR GateOR Gate • Characteriscs – Performs ‘logical addion’. • If any of the input are HIGH, then the output is HIGH. • If all of the input are LOW, then the output is LOW. • Symbols NAND GateNAND Gate • NAND NOT‐AND combines the AND gate and an inverter • Used as a universal gate – Combina@ons of NAND gates can be used to perform AND, OR and inverter opera@ons – If all or any of the input are LOW, then the output is HIGH. -
Hardware Abstract the Logic Gates References Results Transistors Through the Years Acknowledgements
The Practical Applications of Logic Gates in Computer Science Courses Presenters: Arash Mahmoudian, Ashley Moser Sponsored by Prof. Heda Samimi ABSTRACT THE LOGIC GATES Logic gates are binary operators used to simulate electronic gates for design of circuits virtually before building them with-real components. These gates are used as an instrumental foundation for digital computers; They help the user control a computer or similar device by controlling the decision making for the hardware. A gate takes in OR GATE AND GATE NOT GATE an input, then it produces an algorithm as to how The OR gate is a logic gate with at least two An AND gate is a consists of at least two A NOT gate, also known as an inverter, has to handle the output. This process prevents the inputs and only one output that performs what inputs and one output that performs what is just a single input with rather simple behavior. user from having to include a microprocessor for is known as logical disjunction, meaning that known as logical conjunction, meaning that A NOT gate performs what is known as logical negation, which means that if its input is true, decision this making. Six of the logic gates used the output of this gate is true when any of its the output of this gate is false if one or more of inputs are true. If all the inputs are false, the an AND gate's inputs are false. Otherwise, if then the output will be false. Likewise, are: the OR gate, AND gate, NOT gate, XOR gate, output of the gate will also be false. -
Designing Combinational Logic Gates in Cmos
CHAPTER 6 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS In-depth discussion of logic families in CMOS—static and dynamic, pass-transistor, nonra- tioed and ratioed logic n Optimizing a logic gate for area, speed, energy, or robustness n Low-power and high-performance circuit-design techniques 6.1 Introduction 6.3.2 Speed and Power Dissipation of Dynamic Logic 6.2 Static CMOS Design 6.3.3 Issues in Dynamic Design 6.2.1 Complementary CMOS 6.3.4 Cascading Dynamic Gates 6.5 Leakage in Low Voltage Systems 6.2.2 Ratioed Logic 6.4 Perspective: How to Choose a Logic Style 6.2.3 Pass-Transistor Logic 6.6 Summary 6.3 Dynamic CMOS Design 6.7 To Probe Further 6.3.1 Dynamic Logic: Basic Principles 6.8 Exercises and Design Problems 197 198 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS Chapter 6 6.1Introduction The design considerations for a simple inverter circuit were presented in the previous chapter. In this chapter, the design of the inverter will be extended to address the synthesis of arbitrary digital gates such as NOR, NAND and XOR. The focus will be on combina- tional logic (or non-regenerative) circuits that have the property that at any point in time, the output of the circuit is related to its current input signals by some Boolean expression (assuming that the transients through the logic gates have settled). No intentional connec- tion between outputs and inputs is present. In another class of circuits, known as sequential or regenerative circuits —to be dis- cussed in a later chapter—, the output is not only a function of the current input data, but also of previous values of the input signals (Figure 6.1). -
8-Bit Adder and Subtractor with Domain Label Based on DNA Strand Displacement
Article 8-Bit Adder and Subtractor with Domain Label Based on DNA Strand Displacement Weixuan Han 1,2 and Changjun Zhou 1,3,* 1 College of Mathematics and Computer Science, Zhejiang Normal University, Jinhua 321004, China; [email protected] 2 College of Nuclear Science and Engineering, Sanmen Institute of technicians, Sanmen 317100, China 3 Key Laboratory of Advanced Design and Intelligent Computing (Dalian University) Ministry of Education, Dalian 116622, China * Correspondence: [email protected] Academic Editor: Xiangxiang Zeng Received: 16 October 2018; Accepted: 13 November 2018; Published: 15 November 2018 Abstract: DNA strand displacement, which plays a fundamental role in DNA computing, has been widely applied to many biological computing problems, including biological logic circuits. However, there are many biological cascade logic circuits with domain labels based on DNA strand displacement that have not yet been designed. Thus, in this paper, cascade 8-bit adder/subtractor with a domain label is designed based on DNA strand displacement; domain t and domain f represent signal 1 and signal 0, respectively, instead of domain t and domain f are applied to representing signal 1 and signal 0 respectively instead of high concentration and low concentration high concentration and low concentration. Basic logic gates, an amplification gate, a fan-out gate and a reporter gate are correspondingly reconstructed as domain label gates. The simulation results of Visual DSD show the feasibility and accuracy of the logic calculation model of the adder/subtractor designed in this paper. It is a useful exploration that may expand the application of the molecular logic circuit. Keywords: DNA strand displacement; cascade; 8-bit adder/subtractor; domain label 1. -
–Not –And –Or –Xor –Nand –Nor
Gates Six types of gates –NOT –AND –OR –XOR –NAND –NOR 1 NOT Gate A NOT gate accepts one input signal (0 or 1) and returns the complementary (opposite) signal as output 2 AND Gate An AND gate accepts two input signals If both are 1, the output is 1; otherwise, the output is 0 3 OR Gate An OR gate accepts two input signals If both are 0, the output is 0; otherwise, the output is 1 4 XOR Gate An XOR gate accepts two input signals If both are the same, the output is 0; otherwise, the output is 1 5 XOR Gate Note the difference between the XOR gate and the OR gate; they differ only in one input situation When both input signals are 1, the OR gate produces a 1 and the XOR produces a 0 XOR is called the exclusive OR because its output is 1 if (and only if): • either one input or the other is 1, • excluding the case that they both are 6 NAND Gate The NAND (“NOT of AND”) gate accepts two input signals If both are 1, the output is 0; otherwise, the output is 1 NOR Gate The NOR (“NOT of OR”) gate accepts two inputs If both are 0, the output is 1; otherwise, the output is 0 8 AND OR XOR NAND NOR 9 Review of Gate Processing Gate Behavior NOT Inverts its single input AND Produces 1 if all input values are 1 OR Produces 0 if all input values are 0 XOR Produces 0 if both input values are the same NAND Produces 0 if all input values are 1 NOR Produces 1 if all input values are 0 10 Combinational Circuits Gates are combined into circuits by using the output of one gate as the input for another This same circuit using a Boolean expression is AB + AC 11 Combinational Circuits Three inputs require eight rows to describe all possible input combinations 12 Combinational Circuits Consider the following Boolean expression A(B + C) Does this truth table look familiar? Compare it with previous table 13. -
Performance Analysis of Adiabatic Logic Gate Circuits Using 4T Dram Cells
PERFORMANCE ANALYSIS OF ADIABATIC LOGIC GATE CIRCUITS USING 4T DRAM CELLS by ANUPRIYA KRISHNAMOORTHY A THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Engineering in The Department of Electrical and Computer Engineering to The School of Graduate Studies of The University of Alabama in Huntsville HUNTSVILLE, ALABAMA 2016 iii iv ACKNOWLEDGEMENTS This thesis could not be completed without the assistance of several people who deserve special mention. First, I would like to thank Dr. Fat Duen Ho for his guidance throughout all the stages of the work. Second the members of my committee, Dr. David Wendi Pan and Dr. Jia Li, who have been helpful with comments and suggestions. I would like to thank my family especially my parents Krishnamoorthy Vanchinathan(Father), Umamaheswari Jagadeesan (Mother) and my elder sibling Abinaya Krishnamoorthy (Sister) and my friend Ashish Ramesh, for tolerating me through the whole process. v TABLE OF CONTENTS Page List of Figures ............................................................................................................................................ viii List of Symbols ............................................................................................................................................ xi 1. INTRODUCTION AND BACKGROUND 1.1 Overview ................................................................................................................................... 1 1.2 Tank Oscillator Operation ........................................................................................................ -
A New Design of XOR-XNOR Gates for Low Power Application
View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by UTHM Institutional Repository 2011 International Conference on Electronic Devices, Systems & Applications (ICEDSA) A New Design of XOR-XNOR gates for low power application Nabihah Ahmad Rezaul Hasan Faculty of Electrical and Electronic, School of Engineering and Advanced Technology Universiti Tun Husseion Onn Malaysia Massey University Batu Pahat, Johor, Malaysia Auckland, New Zealand [email protected] [email protected] Abstract—XOR and XNOR gate plays an important role in network can be found in [4]. Each input is connected to both an digital systems including arithmetic and encryption circuits. This NMOS transistor and a PMOS transistor. It provide a full paper proposes a combination of XOR-XNOR gate using 6- output voltage swing but with a large number of transistors. transistors for low power applications. Comparison between a best existing XOR-XNOR have been done by simulating the Complementary pass transistor logic (CPL) is used in [1]. proposed and other design using 65nm CMOS technology in Wang et al. [2] report the XOR-XNOR circuits based on Cadence environment. The simulation results demonstrate the transmission gates. It uses eight transistors and complementary delay, power consumption and power-delay product (PDP) at inputs and has a drawback of loss of driving capability. Wang different supply voltages ranging from 0.6V to 1.2V. The results et al. also designed XOR-XNOR circuits based on inverter show that the proposed design has lower power dissipation and gates. It does not require a complementary inputs but it has no has a full voltage swing. -
Exclusive Or from Wikipedia, the Free Encyclopedia
New features Log in / create account Article Discussion Read Edit View history Exclusive or From Wikipedia, the free encyclopedia "XOR" redirects here. For other uses, see XOR (disambiguation), XOR gate. Navigation "Either or" redirects here. For Kierkegaard's philosophical work, see Either/Or. Main page The logical operation exclusive disjunction, also called exclusive or (symbolized XOR, EOR, Contents EXOR, ⊻ or ⊕, pronounced either / ks / or /z /), is a type of logical disjunction on two Featured content operands that results in a value of true if exactly one of the operands has a value of true.[1] A Current events simple way to state this is "one or the other but not both." Random article Donate Put differently, exclusive disjunction is a logical operation on two logical values, typically the values of two propositions, that produces a value of true only in cases where the truth value of the operands differ. Interaction Contents About Wikipedia Venn diagram of Community portal 1 Truth table Recent changes 2 Equivalencies, elimination, and introduction but not is Contact Wikipedia 3 Relation to modern algebra Help 4 Exclusive “or” in natural language 5 Alternative symbols Toolbox 6 Properties 6.1 Associativity and commutativity What links here 6.2 Other properties Related changes 7 Computer science Upload file 7.1 Bitwise operation Special pages 8 See also Permanent link 9 Notes Cite this page 10 External links 4, 2010 November Print/export Truth table on [edit] archived The truth table of (also written as or ) is as follows: Venn diagram of Create a book 08-17094 Download as PDF No. -
Combinational Logic Circuits
CHAPTER 4 COMBINATIONAL LOGIC CIRCUITS ■ OUTLINE 4-1 Sum-of-Products Form 4-10 Troubleshooting Digital 4-2 Simplifying Logic Circuits Systems 4-3 Algebraic Simplification 4-11 Internal Digital IC Faults 4-4 Designing Combinational 4-12 External Faults Logic Circuits 4-13 Troubleshooting Prototyped 4-5 Karnaugh Map Method Circuits 4-6 Exclusive-OR and 4-14 Programmable Logic Devices Exclusive-NOR Circuits 4-15 Representing Data in HDL 4-7 Parity Generator and Checker 4-16 Truth Tables Using HDL 4-8 Enable/Disable Circuits 4-17 Decision Control Structures 4-9 Basic Characteristics of in HDL Digital ICs M04_WIDM0130_12_SE_C04.indd 136 1/8/16 8:38 PM ■ CHAPTER OUTCOMES Upon completion of this chapter, you will be able to: ■■ Convert a logic expression into a sum-of-products expression. ■■ Perform the necessary steps to reduce a sum-of-products expression to its simplest form. ■■ Use Boolean algebra and the Karnaugh map as tools to simplify and design logic circuits. ■■ Explain the operation of both exclusive-OR and exclusive-NOR circuits. ■■ Design simple logic circuits without the help of a truth table. ■■ Describe how to implement enable circuits. ■■ Cite the basic characteristics of TTL and CMOS digital ICs. ■■ Use the basic troubleshooting rules of digital systems. ■■ Deduce from observed results the faults of malfunctioning combina- tional logic circuits. ■■ Describe the fundamental idea of programmable logic devices (PLDs). ■■ Describe the steps involved in programming a PLD to perform a simple combinational logic function. ■■ Describe hierarchical design methods. ■■ Identify proper data types for single-bit, bit array, and numeric value variables. -
Tutorial on Adder and Subtractor Logic Circuits Digital Adder: 1. Half Adder 2. Full Adder. Half Adder- Full Adder
Tutorial on Adder and Subtractor Logic Circuits Digital Adder: In digital electronics an adder is a logic circuit that implements addition of numbers. In many computers and other types of processors, adders are used to calculate addresses, similar operations and table indices in the arithmetic logic unit (ALU) and also in other parts of the processors. These can be built for many numerical representations like binary coded decimal or excess-3. Adders are classified into two types: 1. Half adder 2. Full adder. Half Adder- The half adder circuit is required to add two input digits (for Ex. A and B) and generate a carry and sum. The half adder adds two binary digits called as augend and addend and produces two outputs as sum and carry (XOR is applied to both inputs to produce sum and AND gate is applied to both inputs to produce carry). It means half adder circuits can add only two digits in other words if we need to add more than 2 digits it will not work, so, it the limitation of an half adder electronic circuits. To resolve this problem a full adder circuit is required. Application- The ALU of a computer uses half adder to compute the binary addition operation on two bits. Half adder is used to make full adder as a full adder requires 3 inputs, the third input being an input carry i.e. we will be able to cascade the carry bit from one adder to the other. Ripple carry adder is possible to create a logical circuit using multiple full adders to add N- bit numbers.