Integration and Analysis of a 24.3Mhz FM Transmitter/Receiver System

Home , Intermediate frequency, Local oscillator

Integration and Analysis of a 24.3MHz FM Transmitter/Receiver System

Alex Tung Lab Partner: Michael Wiemer EE133: Prof. Bob Dutton Final Project Write-up TABLE OF CONTENTS

ABSTRACT 3

INTRODUCTION 3

CIRCUIT DESIGN THEORY 3

DISCUSSION/RESULTS 5

CONCLUSION 9

APPENDIX A-1: POWER AMPLIFIER 11

APPENDIX A-2: LOW-NOISE AMPLIFIER 13

APPENDIX A-3: 4.5V REFERENCE 15

APPENDIX A-4: AUDIO INPUT 16

APPENDIX B: FORMAL LAB WRITE-UP REFERENCES 17

2 ABSTRACT tery power supplies. The transmitter consumes 360mW of DC power and transmits a 2.75dBm We designed and built an FM transmitter / re- signal. ceiver system to operate at 24.3MHz and 9V bat- at an output power of 2.7dBm. The receiver has a 1. Audio Input and Amplification clear minimum detectable signal of –90dBm and a The audio input and amplification circuitry con- maximum receivable distance of 5/8 miles when sists of a microphone and non-inverting amplifier, used in conjunction with a 20dBm transmitter. which produces a nominal 100 V/V voltage gain at its output. The input level of the microphone can be adjusted using a potentiometer so as to mini- INTRODUCTION mize distortion of loud signals. The output DC level of the circuit is also adjustable, so that the Optimal performance of an FM transmitter / re- VCO maybe set to the correct free-running fre- ceiver system depends on a number of factors, in- quency (see Appendix A-4). cluding solid design and a precise implementation of each component block of the system. Designing 2. Voltage-Controlled Oscillator and tuning the transmitter and receiver to function The voltage-controlled oscillator performs the fre- well with one another also presents a key chal- quency modulation of an intermediate frequency lenge. In addition, implementation of filters and with the input audio signal by converting the volt- low-noise amplifiers helps to reduce the degrada- age input to a frequency output. The output DC tion of system performance due to outside noise level from the audio amplifier sets the free- sources while also improving maximum receiv- running frequency of the VCO, and an applied in- able distance. This paper will discuss the design put signal produces a frequency-varied output that and implementation of a 24.3 MHz transmit / re- corresponds to the input voltage fluctuations. We ceive system in terms of expected performance, used the LM566 VCO to implement this oscillator measured performance, and improvements made. in our transmitter. With a DC input level of 7.5V, the free-running frequency of the oscillator can be adjusted to the needed 300kHz with a variable ca- CIRCUIT DESIGN THEORY pacitor in its timing regulation circuitry. For further discussion of the VCO, see Appendix B-2. We designed the transmitter and receiver to operate at a frequency of 24.3 MHz with an intermedi- Figure 1: Transmitter Circuit Blocks ate frequency (IF) of 300 kHz. Each of the two system components consists of a number of circuit blocks, which perform various functions within the system. We discuss each of these blocks sub- sequently.

I. The Transmitter The transmitter uses an input audio signal to modulate an intermediate frequency, mixes the 3. Mixer signal to a higher transmit frequency, and outputs The SA602 Analog Multiplier serves as the mixer the modulated signal from an antenna. The fol- for this system. The mixer takes as input the lowing blocks combine to achieve these functions: 300kHz IF signal and upconverts it by multiplying an audio input and amplifier, a voltage-controlled it with a 24MHz carrier signal from a local oscil- oscillator, a mixer, a local oscillator, and a power lator. This multiplication produces an output sig- amplifier (See Figure 1). nal at the carrier frequency of 24MHz and two sideband signals at 24.3MHz and 23.7MHz. In

3 theory, one would like to suppress the excess In order to reduce the amount of distortion caused 24MHz carrier and 23.7MHz negative sideband by harmonic signals, we designed the LNA with a signals, as they do not transmit the desired infor- series LC input filter centered at 24.3MHz with a mation. Performing this single-sideband transmis- 10MHz bandwidth. sion requires more complicated techniques than are within the scope of this project. 2. Low-Noise Amplifier In order to maximize receivable distance, the re- 4. Local Oscillator ceiver end of the system includes an input amplifi- The SA602 contains the added functionality of an cation stage in the form of a single-transistor low- on-chip local oscillator, the frequency of which noise amplifier. This stage amplifies the power of can be set using a crystal and capacitive divider. the incoming signal while minimizing distortion at We used this oscillator output as the carrier signal its output. The LNA consists of a bipolar transistor for our mixer, setting the oscillation frequency with resistive feedback and an inductive load. The with a 24MHz crystal. The ease of this imple- output of the amplifier consists of an LC match mentation makes construction of a separate, dis- which transforms the actual load impedance crete oscillator (e.g. Colpitts or Weinbridge) un- (1.5kΩ) of the mixer to the load desired for the necessary. specified amount of power gain (See Appendix A-2). The input impedance should ideally match 5. Power Amplifier the impedance of the input source through some Once the input signal is upconverted to the desired LC transformation network (i.e. it should be transmission frequency, it must be amplified to matched with the impedance of the antenna, if that achieve maximum transmittable distance. We de- impedance is known.) signed the power amplifier to deliver 100mW of RF power to the load, which is the antenna. We used a two-transistor cascode configuration to Figure 2: Receiver System Blocks construct a class A amplifier, placing an LC match on the output to allow resonant transformation to a 50ohm load impedance (See Appendix A-1). The input to the amplifier comes from the SA602 mixer through a coupling capacitor. Although the class A design of the amplifier causes it to con- sume a great deal of DC power, the cascode implementation allows appreciable RF power gain while minimizing the effects of the Miller capaci- 3. Mixer tance of the input transistor on the amplifier fre- We implemented the mixer on the receiver board quency response. with the same SA602 analog multiplier chip as we used on the transmitter board. This mixer multi- II. The Receiver plies the 24.3MHz input signal from the LNA with The receiver end of the system captures the trans- a 24MHz local oscillator signal and outputs the mitted signal through an antenna and amplifies original modulated 300kHz IF signal. that signal so that it may be downconverted to IF, filtered, and demodulated to the original signal. 4. Crystal Oscillator The following components together perform this We used a 24MHz packaged crystal oscillator to functionality: an input filter, low-noise amplifier, provide the local oscillator signal on the receiver mixer, IF amplifier and filter, phase-locked loop, side of the circuit. This provides a simple and reli- and an audio speaker. able input to the mixer at the correct frequency and large amplitude. 1. Input Filter 5. Intermediate Frequency Amplifier and Filter

4 In order to minimize the amount of noise and dis- I. Transmitter tortion in our system output as well as maximize The following is a discussion of the performance the receivable distance of our circuit, we designed of each of the blocks within the transmitter circuit. an intermediate frequency amplifier and filter stage. The IF amplifier consists of a non-inverting 1. Audio Input and Amplification amplifier with nominal gain of 100V/V, a four- The audio amplifier circuit provides sufficient sig- pole passive Butterworth bandpass filter, and an- nal gain while allowing for adjustment to large other non-inverting amplifier with adjustable gain input signals. We were able to adjust the potenti- < 100. We designed the filter to have a –3dB ometer at the input to the op-amp to accommodate bandwidth of 100kHz and matched the source im- a comfortable speaking distance from the micro- pedance and output load to an arbitrary 50ohm phone. The circuit consumes 36mW of DC power impedance (this value helps ease testing with and has a gain of 20.7 dB at 1kHz. We found the 50ohm test equipment inputs). The input to the frequency response to be less than ideal, however, first amplifier includes a 1.5kohm match to the as the output peaks at 4.63kHz, and from meas- mixer output. For further discussion of the IF am- urements made on the spectrum analyzer the –3dB plifier, see Appendix B-3. bandwidth is 2.75kHz to 8.5kHz. Since the audio range is defined from 20Hz to 20kHz and most 6. Phase-Locked Loop vocal signals fall under 1kHz, this is not the opti- In order to demodulate the IF signal down to the mal bandwidth for the desired input signals. Be- original audio signal, we include a phase-locked cause the frequency response of this circuit is loop at the output of the IF amplifier. Imple- largely determined by the response of the op-amp, mented with the LM565, the PLL “locks” onto the which conceivably has a more than adequate slew frequency variations in the FM signal by provid- rate, it is uncertain as to why the circuit would ing feedback to an internal VCO and outputs a yield such an undesirable response. It is possible voltage corresponding to those frequencies (i.e. that measurements were made without properly the original audio signal). The internal VCO is set tuning the input potentiometer. This could cause to a free-running frequency of 300kHz. The PLL distortion or attenuation of the signal at the meas- has a minimum detectable voltage of 6mV, which ured frequencies. The output potentiometer sets is suitable for this application. For further discus- the output to a DC voltage of 7.5V. See Appendix sion of the operation and performance of the PLL, A-4 for further discussion of this circuit. see Appendix B-3. Table 1: Audio Input Characteristics 7. Audio Output Mic/Audio IN Although an audio amplifier and speaker could be DC Power 36mW added to the receiver to create the audio output, Gain 20.7dB we used an external speaker to output the audio Frequency Response 4.63kHz=fo signal because of time constraints. BW 2.75kHz-8.5kHz Linearity (THD) -44dB at 1kHz

DISCUSSION / RESULTS 2. Voltage-Controlled Oscillator Construction and testing of the system yielded The VCO performs well within the required limits varying results when compared to expectations. of the system. With the 7.5V input from the audio This section discusses the experimental results de- amplifier circuit, the VCO operates at a tunable rived from the separate blocks of each of the two free-running frequency of 300kHz. It consumes system components and examines improvements 48.6mW and has an output power of –24.7dBm. It made as well as possible future improvements to is possible that this low output power is due to the the system. attenuating frequency response of the audio amplifier. With a tuning range of 40kHz to 645kHz and frequency variation with voltage of k = 200kHz/V, 5 the VCO is able to output more than the needed desired frequency response for the amplifier. Cal- bandwidth of 100kHz deviation on the output sig- culated and simulated component values yielded nal. We found that the VCO performance is not undesirable results, and we therefore chose values adversely affected by temperature increases due to according to design equations to create the needed “warming up.” See Table 2 for a summary of response (See Appendix A-1). In general, imped- VCO performance characteristics. ance matching is crucial for delivering maximum power to a load, but in this case our attempted im- Table 2: VCO Performance Characteristics pedance matches reduced the output power of the VCO power amplifier. This was especially true of the DC Power 48.6mW match to the output of the mixer. Difficulty in de- Output Power -24.7dBm signing this match comes in approximating the Tuning Range (freq) 40kHz-645kHz input capacitance of the input transistor. Likewise k (Hz/V) 200kHz/V matching approximate output capacitances to an Bandwidth 605kHz Temperature Stability cold:302.5kHz warm:303.5kHz Table 4: Power Amplifier Characteristics Power Amp DC Power 360mW 3. Mixer Power Gain 26dBm Frequency Response fo=22.4Mhz The transmitter mixer takes a -3.7dBm free- BW 17.5-30MHz running 300kHz input from the VCO and multi- Efficiency Po/Pdc=0.52% plies it with the local oscillator signal at 24MHz to Input Match Zin=18-256j, produce -19.0 dBm of conversion gain to the Mixer_out=1.5k; n=0.707 24.3MHz sideband signal. Output harmonics of the IF signal appear 20dBm down from the desired unknown antenna impedance proved to be a diffi- signal, and so these do not affect the system per- cult task that we chose to forego in order to focus formance or distort the information signal. The on system integration and optimization of other mixer provides 56dBm of signal-to-noise ratio at blocks. Table 4 summarizes the power amplifier its output, so that the mixer does not introduce an characteristics. appreciable amount of noise to the system.

4. Local Oscillator Table 5: Overall Transmitter Performance We used a 24MHz crystal in conjunction with the Transmitter on-chip SA602 Colpitts oscillator, and this pro- DC Power 612mW duced a reliable local oscillator signal. Output Power 2.75dBm Max Bandwidth 6.4MHz 5. Power Amplifier Lifetime (9V Batt) * 8.53 hours The power amplifier underwent a few iterations Max Receivable Distance 1/2mile * Lifetime is measured according to the specified mAh before we were able to make it function properly. rating of the battery. System will fail before this time, We first attempted to design a push-pull amplifier due to changing supply voltage. with PMOS and NMOS transistors, but we found that the transistors were incapable of delivering enough current to the load to achieve the desired power gain. Reverting to the class A cascode con- Overall Transmitter Performance figuration, we then found difficulty in creating the The transmitter outputs 2.75dBm to a 50ohm impedance and consumes 612mW of power with a Table 3: Transmitter Mixer Characteristics maximum transmittable distance of about .5 miles Mixer (given the discussed receiver). One improvement DC Power 24.27mW that would help suppress the effects of coupled Conversion Gain -19.0dBm FM and ambient signals would be to encase the 6 SNR 56dBm transmitter circuit in an RF shield. We found this 24.3MHz. In addition, matching the input of the to improve the performance of the receiver LNA, which has a measured input impedance of greatly. 300 Ω, to the source impedance of the antenna could greatly improve the amount of power trans- II. Receiver ferred. Because we used simple wire antennae, however, we decided not to focus our efforts on The following is a discussion of the performance this matching issue. A summary of LNA perform- of each of the blocks within the receiver circuit. ance can be found in Table 6.

1. Low-Noise Amplifier Input Filter 3. Mixer The input filter to the LNA produced very little The mixer on the receiver side consumes signal power attenuation (-.2dBm) and had a fre- 26.19mW of power and has a conversion gain of quency response centered at 24.45MHz, with 20dB from the 24.3MHz input to the 300kHz out- –3dB points at 15.82MHz and 36.5MHz. We put. The signal-to-noise ratio of 54 dBm at the found that this helped in filtering out unwanted output provides good suppression of ambient signals from radio stations and other sources. noise. In general the receiver mixer performed similarly to the transmitter mixer (See Table 7). 2. Low-Noise Amplifier One troubling feature about the mixers on both the We rebuilt the LNA described in "Construction of transmitter and receiver end is that they seem to a 20dB Shunt and Series Low-Noise Amplifier" exhibit very little carrier suppression. We believe (Appendix B) and found that it produced the de- that better carrier suppression could be achieved sired gain and frequency response. Unsatisfied by taking a double-ended output from the mixer. with the power consumption of that design (about This would create a 180 degree phase shift be- 63mW), however, we decided to redesign the tween the carrier signals at the output, so that the LNA with an inductive load to replace the resis- carrier would tend to annihilate itself while the tive load of the old design (See Appendix A-2). sidebands would be increased. Implementation of The new LNA produced more than the specified this proves difficult, however, since ultimately the gain needed (31dBm) and consumed little power mixer must provide a single-ended output. Further at 6.60mW, but we found that the frequency re- discussion of mixer performance characteristics sponse was not centered around the desired can be found in Appendix B. 24.3MHz. Instead, the response peaked around 20.7MHz and functioned with a bandwidth of Table 7: Receiver Mixer Performance 18.7MHz to 22.9MHz. The response produced Mixer –4dB from its peak at 24.3MHz – this probably DC Power 26.19 mW caused a great deal of degradation in overall sys- Conversion Gain -20dBm Frequency Response Table 6: LNA Input Characteristics Peak 3dB Points 19 MHz LNA LNA Input Filter LNA DC Power 6.60 mW 30 MHz Power Gain -.2dBm 31 dBm Bandwidth 11 MHz Frequency Response SNR 54 dBm Peak 24.45 MHz 20.7 MHz LO Input Power 19dBm 3dB Points 15.82 MHz 18.7 MHz 36.5 MHz 22.9 MHz SNR 50 dBm Input Match 17+j295 4. Crystal Oscillator The crystal oscillator used as the local oscillator tem performance. The problem could be solved by for the receiver mixer provides a steady 24MHz tuning the output filter match of the LNA so that signal to the circuit at close to 4.7V amplitude. It the response centers more closely around is important for the carrier signal to be large in

7 terms of mixer efficiency (a large signal causes the This may also be an issue of the amplifiers pro- multiplier outputs transistors to switch completely viding too much gain, so that the op-amp outputs on and off, supplying maximum current to the are hitting the power supply rails. This would also load). The signal produced by the crystal oscillator explain why the total system gain (55dBm) is may be too large, however, as we believe it cou- smaller than the sum of the gain of the individual ples into many of the other signal paths on the re- blocks. Further discussion of the IF filter and am- ceiver board and also seems to produce a 160kHz plifier is found in Appendix B. harmonic oscillation in the main signal path. The signal does not degrade system performance, as it 6. Phase-Locked Loop is 10-15dBm down from the IF signal, but with The PLL had a minimum detectable signal voltage lower amplitude inputs it could depreciate the re- of around 6mV. This is sufficiently large for this ceivable distance. To verify that the crystal oscil- application given the amount of amplification on lator is the cause of these harmonics, however and the signal prior to the PLL input. The lock range to reduce the amount of interference caused by the of the PLL is 172kHz to 468kHz, which is large oscillator, we should replace it with the same on- enough to accommodate the desired 100kHz chip Colpitts configuration used with the trans- range. We found variation in the supply voltage to mitter mixer. have considerable effect on the PLL lock range. At 16 V supply, the range diminishes to 136kHz to 344kHz and a minimum detectable input ampli- Table 8: IF Amplifier and Filter Characteristics tude of 13mV. This finding implies that the lock IF Amp IF Filter IF Total range would be affected by variations in battery DC Power 82.2 mW voltage as power is drained from the batteries and Voltage Gain -8.39 dBm 71 dBm Frequency Response therefore can have an effect on the maximum re- Peak 316 kHz 298 kHz ceivable distance. More discussion of the PLL per- 3dB Points 253 kHz 255 kHz formance is found in “Construction of a Phase- 400 kHz 353 kHz Locked Loop and a 300kHz Intermediate Fre- Bandwidth 143 kHz 90 kHz quency 4-pole Butterworth passive filter and am- SNR 45 dBm plification system" (Appendix B).

Table 9: Phase-Locked Loop Characteristics 5. Intermediate Frequency Amplifier and Filter PLL We found the IF amplifier and filter to produce a DC Power 41.85 mW total gain of 71dBm, with the filter attenuating the Minimum Input Signal 6mV signal by 8.39dBm. This attenuation is larger than Lock/Hold Range 172 - 468 kHz expected but is due to the use of resistors and Linearity (THD) -5.4 dB lossy passive components in the construction of Loop Gain 1.12e6 the Butterworth filter. The overall IF amplifier k 263 kHz/V block yields favorable results, with an overall fo 300 kHz bandwidth of 90kHz and a peak center frequency SNR 40 dB of 298kHz. An issue that could be cause for further consideration is that the amplifier tends to 7. Audio Output boost 300kHz harmonics in addition to the desired For the purpose of testing, we used a direct output IF signal. In measuring the output of the first am- (through an AC coupling capacitor) to a battery- plifier stage, we found that the harmonic at powered speaker for our circuit. In order to make 600kHz appears greater than the 300kHz signal by the receiver self-sufficient, we would need to build 4 dBm. This is rectified at the output of the filter, an audio amplifier to drive a speaker. We found where the signal is 4 dBm above the harmonic, the speakers we used to provide a relatively clear and at the output of the second amplifier, the sig- and discernible output. nal appears 10dBm greater than the harmonic.

8 8. Other Comments larly when we touched our shielding to a large metallic ground (e.g. a fire hydrant or stop sign). • Voltage Reference Doing this reduced the amount of background Because of the use of battery supply voltage, we noise and allowed us to hear the transmitted signal implemented a 4.5V reference to provide a “fake” more clearly. ground on each board for the circuit blocks need- ing this voltage reference: the IF amplifier, crystal III.Transmitter/Receiver System oscillator power, and the VCO. This circuit is de- The transmitter and receiver system collaborated scribed in Appendix A-3. well, with a maximum transmittable distance of about 1/2 mile. In general, we found that matching • Antennae of impedances is a key factor in maximizing sys- In our initial design, we attempted to use CB an- tem performance. Matching impedances allows for tennae for transmission and reception, and we de- maximum power transfer as well as minimization signed impedance matching networks (passive L of travelling wave reflections in the transmission and C components). We found these networks in- lines. The first improvement in this respect can be effective, however, when used with the antennae. made in matching the output of the transmitter and Later finding the antennae to be designed for a the input of the receiver to their respective anten- 27MHz system, we then resorted to simple quarter nae will help deliver maximum power to the re- wavelength 11' wire antennae. For optimal per- spective loads. In addition, matching between formance, antennae with known impedances stages within the two component blocks can be should be used, and the receiver input and trans- improved, most notably between the transmitter mitter output impedances should be matched to mixer and the power amplifier. We did attempt to the impedances of the antennae. build matching networks in each of these loca- tions, but they tended not to yield the desired fre- Overall Receiver Performance quency response, due to variations in component Overall the receiver performs well, with a mini- values, stray parasitic capacitances and transistor mum clear detectable signal of –90dBm and a input capacitances. We need to conduct a more complete loss of signal at –115dBm in lab. The thorough characterization of input / output imped- total harmonic distortion measured with a 1kHz ances before we can attempt to match to them. input a nominal amplitude is 7.1%. In field testing, we found the maximum receivable distance to be CONCLUSION 5/8 mile using a 20dBm transmitter. We found We designed and built a 24.3 MHz FM transmitter that the receiver’s performance is very sensitive to / receiver system with both functional chips and lab probings. Often replacing a component or re- discrete components. We successfully integrated a soldering a power wire would lead to 20dBm in number of circuit blocks to perform the required system improvement or degradation. In general FM modulation and demodulation. Maximization reliability can be improved with cleaner wiring of performance proved to come through enough and a more modular circuit layout that allows for power amplification in transmission and low-noise easier debugging and separation of components. amplification in reception. We found that there is We found that in field testing, the RF shielding in such a thing as too much amplification, however, the form of a Walmart “grease” pot helped a great which can cause distortion as with the IF ampli- deal in minimizing coupled radio signals, particu- fier. In addition, impedance matching is an important consideration, although reliable characteri- Table 10: Overall Receiver Performance zation of the impedances to be matched is neces- Receiver sary for this to be an effective improvement to the DC Power 288 mW system. In addition, tuning the two system com- System Gain (pre-PLL) 55 dBm ponents to work together at the correct frequencies System BW 90 kHz helps the system function cohesively. The trans- System THD 7.1 % mitter bandwidth is 6.4MHz with a power output Lifetime (9V Batt) 18.1 hours Min Detectable (clear) Signal -90dBm 9 of 2.75dBm and DC power consumption of 612mW. The receiver consumes 288mW of power and can detect signals down to –115dBm. The system achieves a maximum receivable distance of .5 miles.

10 APPENDIX A-1: POWER AMPLIFIER

CIRCUIT DESIGN THEORY Figure 2: Final Power Amplifier Design We attempted a few iterations in the power amplifier design. The first was to create a class AB amplifier in a push-pull configuration as in Figure 1. The circuit has a voltage gain of unity, and the di-

Figure 1: Initial Power Amplifier Design

In designing the input and output stages to the power amplifier, we considered the input and output capacitances of the transistors. The devices used have input capacitances of 38pF and output capacitances of 25pF. The input network is designed to create a real impedance at the input which is matched to the 1.5kΩ impedance of the ode-connected transistors help decrease the non- mixer. The output network is designed to match linearities in the output. We thought that using the output to a 50Ω antenna impedance. The AC high-power MOS transistors in this design would load of the amplifier is an inductor in parallel with greatly increase the power efficiency of the circuit a capacitor and resistor in series. With a target of over the traditional cascoded class A design, but 20dBm, we designed the amplifier to have when we tried to implement the circuit, we found 18.75dBm of gain, where power gain is given by that the transistors could not source enough cur- the equation PRRg==2 75⇒ 18. 75dBm, rent to supply the power gain needed, despite the Gain s l m where Rs=50Ω is the input impedance, R =150Ω fact that the purported specifications should be L is the tank resistance of the load, and gm was as- adequate. This design is normally implemented sumed to be 0.1S. We calculated the center fre- with bipolar transistors, so perhaps use of MOS quency using real lab component values to be technology and the quadratic relationship of out- 30.1MHz using this equation: put current to input voltage caused the problems 1 1 1 2 L described above. f =    ===30. 1MHz R 150Ω ot 2π  LC− R22 C  CR Having run into this obstacle, we reverted to the class A cascode design, as shown in Figure 2. The DISCUSSION / RESULTS two transistors are VN10KLS NMOS devices, and each is DC biased with 10kohm potentiometers The measured amplifier power gain is 26dBm, and between ground and Vcc. Each transistor must be the center frequency is 22.4MHz. The amplifier biased such that the amplifier is able to output consumes 360mW of DC power. The calculated large signals without turning off one or both of the inductor and capacitor values yield a very differ- transistors. Because of this, the bottom transistor ent result in the real circuit from the projected re- is biased at 2V, which is large enough to sustain sult. This is mostly due to the fact that the input the transistor turn-on voltage of 1.5V and maxi- and output capacitances used in calculation were mum input signals of around 250mV. The cascode derived from the data sheet and are only nominal transistor is biased at the power supply, because values that can vary from transistor to transistor. we achieved optimal power gain with this configu- In addition, the projected gm =.1 S of the transis- ration. tor is only a rough estimate of the actual gm. We had to increase the value of the output capacitor in 11 order to achieve the correct center frequency, and ended up with a value that did not match theory very well.

When integrating the power amplifier into the transmitter circuit, we found the 50Ω input matched to greatly degrade system performance and frequency response, and in the end we chose to simply connect the mixer output and the power amplifier input through an AC coupling capacitor.

CONCLUSION

In general the power amplifier functioned well, although definite improvements can be made. Matching between the mixer and the amplifier input as well as a better defined match between the output and the antenna would help to improve performance and power delivered. The class A design provides high, linear power gain at the cost of efficiency, because it draws a constant DC current even when not transmitting. A preferable configuration would be a class C or better amplifier, which draws minimal DC power unless it is actu- ally amplifying a signal.

12 APPENDIX A-2: LOW-NOISE AMPLIFIER

CIRCUIT DESIGN THEORY 83. β 9-.7 = 8.3V. Therefore Rf = , where β is as- Ic We constructed the LNA described in Appendix sumed to be 75. B-1 and it initially consumed 63mW of power while barely producing 20dBm of power gain. In addition to the LC filter match on the output, Although this was satisfactory, we decided to at- we also designed an LC series input filter to cut tempted a new, simpler design, which uses fewer down on ambient noise and unwanted signals cou- components and considerably less power. pling into the circuit. We chose the component 1 The new design is shown in Figure A-2-1. The values using the relation fo = and tested 2π LC advantage of this design is that the designer may the filter separately with different values to get the first set the output current of the transistor, and correct match. therefore specify the power consumption in the beginning of design. In addition, replacing the re- DISCUSSION / RESULTS sistive load with an inductive one allows the output voltage to swing past the positive power rail The LNA produces a gain of 31dBm and con- and also allows for ease of output impedance sumed 6.60mW of power. Simulations in HSPICE matching. Once the current Ic is set, we have the produced similar results after the initial design, Figure A-2-1: New LNA Design and so the high gain was not surprising. The circuit's power consumption is close to 4mW lower than expected, however, which means that the current being drawn is lower than expected as well. Both of these deviations from the design theory could be explained by the fact that the actual source impedance measured was close to 300Ω, which would increase the actual power output of the transistor. In addition, the gm of the transistor might be higher than expected from theoretical transconductance gm of the transistor through the values, which would also give increase in power relationship gm = Ic/Vt. Because the power gain gain. It is also possible that the beta of the tran- of the amplifier is known through the relationship sistor is lower than expected, which would mean 2 PgRR= mSL and assuming a 50Ω source imped- less base current flows into the transistor and less ance, we can use an LC match to transform the collector current flows in the output. load impedance to whatever RL we need to give us the required gain. We designed for 25dBm of gain, The LNA filter peaks at 24.45MHz and has -3dB to overshoot the requirement of 20dBm. We de- points at 15.82MHz and 36.5MHz. Although this cided to use a relatively large inductor in the col- seems like a wide spectrum of values, the filter lector of the transistor and a full LC match on the does help in keeping out much higher frequency output, but in retrospect, we could have used the FM signals (most radio stations transmit above load inductor as part of the LC match. We chose 90MHz).

Rf based on the assumption that IB, the base current through the transistor, is equal to the current The LNA itself has a frequency response that is off-center from the ideal peak response. The out- through Rf, and Rf must sustain a voltage drop of put peaks at 20.7MHz and has -3dB points at 18.7MHz and 22.9MHz, which places it out of the range of our system. 24.3MHz comes at -4dB 13 from the peak of the output. This can be rectified by adjusting the output match capacitor (perhaps by using a variable capacitor in its place).

Although the SWR meter gave a reading of 17+j295 Ω input impedance, a resistive divider test yielded 300 Ω as the real input impedance. We also did not know the impedance of the antenna. Thus, unreliability in impedance measurements made it difficult to accurately match the input of the LNA. A summary of the LNA filter performance is found in Table A-2-1. Table A-2-1: LNA Filter Characteristics LNA LNA Input Filter LNA DC Power 6.60 mW Power Gain -.2dBm 31 dBm Frequency Response Peak 24.45 MHz 20.7 MHz 3dB Points 15.82 MHz 18.7 MHz 36.5 MHz 22.9 MHz SNR 50 dBm Input Match 17+j295

CONCLUSION

The LNA functions well, with an appreciable power gain of 31dBm, although adjustments to the frequency response and input matching will greatly improve its performance.

14 APPENDIX A-3: 4.5 V REFERENCE

CIRCUIT DESIGN THEORY

Because a few of our circuits required a "fake" ground between the power supply rails (the IF amplifier for instance) or some other non-9V reference, we implemented an op-amp buffered voltage divider reference for use in these circuits. We matched the two 100kohm resistors with each other to ensure a reliable half-voltage point. See Figure A-3-1. The IF Amplifier, Crystal Oscilla- tor, and VCO use this reference.

Figure A-3-1: 4.5V Reference

DISCUSSION / RESULTS

The circuit performed as designed, producing a voltage reference at half-voltage from the supply.

CONCLUSION

The ease of implementation of this circuit makes it a good alternative to bulky and high powered voltage-regulators, as it allows the designer to specify any reference between the power rails that he or she needs in the circuit.

15 APPENDIX A-4: AUDIO INPUT

CIRCUIT DESIGN THEORY A summary of performance characteristics appears in Table A-4-1. We used a standard microphone amplification circuit for the audio input to the transmitter. The circuit includes a current-limiting resistor on the in- Table A-4-1: Audio Input Performance put and a voltage-divider potentiometer for use in Mic/Audio IN adjusting the gain of the microphone. The op-amp DC Power 36mW is configured as an inverting amplifier with its Gain 20.7dB output tied to a potentiometer through an AC cou- Frequency Response 4.63kHz=fo pling capacitor. The output potentiometer allows BW 2.75kHz-8.5kHz Linearity (THD) -44dB at 1kHz us to set the DC input voltage to the VCO, which in turn helps set the free-running frequency of the VCO. The circuit is shown in Figure A-4-1.

CONCLUSION Figure A-4-1: Microphone Amplification Although it is unclear why the frequency response behaves as it does, the microphone amplifier circuit seemed to work sufficiently for our application. If measurements were not faulty, however, and the circuit is attenuating the signal at the desired frequency range, then this is a point in the circuit to adjust and improve. This can be done by verifying accuracy in measurements first, and then perhaps replacing the op-amp and adjusting component values to target the cause of the undesired DISCUSSION / RESULTS response. We found adjusting the input potentiometer of the microphone amplifier helped a great deal in adjusting the speaking distance needed from the microphone. Initially, we had to cup our hands over the microphone and talk into it closely to achieve a clear output. By adjusting the potentiometer, we can achieve a clear output at a comfortable speaking distance (about 3/4 foot from the microphone).

The output of the circuit yielded a poor frequency response that does not adequately span the audio range of 20Hz to 20kHz. This could be due to nonlinearities in the op-amp or possibly faulty measurement techniques. This response was measured using the sweeping spectrum analyzer.

16 APPENDIX B: FORMAL LAB WRITE-UP REFERENCES

B-1. Construction of a 20dB shunt and Series Low-Noise Amplifier with matched 50ohm input and output impedances, a 24MHz LC Filter Tank Circuit, a single diode 20kHz RC Peak Detector, and a 17dB Conversion Gain Four-Quadrant Multiplier for use in an FM transmitter/receiver system Tung, Alex

B-2. Construction of Two types of 24MHz Colpitts Oscillators using a single transistor and an SA602 Four-Quadrant Multiplier, and experimentation with a LM566 Voltage-Controlled Oscillator Tung, Alex

B-3. Construction of a Phase-Locked Loop and a 300kHz Intermediate Frequency 4-Pole Butterworth passive filter with dual non-inverting amplifiers for use in the demodulation of FM signals in an FM transmitter/receiver system Tung, Alex