energies

Article Full-Bridge Active-Clamp Forward-Flyback Converter with an Integrated Transformer for High-Performance and Low Cost Low-Voltage DC Converter of Vehicle Applications

Jaeil Baek 1 and Han-Shin Youn 2,*

1 Department of Electrical Engineering, Princeton University, Princeton, NJ 08540, USA; [email protected] 2 Department of Electrical Engineering, Incheon National University, 119, Academy-ro, Yeonsu-gu, Incheon 406840, Korea * Correspondence: [email protected]



Received: 14 January 2020; Accepted: 12 February 2020; Published: 16 February 2020


Abstract: This paper presents a full-bridge active-clamp forward-flyback (FBACFF) converter with an integrated transformer sharing a single primary winding. Compared to the conventional active-clamp-forward (ACF) converter, the proposed converter has low voltage stress on the primary switches due to its full-bridge active-clamp structure, which can leverage high performance Silicon- metal–oxide–semiconductor field-effect transistor (Si-MOSFET) of low voltage rating and low channel resistance. Integrating forward and flyback operations allows the proposed converter to have much lower primary root mean square (RMS) current than the conventional phase-shifted-full-bridge (PSFB) converter, while covering wide input/output voltage range with duty ratio over 0.5. The proposed integrated transformer reduces the transformer conduction loss and simplify the secondary structure of the proposed converter. As a result, the proposed converter has several advantages: (1) high heavy load efficiency, (2) wide input voltage range operation, (3) high power density with the integrated transformer, and (4) low cost. The proposed converter is a very promising candidate for applications with wide input voltage range and high power, such as the low-voltage DC (LDC) converter for eco-friendly vehicles.

Keywords: active-clamp converter; DC-DC converter; eco-friendly vehicle; forward-flyback converter; high efficiency; high power density; integrated transformer; low-voltage DC converter; soft-switching

1. Introduction Nowadays, eco-friendly vehicles such as hybrid electric vehicle and electric vehicle have been researched and developed to satisfy the strengthened CO2 emission regulations as well as to increase fuel economy [1–3]. A lot of power conversion systems have been studied for eco-friendly vehicles. These power conversion systems require not only a high efficiency to improve the fuel economy but also a high power density because those are installed in the engine and trunk rooms of eco-friendly vehicles. Moreover, the price of eco-friendly vehicles is much higher than that of the traditional vehicles due to additional power conversion systems, i.e., drive motor, inverter, converters, and battery. Therefore, reducing the production cost is also one of the most important design considerations for eco-friendly vehicles. Furthermore, the power consumption caused by electronic devices of vehicles has been rapidly increased due to the remarkable improvement of information technology and development of electronic system such as advanced driver assistance system (ADAS), motor drive steering system (MDPS), traction control system (TCS), information devices, etc. [4].

Energies 2020, 13, 863; doi:10.3390/en13040863 www.mdpi.com/journal/energies Energies 2019, 12, x FOR PEER REVIEW 2 of 17 Energies 2020, 13, 863 2 of 17 Energies 2019, 12, x FOR PEER REVIEW 2 of 17 To supply power to electronic devices of vehicles, a LDC converter that charges low voltage (LV) battery (e.g., 13.6 V) with the energy stored in high voltage (HV) battery (e.g. 300 V) is commonly ToTo supply supply power power to to electronic electronic devices devices of of vehicles vehicles,, a a LDC LDC converter converter that that charges charges low low voltage voltage (LV) (LV) used in eco-friendly vehicles. The LV battery is usually controlled to maintain its nominal voltage. batterybattery (e.g., 13.613.6 V)V) withwith the the energy energy stored stored in in high high voltage voltage (HV) (HV) battery battery (e.g., (e.g. 300 300 V) is V) commonly is commonly used Namely, the LDC converter should be designed to cover wide input voltage range of the HV battery. usedin eco-friendly in eco-friendly vehicles. vehicles. The LV The battery LV battery is usually is usually controlled controlled to maintain to maintain its nominal its nominal voltage. voltage. Namely, Due to the increased power consumption of high-performance electronic devices (ADAS, MDPS, and Namely,the LDC the converter LDC converter should be should designed be designed to cover wide to cover input wide voltage input range voltage of the range HV of battery. the HV Due battery. to the so on) in vehicles, the discharging current of the LV battery has been increased. Accordingly, to Dueincreased to the powerincreased consumption power consumption of high-performance of high-performance electronic electronic devices (ADAS, devices MDPS, (ADAS, and MDPS, so on) and in maintain the LV battery in normal range, the nominal output current of the LDC converter, i.e., sovehicles, on) in thevehicles, discharging the discharging current of the current LV battery of the has LV been battery increased. has been Accordingly, increased. to Accordingly, maintain the LVto charging current of the LV battery, has been also continuously increased. As a result, it is getting maintainbattery in the normal LV battery range, in the normal nominal range, output the current nominal of theoutput LDC current converter, of the i.e., LDC charging converter, current i.e., of important for the LDC converter to achieve higher heavy load efficiency. Currently, plug-in hybrid chargingthe LV battery, current has of beenthe LV also battery, continuously has been increased. also continuously As a result, increased. it is getting As important a result, it for is the getting LDC importantconverterelectric vehicles tofor achieve the (PHEVs)LDC higher converter usually heavy to loadadopt achieve effi aciency. HV higher batte Currently, heavyry with load plug-in240–413 efficiency. hybrid V (nominal Currently, electric 360 vehicles plug-inV), and (PHEVs) hybridHEVs do electricusuallya HV batteryvehicles adopt awith HV(PHEVs) battery200–310 usually with V operating 240–413 adopt a V HVrange (nominal batte (nominry 360 with V),al 240–413270 and V). HEVs BothV (nominal do uses a HV approximatedbattery 360 V), with and 200–310HEVs 13.6 doV VLV aoperatingbattery. HV battery In range addition, with (nominal 200–310 the LDC 270V operating V).converter Both usesrange is designed approximated (nomin upal 270to 2kW 13.6V). Both Vmeaning LV uses battery. veryapproximated Inhigh addition, output 13.6 the current V LDC LV of battery.converter140–160 In A. isaddition, designed the up LDC to 2 converter kW meaning is designed very high up output to 2kW current meaning of 140–160 very high A. output current of 140–160InIn orderA.order to to achieve achieve high high e ffiefficiencyciency and and high high power power density density under under wide wide input input voltage voltage range range and and highhighIn outputoutput ordercurrent currentto achieve specifications, specifications, high efficiency the the conventional andconvention high poweral LDC LDC density converter converter under adopts adopts wide a phase-shiftedinputa phase-shifted voltage full-bridgerange full-bridge and high(PSFB)(PSFB) output converter converter current as as shownspecifications, shown in Figurein Figure the1 due convention 1 todue the to zero-voltage althe LDC zero-voltage converter switching adoptsswitching (ZVS) a phase-shifted characteristic (ZVS) characteristic full-bridge and twice and (PSFB)poweringtwice poweringconverter operation operationas inshown one switching in Figureone switching period 1 due ofto period the the PSFB zero-voltage of converterthe PSFB switching [converter5–9]. However, (ZVS) [5–9]. sincecharacteristic However, the operating since and the twicedutyoperating ratiopowering atduty the operationratio nominal at the inputin nominal one voltage switching input is farvoltage period small, is of thefar the PSFBsmall, PSFB converter the converter PSFB hasconverter [5–9]. large However, circulating has large since circulating current the operatingduringcurrent freewheeling during duty ratio freewheeling at periods the nominal periods as shown input as inshownvoltage Figure in is1 b,Figurefar which small, 1b, causesthe which PSFB significant causes converter significant high has large conduction high circulating conduction loss currentatloss heavy at duringheavy load condition.loadfreewheeling condition. Furthermore, periods Furthermore, as shown the PSFB the in Figure converterPSFB converter1b, which has large causeshas systemlarge significant system volume volumehigh because conduction because of two of lossmagnetictwo at magnetic heavy components load components condition. (transformer (transformerFurthermore, and output and the PSFBoutput inductor converter inductor shown has inshown Figurelarge in system2 b),Figure which volume 2b), must which because be firmlymust of be twofixedfirmly magnetic by fixed using by components additional using additional bulky (transformer devices, bulky anddevices, and large output and size largeinductor of snubber size shownofcircuits snubber in toFigure circuits constraint 2b), to constraintwhich voltage must stresses voltage be firmlyonstresses the fixed secondary on bythe using secondary diodes. additional As diodes. a result, bulky As the devices, a conventional result, and the large conventional PSFB size converter of snubber PSFB makes circuits converter diffi tocult constraint makes to minimize difficult voltage the to stressessizeminimize of theon powerthethe sizesecondary control of the unitpowerdiodes. (PCU) control As shown a result, unit in (PCU) Figurethe conventional shown2a which in includesFigure PSFB converter2a an which inverter, includesmakes LDC difficult converter,an inverter, to minimizeandLDC control converter, the board. size and of thecontrol power board. control unit (PCU) shown in Figure 2a which includes an inverter, LDC converter, and control board.

(a) (b) (a) (b) Figure 1. Conventional phase-shifted full-bridge (PSFB) converter. (a) Circuit diagram. (b) Primary FigureFigure 1. 1. ConventionalConventional phase-shifted phase-shifted full- full-bridgebridge (PSFB) (PSFB) converter. converter. ( (aa)) Circuit Circuit diagram. diagram. ( (bb)) Primary Primary current waveform. currentcurrent waveform. waveform.

(a()a ) (b)( b) Figure 2. Pictures of power control unit (PCU) and LDC converter for vehicle applications. (a) PCU. FigureFigure 2. 2. Pictures Pictures of of power power control control unit unit (PCU) (PCU) and and LDC LDC converter converter for for vehicle vehicle applications. applications. (a) (PCU.a) PCU. (b) LDC. (b(b) )LDC. LDC.

Energies 2020, 13, 863 3 of 17

Many DC/DC topologies with low circulating current have been developed to reduce the conduction loss of the conventional PSFB converter [5–11]. The converter presented in [7] reduces the circulating current of the PSFB converter by using large resonant inductance. However, it has serious disadvantages of two additional switches and large volume of auxiliary inductor, which results in increasing the volume and cost of the LDC converter. The converters shown in [8,11] can obtain small circulating current by using an additional capacitor in the primary side or a coupled inductor in the secondary side. However, an additional capacitor in [8] cannot be small to handle high voltage stress and high current stress. A coupled inductor in [11] requires larger core size compared to a discrete output inductor to keep the same power loss. Moreover, these converters should have two separate magnetic components. Therefore, these converters are still limited in improving power density of the LDC converter. To complement large circulating current of the conventional PSFB converter, many active-clamp-forward (ACF) converters have been studied [12–19]. These ACF converters have advantages of the zero circulating current and low number of switches, which results in lower conduction loss compared to the conventional PSFB converter. However, despite of low conduction loss, these converters suffer from high voltage stress on the primary switches, which becomes far worse taking into account wide input voltage range. As a result, the ACF converters in [12–19] should use low performance of Si-MOSFETs increasing conduction loss and switching loss. In order to improve this drawback and achieve high efficiency, the ACF converters can adopt silicon-carbide (SiC) MOSFETs which has high voltage rating, small on-resistance, and small parasitic capacitance. However, using SiC-MOSFETs significantly increases the cost of LDC converter. Moreover, the ACF converters still use two magnetic components increasing the volume of converter. To relieve the voltages stress on the primary switches of the ACF converters, three-switch ACF converters were researched and developed [14,15]. However, one of three switches still suffer from high voltage stress. Moreover, the converters in [14,15] should use complex driving circuits and two magnetic components. To reduce the number of the magnetic components, ACF converters with an integrated magnetic were represented as shown in Figure3[ 16,17]. Although these converters utilize only one integrated magnetic, the primary and secondary windings are wound the outside of the core shown in Figure3, which requires additional shield and structure causing the extra cost and volume to minimize the adverse effect of electromagnetic interference (EMI). As a result, the conventional and previously studied ACF Energies 2019, 12, x FOR PEER REVIEW 4 of 17 converters have limitations in commercialization especially for vehicle applications.

C1 D1 Np NL CO RO

CO NP1 NS1 Cc Q1 NS RO

D1 Lr VS VS QA NP2 NS2 Q2

QM D2 D2 C2

(a) (b)

FigureFigure 3. 3.ConventionalConventional active-clamp-forward active-clamp-forward (ACF) (ACF) converters converters with integrated with integrated magnetics. magnetics. (a) Integration(a) Integration of a transformer of a transformer and an and output an output inductor inductor [16]. ( [b16) Integration]. (b) Integration of two of transformers two transformers [17]. [17].

In this paper, the full-bridge active-clamp-forward-flyback (FBACFF) converter adopting an 2. Operational Principle integrated transformer sharing single primary winding is proposed for the LDC converter of vehicle applications.Figures 4 and The proposed5 show the FACFF circuit converter diagram has and the operational following advantages key waveforms compared of the to conventionalproposed converter,topologies: respectively. (1) active-clamp In the proposed structure ofconverter, the proposed the primary converter switches minimizes Q1 and the Q circulating4 are turned current on at of thethe same conventional time to transfer PSFB converter,the power whichfrom the results input in to higher the output efficiency; through (2) full-bridgethe forward structure transformer of the (Tforproposed). Meanwhile, converter the switches relieves Q high2 and voltage Q3 are stressdriven on complementarily the primary switches with Q of1 and the Q conventional4 to reset Tfor ACFas wellconverter as to deliver and thusthe energy the proposed stored in converter the flyback can transformer adopt cost-competitive (Tfly) into the Si-MOSFETsoutput. For the and sake achieve of analysis,high effi severalciency assumpti withoutons high-cost are made SiC-MOSFETs; as follows: (3) it can have lower diode voltage stress than the 1) all parasitic components except for those specified in Figure 4 are ignored; 2) a clamp capacitor (CC) is large enough to be considered as a constant voltage source (VCc ); 3) the output voltage (VO) is constant; 4) the transformer turns ratio (n) of the forward and flyback transformers (Tfor and Tfly) is N/1, where N is the number of the primary winding.

iO T Q1 vds1 Tfor fly Q3 vds3 n:1 n:1

VCc iD1 iD2 VO Llkg Lm,for Lm,fly iLlkg Cc CO RO VS Tint, n:1

vD1 vD2 Q2 vds2 Q4 vds4 D1 D2

(a)

D1 Tfor Q1 Q3

Cc CO VS RO

Q2 Q4 Tfly D2 Tint, n:1 (b)

Figure 4. Proposed converter. (a) Circuit diagram. (b) Circuit diagram with a proposed integrated transformer.

Energies 2019, 12, x FOR PEER REVIEW 4 of 17

Energies 2020, 13, 863 4 of 17

C1 D1 Np NL CO RO

CO NP1 NS1 Cc Q1 PSFB converter, whichNS enables the proposed converterRO to use high-current rating diodes; and (4) a

proposed single integrated transformerD reduces1 volume and cost of theLr LDC converter. The primary VS VS and secondaryQA windings of the proposed integrated transformer are wound insideNP2 N ofS2 the transformer Q2

QM D2 core, which enables the proposed converterD2 not only to minimize theC2 adverse effect of EMI but also to eliminate additional snubber circuits due to small leakage inductance. As a result, the proposed converter can achieve high efficiency, high power density, and low cost compared to the conventional (a) (b) topologies. In order to verify the validity of the proposed converter, a prototype with 200–310 V input andFigure 1.8 kW3. Conventional (13.6 V/130 A) active-clamp-forward output was built and the(ACF) experimental converters results with areintegrated presented magnetics. compared ( witha) theIntegration conventional of a transformer PSFB converter and an which output is theinductor most widely[16]. (b) used Integration in the commercialized of two transformers LDC [17]. converter. 2. Operational Principle 2. Operational Principle Figures4 and5 show the circuit diagram and operational key waveforms of the proposed converter, Figures 4 and 5 show the circuit diagram and operational key waveforms of the proposed respectively. In the proposed converter, the primary switches Q1 and Q4 are turned on at the same time 1 4 converter,to transfer respectively. the power In from the the proposed input to theconverter, output throughthe primary the forward switches transformer Q and Q (Tfor are). Meanwhile,turned on at the samethe switches time toQ transfer2 and Q 3theare power driven complementarilyfrom the input to with theQ output1 and Q through4 to reset theTfor asforward well as transformer to deliver (Tfor).the Meanwhile, energy stored the inswitches the flyback Q2 and transformer Q3 are driven (Tfly) into complementarily the output. For with the sake Q1 and of analysis, Q4 to reset several Tfor as well assumptionsas to deliver are the made energy as follows: stored in the flyback transformer (Tfly) into the output. For the sake of analysis, several assumptions are made as follows: (1) all parasitic components except for those specified in Figure4 are ignored;

1) all(2) parasitica clamp components capacitor ( CexceptC) is large for th enoughose specified to be considered in Figure as 4 a are constant ignored; voltage source (VCc ); 2) a clamp(3) the capacitor output voltage (CC) is (largeVO) is enough constant; to be considered as a constant voltage source (VCc ); 3) the(4) output the transformervoltage (VO turns) is constant; ratio (n) of the forward and flyback transformers (Tfor and Tfly) is N/1, where 4) the transformerN is the number turns ratio of the (n primary) of the winding.forward and flyback transformers (Tfor and Tfly) is N/1, where N is the number of the primary winding.

iO T Q1 vds1 Tfor fly Q3 vds3 n:1 n:1

VCc iD1 iD2 VO Llkg Lm,for Lm,fly iLlkg Cc CO RO VS Tint, n:1

vD1 vD2 Q2 vds2 Q4 vds4 D1 D2

(a)

D1 Tfor Q1 Q3

Cc CO VS RO

Q2 Q4 Tfly D2 Tint, n:1 (b)

FigureFigure 4. Proposed 4. Proposed converter. converter. (a) Circuit (a) Circuitdiagram. diagram. (b) Circuit (b )diagram Circuit diagramwith a proposed with a proposed integrated transformer.integrated transformer.

Energies 2019Energies, 12, x2020 FOR, 13 PEER, 863 REVIEW 5 of 17 5 of 17

DTs

DeffTs Deff＇ Ts

Q2 Q1,Q4 Q2,Q3 Q1,Q4

VS

VS-nVO nVO vLlkg nVO vLm,fly

VCc-nVO vLm,for VCc

iLm,fly iLlkg

iLm,for

vds1 VS vds2 vds4

VCc

vds3 IO iD2

iD1 vD1

(VCc)/n VS/n vD2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t0' Figure 5. Key operational waveforms of the proposed converter. Figure 5. Key operational waveforms of the proposed converter. The proposed converter shows 10 operational modes during one switching period and each mode The isproposed explained withconverter its topological shows state 10 asoperational shown in Figure modes6. during one switching period and each Mode 1 [t –t , Figure6a]: At time t , after the commutation of the secondary diodes (D and D ) mode is explained with0 1 its topological state0 as shown in Figure 6. 1 2 ends and the leakage inductor current (iLlkg) reaches to the magnetizing current of Tfly (iLm,fly), nVO, Mode 1 [t0–t1, Figure 6a]: At time t0, after the commutation of the secondary diodes (D1 and D2) and VS–nVO are applied to the magnetizing inductance of Tfor (Lm,for) and the magnetizing inductance ends andof theTfly leakage(Lm,fly), respectively.inductor current As a result, (iLlkg)i Lm,forreaches, iLm,fly to, andthe imagnetizingLlkg are linearly current increased. of TheTfly ( poweriLm,fly), isnVO, and VS–nVO aretransferred applied to to the the output magnetizing through Q inductance1, Q4, integrated of Tfor transformer, (Lm,for) and and theD magnetizing1 at this mode. inductance From the of Tfly voltage across transformers, i , i , and current of D (i ) are expressed as follows: (Lm,fly), respectively. As a result, iLm,forLm,for, iLm,flyLm,fly, and iLlkg are linearly1 D1 increased. The power is transferred to the output through Q1, Q4, integrated transformer, andnV DO 1 at this mode. From the voltage across iLm, f or(t) = iLm, f or(t0) + (t t0), (1) transformers, iLm,for, iLm,fly, and current of D1 (iD1) are expressedLm, f or as− follows:

nVO itit()=+− ( )V ( ttS nV ),O iLm, f lyLm(t,,00) for = iLlkg( Lmt)= for iLm, f ly(t0) + − (t t0), (2) (1) Lmfor, Lm, f ly − ( ) VnV− ( ) ==iLm, f ly t +iLmSO, f or t − itititLm,,00 fly() LlkgiD ()1(t) = Lm fly ( )− . ( tt ), (3) (2) n Lmfly, itit()− () it()= Lm,, fly Lm for . (3) D1 n Mode 2 [t1–t2, Figure 6b]: After t1, Q1 and Q4 are turned off, and mode 2 begins. iLm,fly is the same as the reflected load current (IO/n) charges Coss1 and Coss4 and discharges Coss2 and Coss3. Thus, the voltages across Q1 and Q4 (vds1 and vds4) simultaneously increase to VS/2, and the voltages across Q2 and Q3 (vds2 and vds3) decrease to VS/2 and VCc–VS/2, respectively. Thus, the voltage across Lm,fly (vLm,fly) is decreased from VS–nVO to –nVO so that the sum of the voltages across Lm,fly and Lm,for is zero at the end of this mode. Mode 3 [t2–t3, Figure 6c]: vLm,fly reaches –nVO at t2, D1, and D2 start to conduct. The leakage inductance of the integrated transformer (Llkg) resonates with parasitic output capacitors (Coss1, Coss2, Coss3, and Coss4). The equivalent circuit of this mode is illustrated in Figure 7a. From this Figure, the energy stored in Llkg charges Coss1 and Coss4 and discharges Coss2 and Coss3. Thus, vds1 and vds4 are increased, and vds1 is clamped to VS. Meanwhile, vds2 and vds3 are decreased to zero and VCc–VS, respectively.

Energies 2019, 12, x FOR PEER REVIEW 6 of 17

Mode 4 [t3–t4, Figure 6d]: After vds2 reaches to zero at t3, mode 4 starts. In this mode, only Coss3 and Coss4 are continuously discharged and charged by the resonance with Llkg, respectively. vds3 decreases to zero and vds4 increases to VCc. The equivalent circuit of this mode is depicted in Figure 7b. Based on Mode 3 and Mode 4, the ZVS condition of Q2 and Q3 are: 2 V 112 ≥+S Lilkg Llkg() t2 C oss V Cc , (4) 222 where Coss = Coss1 = Coss2 = Coss3 = Coss4. Mode 5 [t4–t5, Figure 6e]: At time t4, vds2 and vds3 are 0V, and iLkkg flows through body diodes of Q2 andEnergies Q3.2020 As ,a13 result,, 863 Q2 and Q3 can achieve the ZVS operation. Moreover, since the sum of vLm.for6 ofand 17 vLm.fly is zero, –VCc is applied to Llkg. Thus, iLlkg is linearly decreased to iLm.for with the commutation between D1 and D2. iLlkg at this mode is:

iO

iO Q1 Tfor Tfly Q3 n:1 n:1 Q1 Tfor Tfly Q3 n:1 n:1 VLlkg

VLlkg VCc iD1 iD2 VO Llkg Lm,for Lm,fly iLlkg Cc CO RO VCc iD1 iD2 VO Llkg Lm,for Lm,fly VS VLm,for VLm,fly iLlkg Cc CO RO VS VLm,for VLm,fly Tint, n:1 Q2 Q4 Tint, n:1 Q2 Q4 D1 D2 D1 D2 (b) (a)

iO iO

Q1 Tfor Tfly Q3 Q1 Tfor Tfly Q3 n:1 n:1 n:1 n:1

VLlkg VLlkg

VCc iD1 iD2 VO VCc iD1 iD2 VO Llkg Lm,for Lm,fly Llkg Lm,for Lm,fly iLlkg Cc CO RO iLlkg Cc CO RO VS VLm,for VLm,fly VS VLm,for VLm,fly

Tint, n:1 Tint, n:1 Q2 Q4 Q2 Q4 D1 D2 D1 D2

(c) (d)

iO iO

Q1 Tfor Tfly Q3 Q1 Tfor Tfly Q3 n:1 n:1 n:1 n:1

VLlkg VLlkg

VCc iD1 iD2 VO VCc iD1 iD2 VO Llkg Lm,for Lm,fly Llkg Lm,for Lm,fly iLlkg Cc CO RO iLlkg Cc CO RO VS VLm,for VLm,fly VS VLm,for VLm,fly

Tint, n:1 Tint, n:1 Q2 Q4 Q2 Q4 D1 D2 D1 D2

(e) (f)

iO iO

Q1 Tfor Tfly Q3 Q1 Tfor Tfly Q3 n:1 n:1 n:1 n:1

VLlkg VLlkg

VCc iD1 iD2 VO VCc iD1 iD2 VO Llkg Lm,for Lm,fly Llkg Lm,for Lm,fly iLlkg Cc CO RO iLlkg Cc CO RO VS VLm,for VLm,fly VS VLm,for VLm,fly

Tint, n:1 Tint, n:1 Q2 Q4 Q2 Q4 D1 D2 D1 D2

(g) (h)

iO iO

Q1 Tfor Tfly Q3 Q1 Tfor Tfly Q3 n:1 n:1 n:1 n:1

VLlkg VLlkg

VCc iD1 iD2 VO VCc iD1 iD2 VO Llkg Lm,for Lm,fly Llkg Lm,for Lm,fly iLlkg Cc CO RO iLlkg Cc CO RO VS VLm,for VLm,fly VS VLm,for VLm,fly

Tint, n:1 Tint, n:1 Q2 Q4 Q2 Q4 D1 D2 D1 D2

(i) (j)

FigureFigure 6. 6. TopologicalTopological state state of of proposed proposed converter. converter. (a (a) )Mode1( Mode 1t0– (tt01).–t (1b).) (Mode2(b) Modet1– 2t2 ().t1 (–ct)2 Mode3(). (c) Modet2–t3 3). ((dt)2 –Mode4(t3). (d)t Mode3–t4). (e 4) ( tMode5(3–t4). (et4)– Modet5). (f) 5Mode6( (t4–t5).t5 (–ft)6 Mode). (g) Mode7( 6 (t5–t6t).6– (tg7).) Mode(h) Mode8( 7 (t6–tt7–).t8 ().h ()i Mode) Mode9( 8 (tt78–t89).). ((ji)) Mode10( Mode 9 (tt98––t0t’).9). (j) Mode 10 (t9–t0’).

Mode 2 [t1–t2, Figure6b]: After t1, Q1 and Q4 are turned off, and mode 2 begins. iLm,fly is the iLlkg(t3) iLlkg(t4) same as the reflected load current (IO/n) charges Coss1 and Coss4 and discharges Coss2 and Coss3. Thus, Llkg Llkg the voltages across QCeq1 and Q (v Candeq2 v ) simultaneously increaseC toeq3 V /2, and the voltages across 1 vds2(t34) ds1 vds4ds4(t3) Svds4(t4) =V /2 =V /2 =V Q2 and Q3 (vds2 and vds3) decreaseS to VS/2 andS VCc–VS/2, respectively. Thus,S the voltage across Lm,fly (vLm,fly) is decreased from VS–nVO to –nVO so that the sum of the voltages across Lm,fly and Lm,for is zero at the end of this mode. Mode 3 [t2–t3, Figure6c]: vLm,fly reaches –nVO at t2, D1, and D2 start to conduct. The leakage inductance of the integrated transformer (Llkg) resonates with parasitic output capacitors (Coss1, Coss2, Coss3, and Coss4). The equivalent circuit of this mode is illustrated in Figure7a. From this Figure, the energy stored in Llkg charges Coss1 and Coss4 and discharges Coss2 and Coss3. Thus, vds1 and vds4 are increased, and vds1 is clamped to VS. Meanwhile, vds2 and vds3 are decreased to zero and VCc–VS, respectively. Energies 2019, 12, x FOR PEER REVIEW 6 of 17

Mode 4 [t3–t4, Figure 6d]: After vds2 reaches to zero at t3, mode 4 starts. In this mode, only Coss3 and Coss4 are continuously discharged and charged by the resonance with Llkg, respectively. vds3 decreases to zero and vds4 increases to VCc. The equivalent circuit of this mode is depicted in Figure 7b. Based on Mode 3 and Mode 4, the ZVS condition of Q2 and Q3 are: 2 V 112 ≥+S Lilkg Llkg() t2 C oss V Cc , (4) 222 where Coss = Coss1 = Coss2 = Coss3 = Coss4.

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iLlkg(t3) iLlkg(t4)

Llkg Llkg Ceq1 Ceq2 Ceq3 vds2(t3) vds4(t3) vds4(t4) =VS/2 =VS/2 =VS Energies 2019, 12, x FOR PEER REVIEW 7 of 17 (a) (b)

iLlkg(t7) iLlkg(t8)

Llkg Llkg Ceq1 Ceq2 Ceq3 vds1(t7) vds4(t7) vds3(t8) =VS/2 =VS/2 =VS

(c) (d) Figure 7. a t t Figure 7. EquivalentEquivalent circuit ofof thethe proposedproposed converter converter during during switching switching transitions. transitions. ( ) ( Modea) Mode3 3 ( 2 –(t23–).t3). (b) Mode 4 (t –t ). (c) Mode 8 (t –t ). (d) Mode 9 (t –t ). (b) Mode4 (t33–t44). (c) Mode8 (t7–7t8).8 (d) Mode9 (t8–t89). 9 Mode 4 [t –t , Figure6d]: After v reaches to zero at t , mode 4 starts. In this mode, only 3 4 ds2 V 3 =−−Cc Coss3 and Coss4 are continuously dischargedititLlkg() andLlkg (44 charged ) ( ttby the ). resonance with Llkg, respectively. vds3(5) Llkg decreases to zero and vds4 increases to VCc. The equivalent circuit of this mode is depicted in Figure7b. BasedFrom on Mode (5), the 3 andcommutation Mode 4, the period ZVS condition, where the of Qinput2 and powerQ3 are: is not transferred to the output, can be approximated as LlkgIO/(nVCc).  2 Mode 6 [t5–t6, Figure 6f]: After1 the2 commutation1 of D1 VandS D2 ends, the voltage on D1 reaches LlkgiLlkg(t2) Coss VCc + , (4) VCc/n and the reset operation of T2for starts by v≥Lm,for2 (=nVO–VCc).2 Meanwhile, the energy stored in Tfly is

Lm,fly O Lm,for Lm,fly 2 D2 deliveredwhere Coss to= Ctheoss1 output= Coss2 =becauseCoss3 = vCoss4. is –nV . As a result, i , i , and current of D (i ) are expressedMode as 5 [follows:t4–t5, Figure 6e]: At time t4, vds2 and vds3 are 0 V, and iLkkg flows through body diodes VnV− of Q2 and Q3. As a result, Q2 and Q3=−can achieveCc the ZVS O operation. − Moreover, since the sum of ititLm,,5 for() Lm for ( ) ( tt 5 ), (6) vLm.for and vLm.fly is zero, –VCc is applied to Llkg. Thus,Lmfor, iLlkg is linearly decreased to iLm.for with the commutation between D1 and D2. iLlkg at this mode is: nV == −O − itititLm,,55 fly() Llkg () Lm fly ( ) ( tt ), (7) L V m, fly ( ) = ( ) Cc ( ) iLlkg t iLlkg t4 − t t4 . (5) ititLm,, fly()− LmLlkg for ()− it()= . (8) D2 n From (5), the commutation period, where the input power is not transferred to the output, can be Mode 7 [t6–t7, Figure 6g]: After t6, Q2 and Q3 are turned off, and mode 7 starts. iLm,for charges Coss2 and approximated as LlkgIO/(nVCc). Coss3 and discharges Coss1 and Coss4. Thus, vds2 and vds3 are increased to VCc/2 . vLm,for is increased from VCc–nVO Mode 6 [t5–t6, Figure6f]: After the commutation of D1 and D2 ends, the voltage on D1 reaches to nVO. On the other hand, vds1 and vds4 are decreased to VS–VCc/2 and VCc/2, respectively. This mode ends VCc/n and the reset operation of Tfor starts by vLm,for (=nVO–VCc). Meanwhile, the energy stored in Tfly when vLm,for reaches to nVO and the sum of the voltage on the magnetizing inductances is zero. is delivered to the output because vLm,fly is –nVO. As a result, iLm,for, iLm,fly, and current of D2 (iD2) are expressedMode as8 [ follows:t7–t8, Figure 6h]: vLm,for reaches nVO at t7 and D1 and D2 conduct. Thus, Llkg resonates with Coss1, Coss2, Coss3, and Coss4. The equivalent circuit of thisVCc modenV Ois illustrated as in Figure 7(. From this iLm, f or(t) = iLm, f or(t5) − (t t5), (6) Figure, the energy stored in Llkg charges Coss2 and C−oss3 andLm, fdischarges or − Coss1 and Coss4. Thus, vds2 and vds3 are increased and vds2 is clamped to VS, whereas vds1 and vds4 are decreased to zero and VCc–VS, nVO respectively. iLm, f ly(t) = iLlkg(t) = iLm, f ly(t5) (t t5), (7) − Lm, f ly − Mode 9 [t8–t9, Figure 6i]: After vds1 reaches to zero at t8, Mode 9 begins. In this mode, only Coss3 and Coss4 are continuously charged and dischargediLm, f ly(t) in iaccordanceLm, f or(t) with the resonance with Llkg. As a iD2(t) = − . (8) result, vds4 is decreased to zero and vds3 is increasedn to VCc. The equivalent circuit of this mode is depictedMode in 7Figure[t6–t7 ,7d. Figure Based6g]: on After Modet6 ,8 Qand2 and ModeQ3 are9, the turned ZVS oconditionff, and mode of Q 71 starts.and Q4i Lm,foris: charges 2 Coss2 and Coss3 and discharges Coss1 and Coss4. Thus,vds2 Vand vds3 are increased to VCc/2. vLm,for is 112 ≥+S increased from VCc–nVO to nVO.Li Onlkg Llkg the() t7 otherC hand, oss V Ccvds1 and. vds4 are decreased to VS–VCc/2 and(9) 222 VCc/2, respectively. This mode ends when vLm,for reaches to nVO and the sum of the voltage on the magnetizingMode 10 inductances [t9–t0', Figure is zero.6j]: After vds1 and vds4 become 0V, iLlkg flows through body diodes of Q1 and 4 1 4 Q . Thus,Mode Q 8 [andt7–t 8Q, Figure can achieve6h]: vLm,for the reachesZVS condition.nVO at t 7Moreoverand D1 and, similarD2 conduct. to Mode Thus, 5, sinceLlkg resonates the sum of vwithLm.for Candoss1 ,vCLm.flyoss2, isC osszero,3, and VSC oss4is applied. The equivalent to the L circuitlkg. Thus, of this iLlkg mode is linearly is illustrated increased as in to Figure iLm.flly7 .with From the commutation between D1 and D2. iLlkg at this mode is: V =+−S ititLlkg() Llkg (99 ) ( tt ). (10) Llkg

From (10), the commutation period can be derived as LlkgIO/(nVS).

3. Analysis and Design Consideration

Energies 2019, 12, x FOR PEER REVIEW 8 of 17

In this chapter, characteristics of the proposed converter are analyzed. Moreover, the design consideration of the proposed integrated transformer will be discussed to achieve high power density and simple secondary structure of the proposed converter.

3.1. DC Conversion Ratio

For simplifying analysis of the proposed converter, Llkg and the dead time among Q1–Q4 are ignored. In Figure 8, VS–nVO and –nVO are applied to the Lm,fly during DTS and (1–D)TS, respectively. Thus,Energies the2020 DC, 13conversion, 863 ratio can be approximated as in (12) by the voltage second balance of8 ofLm,fly 17 . −−−=() ()VnVDTnVDTSOSO10 S, (11)

this Figure, the energy stored in L chargesVO CDoss and Coss and discharges Coss and C . Thus, lkg = 2. 3 1 oss4 (12) vds2 and vds3 are increased and vds2 is clampedVS tonVS, whereas vds1 and vds4 are decreased to zero and V –V , respectively. CcMoreover,S based on the voltage second balance of Lm,for and Figure 8, VCc can be achieved as follows:Mode 9 [t8–t9, Figure6i]: After vds1 reaches to zero at t8, Mode 9 begins. In this mode, only Coss3 and Coss4 are continuously charged and−− discharged() − in accordance = with the resonance with Llkg. As nVOS DT() V CcO nV10 D T S , (13) a result, vds4 is decreased to zero and vds3 is increased to VCc. The equivalent circuit of this mode is nVO D Q Q depicted in Figure7d. Based on ModeVV 8== and Mode 9, the ZVS. condition of 1 and 4 is: (14) Cc11−−DD S  2 From Figure 9, the DC conversion1 ratio2 and V1Cc can be recalculatedVS by considering the duty loss1 LlkgiLlkg(t7) Coss VCc + . (9) (DL1) caused by the commutation operation2 when≥ 2 the Q1 and 2Q4 are turned on, the duty loss2 (DL2)

2 3 resultingMode from 10 the[t9 commutation–t0’, Figure6j]: operation After vds1 atand thevds4 Q become and Q 0turn-on V, iLlkg flows instant through as follows: body diodes of Q1 and Q4. Thus, Q1 and Q4 can achieve the ZVS condition. Moreover, similar to Mode 5, since the sum of vLm.for and vLm.fly is zero, VS isV applied1 to the Llkg.L Thus, iLlkg is linearly increased to iLm.flly with the O =−()DD mfor, , commutation between D1 and D2. iLlkg at this modeL1 is: + (15) VLLSmforlkgn ,

nV LL+ DD− VS D ===O i mfor,(t) = i lkg (t ) + L1 (t t ). (10) VVVCcLlkg Llkg 9 S9 S , (16) −− −−Llkg − − 11DDLmfor2, L DD L 21 D

O S L1 lkg O S S L2 where IFrom is the (10), output the commutation load current, period f canis the be derivedswitching as Lfrequency,lkgIO/(nVS). D is L I f /nV , and D is LlkgIOfS/nVCc. 3.Therefore, Analysis and the Design DC conversion Consideration ratio of the proposed converter is almost the same as that of the conventionalIn this ACF chapter, converter. characteristics of the proposed converter are analyzed. Moreover, the design consideration of the proposed integrated transformer will be discussed to achieve high power density 3.2.and Output simple Current secondary Ripple structure of the proposed converter. The conventional isolated converters, such as PSFB and ACF converters, generally adopt two 3.1. DC Conversion Ratio magnetics: (1) transformer to transfer power from the input to the output and (2) output inductor to control Forthe simplifyingoutput current analysis ripple of and the output proposed volt converter,age ripple.Llkg Meanwhile,and the dead one time integrated among Qtransformer1–Q4 are of theignored. proposed In Figure converter8, VS– cannVO playand role –nV Oasare two applied traditional to the magnetics.Lm,fly during TforDT ofS theand integrated (1–D)TS, respectively. transformer operatesThus, theas the DC conversiontransformer ratio of the can conventional be approximated isolated as in (12)converter by the and voltage Tfly secondplays role balance as the of Loutputm,fly. inductor of the conventional converters. In addition, as shown in Figure 9, the difference of iLm.for and (VS nVO)DTS nVO(1 D)TS = 0, (11) iLm.fly is reflected to the output current.− As a result,− the magnitude− of Lm,for and Lm,fly determines the output current ripple and output voltage ripple.V FromD Figure 9, the output current ripples can be O = . (12) represented as in (17) and (18). The maximumV Soutpnut current ripple can be decided on the larger value between (17) and (18):

vgs Q2,Q3 Q1,Q4 Q2,Q3 Q1,Q4

DTs (1-D)Ts

nVO VLm,for VCc-nVO

VS-nVO VLm,fly nVO

Figure 8. Applied voltage on Lm,for and Lm,fly of the proposed converter. Figure 8. Applied voltage on Lm,for and Lm,fly of the proposed converter.

Moreover, based on the voltage second balance of Lm,for and Figure8, VCc can be achieved as follows: nV DT (V nV )(1 D)T = 0, (13) O S − Cc − O − S nV D V = O = V . (14) Cc 1 D 1 D S − − Energies 2020, 13, 863 9 of 17

From Figure9, the DC conversion ratio and VCc can be recalculated by considering the duty loss1 (DL1) caused by the commutation operation when the Q1 and Q4 are turned on, the duty loss2 (DL2) resulting from the commutation operation at the Q2 and Q3 turn-on instant as follows:

VO 1 Lm, f or = (D DL1) , (15) VS n − Lm, f or + Llkg

+ nVO Lm, f or Llkg D DL1 D VCc = = − VS = VS, (16) 1 D DL L 1 D DL 1 D − − 2 m, f or − − 2 − where IO is the output load current, fS is the switching frequency, DL1 is LlkgIOfS/nVS, and DL2 is EnergiesLlkgI 2019OfS/nV, 12Cc, x .FOR PEER REVIEW 9 of 17

DTs

DL1Ts DeffTs DL2Ts Deff＇ Ts

Q1,Q4 Q2,Q3 Q1,Q4

iLm,fly iLlkg

iLm,for

ΔIO2 IO iD2 ΔIO1

iD1 t0 t1 t2 t3 t0' Figure 9. Primary and secondary current waveforms of proposed converter neglecting the dead-time. Figure 9. Primary and secondary current waveforms of proposed converter neglecting the dead-time. Therefore, the DC conversion ratio of the proposed converter is almost the same as that of the kV−− nV nV kV nV nV kn2 V T conventionalΔ= ACFSO converter. − O − = SO − O OS InDDTOLS11() , (17) LL LLV 3.2. Output Currentmfly Ripple,, mfor mfly ,, mfor S −−nV nV kV  −− nV nV kV kn2 V T Δ=TheInDDT conventionalOOCc − isolated converters,()1 −− such as = PSFB andOOCcOS − ACF converters, generally adopt two OLS22 . (18) magnetics: (1)LLm transformer,, fly m for to transfer power from the  LLinput m ,, fly to the m output for and V Cc (2) output inductor to control the output current ripple and output voltage ripple. Meanwhile, one integrated transformer of where k = Lm,for/(Lm,for + Llkg). the proposed converter can play role as two traditional magnetics. T of the integrated transformer Therefore, Lm,fly and Lm,for of the integrated transformer in the forproposed converter should be T adequatelyoperates designed as the transformer and chosen of theto satisfy conventional the requ isolatedirement converter of the output and currentfly plays and role voltage as the output ripples. inductor of the conventional converters. In addition, as shown in Figure9, the di fference of iLm.for and 3.3.i Lm.flyTransformeris reflected Design to the and output Core loss current. As a result, the magnitude of Lm,for and Lm,fly determines the output current ripple and output voltage ripple. From Figure9, the output current ripples can be representedThe proposed as in (17)converter and (18). with The the maximum integrated output tran currentsformer ripple shown can in be Figure decided 10 on can the minimize larger value the numberbetween of the (17) magnetic and (18): components through the integration of Tfor and Tfly. Moreover, the integrated transformer enables the proposed converter to simplify the secondary side without snubber circuits ! ! 2 for the secondary diodes. kVS TonV implementO nVO an integrated transformer, kVS nV variousO nV researchO kn V OandTS studies have ∆IO1 = − n(D DL1)TS = − , (17) been conducted [16,17]. L mHowever,, f ly − Lm , fthese or method− s have severalLm, f ly disadvantages− Lm, f or VS such as large conduction losses due to separate primary! and secondary windings and EMI problem! 2 caused by the nVO nVO kVCc nVO nVO kVCc kn VOTS windings wound∆IO2 = outside− the core,− whichn( 1requiresD D Ladditional2)TS = − bulky and expensive− shield .to reduce (18) L − L − − L − L VCc the adverse effect of them, f ly EMI. m, f or m, f ly m, f or whereIn thisk = paper,Lm,for/(L bym,for using+ Llkg a). characteristic that the primary currents of the forward and flyback transformersTherefore, are theLm,fly same,and anLm,for integratedof the integrated transformer transformer for Tfor and in T thefly is proposed proposed converter where two should cores be are separateadequately and share designed the andprimary chosen winding. to satisfy In the Figure requirement 10, both of thethe output primary current winding and voltage and secondary ripples. busbar3.3. Transformerare wound Design inside and the Core core. Loss As a result, the proposed integrated transformer can reduce the length of the transformer windings than those of the conventional integrated transformers in [16,17], which resultsThe proposed in lower converter conduction with loss the integratedof the transformer. transformer Moreover, shown in due Figure to the10 can windings minimize wound the insidenumber the core, of the the magnetic proposed components integrated through transfor the integrationmer can have of T forbetterand TEMIfly. Moreover, characteristics the integrated than the conventional integrated transformers [16,17]. Therefore, no additional shield is required in the proposed converter. In addition, as shown in Figure 10b, it is noted that the proposed converter can significantly simplify the secondary rectifier structure because the secondary busbar is directly connected to the output capacitor, which results in higher power density. Furthermore, there is no flux interference because two cores are separate from each other. The flux density of the proposed integrated transformer can be simply calculated by considering its operation. When Q1 and Q4 are turned on, D1 conducts and the power is transferred to the output through Tfor. At that time, Tfly stores energy since D2 is reverse biased and there is no current on Tfly and D2. Whereas, when Q2 and Q3 are turned on, D2 conducts. Thus, the energy stored in Tfly starts to be transferred to the output through Tfly and D2, while Tfor is reset by VCc. During these two periods, the flux variations of both cores (Tfor and Tfly) can be expressed as follows:

Energies 2020, 13, 863 10 of 17 transformer enables the proposed converter to simplify the secondary side without snubber circuits for the secondary diodes. To implement an integrated transformer, various research and studies have been conducted [16,17]. However, these methods have several disadvantages such as large conduction losses due to separate primary and secondary windings and EMI problem caused by the windings wound outside the core, which requires additional bulky and expensive shield to reduce the adverse effEnergiesect of the 2019 EMI., 12, x FOR PEER REVIEW 10 of 17

(a) (b)

FigureFigure 10. Integrated10. Integrated transformer transformer of the proposedof the proposed converter. converter. (a) Structure (a) of Structure the integrated of the transformer. integrated (b)transformer. Concise secondary (b) Concise side structure.secondary side structure.

In this paper, by using a characteristic() thatDD+ the primary nVT currents of the forward and flyback Δ= LOS2 transformers are the same, an integratedB transformerfor for T and, T is proposed where two cores are(19) NA for fly separate and share the primary winding. In Figure 10Pefor, both, the primary winding and secondary busbar ()1−+DD nVT are wound inside the core. As a result,Δ= the proposedLOS1 integrated transformer can reduce the length B fly , (20) of the transformer windings than those of the conventionalNAP e, fly integrated transformers in [16,17], which resultswhere in N lowerP is the conduction number of loss primary of the windings transformer. of the Moreover, integrated due transformer to the windings and A wounde,for and inside Ae,fly are the the core,effective the proposed cross-section integrated area of transformer each core. can have better EMI characteristics than the conventional integratedTo transformersanalyze the core [16,17 loss]. Therefore, of the proposed no additional integrated shield transformer, is required in the the improved proposed converter.generalized InSteinmetz addition, asequation shown (IGSE) in Figure can 10 beb, adopted it is noted because that the the proposed flux variations converter of both can cores significantly are not sinusoidal. simplify theThe secondary transformer rectifier core structureloss based because on the IGSE the secondary can be expressed busbar as is directlyfollows: connected to the output capacitor, which results in higher power density. Furthermore,α there is no flux interference because 1 T dB βα− PkBdt=Δ() , (21) two cores are separate from each other.coreTdt0 i The flux density of the proposed integrated transformer can be simply calculated by considering where ΔB is the peak-to-peak flux variation, and its operation. When Q1 and Q4 are turned on, D1 conducts and the power is transferred to the output = k through Tfor. At that time, Tfly storesk energy sinceπ D2 is reverse biased, and there is no current on Tfly i αβα−−2 α (22) (2πθθ )1 cos 2 d and D2. Whereas, when Q2 and Q3 are turned on,0 D2 conducts. Thus, the energy stored in Tfly starts to bewhere transferred parameters to the outputk, α, and through β are theTfly sameand Dparameters2, while T foras isused reset in by theV CcSteinmetz. During equation these two [20]. periods, the fluxAssuming variations that of both the corestransformer (Tfor and turnsTfly) canthe beratio expressed of the asproposed follows: and conventional integrated transformers the same way, the core loss of the proposed integrated transformer is the same as that (D + DL2)nVOTS of the conventional integrated transformer∆B = for the ACF ,converters. Meanwhile, the proposed (19) f or N A integrated transformer can have slightly larger coPre eloss, f or than the conventional PSFB converter with a transformer and output inductor. This is because the turns-ratio of the proposed integrated (1 D + DL1)nVOTS transformer is restricted due to the∆B sharedf ly = primary− windings. Thus,, the number of primary windings (20) NPAe, f ly of the proposed integrated transformer can be lower than that of the transformer and output inductor wherein theNP conventionalis the number PSFB of primary converter, windings which of thecan integratedincrease the transformer core loss andof theAe,for proposedand Ae,fly converterare the effcomparedective cross-section to the conventional area of each PSFB core. converter. Since ΔIO is determined by the Lm,for and Lm,fly, relatively small Lm,for and Lm,fly should be designed to satisfy the requirement of ΔIO. Due to the relatively larger core loss and magnetizing current, the proposed converter may have lower light load efficiency than the conventional PSFB converter. On the other hand, the proposed integrated transformer results in high heavy load efficiency because single primary windings and optimized busbar structure decrease the conduction loss caused by the output current. As mentioned in introduction section, the importance of heavy load efficiency in eco-friendly vehicles has been increasing more than before as the electric load of the vehicle has considerably increased. Therefore, the proposed integrated transformer is appropriate for the LDC converter of eco-friendly vehicles. Furthermore, the proposed integrated transformer not only reduces the volume of the converter but also achieves a high price competitiveness due to the concise secondary rectifier structure as shown in Figure 10b.

3.4. Conduction Loss and Voltage Stresses on Switches and Diodes

Energies 2020, 13, 863 11 of 17

To analyze the core loss of the proposed integrated transformer, the improved generalized Steinmetz equation (IGSE) can be adopted because the flux variations of both cores are not sinusoidal. The transformer core loss based on the IGSE can be expressed as follows:

Z T α 1 dB β α Pcore = ki (∆B) − dt, (21) T 0 dt where ∆B is the peak-to-peak flux variation, and

k ki = , (22) α 1R 2π α (2π) − cos θ 2β αdθ 0 | | − where parameters k, α, and β are the same parameters as used in the Steinmetz equation [20]. Assuming that the transformer turns the ratio of the proposed and conventional integrated transformers the same way, the core loss of the proposed integrated transformer is the same as that of the conventional integrated transformer for the ACF converters. Meanwhile, the proposed integrated transformer can have slightly larger core loss than the conventional PSFB converter with a transformer and output inductor. This is because the turns-ratio of the proposed integrated transformer is restricted due to the shared primary windings. Thus, the number of primary windings of the proposed integrated transformer can be lower than that of the transformer and output inductor in the conventional PSFB converter, which can increase the core loss of the proposed converter compared to the conventional PSFB converter. Since ∆IO is determined by the Lm,for and Lm,fly, relatively small Lm,for and Lm,fly should be designed to satisfy the requirement of ∆IO. Due to the relatively larger core loss and magnetizing current, the proposed converter may have lower light load efficiency than the conventional PSFB converter. On the other hand, the proposed integrated transformer results in high heavy load efficiency because single primary windings and optimized busbar structure decrease the conduction loss caused by the output current. As mentioned in introduction section, the importance of heavy load efficiency in eco-friendly vehicles has been increasing more than before as the electric load of the vehicle has considerably increased. Therefore, the proposed integrated transformer is appropriate for the LDC converter of eco-friendly vehicles. Furthermore, the proposed integrated transformer not only reduces the volume of the converter but also achieves a high price competitiveness due to the concise secondary rectifier structure as shown in Figure 10b.

3.4. Conduction Loss and Voltage Stresses on Switches and Diodes

For the sake of analysis, it is assumed that (1) Lm,for and Lm,fly are large enough to ignore the effect of the magnetizing current during a switching period and (2) Llkg is small enough to neglect the effect of the commutation period. Based on this assumption, RMS currents and voltage stress on the primary switches and secondary diodes can be derived for the conventional PSFB converter, conventional ACF converter, and proposed converter (Table1). From Table1, it can be seen that the proposed converter has negligible RMS currents on Q2 and Q3, inducing the ignorable conduction loss. Thus, the conduction loss on primary switches is much smaller than that of the conventional PSFB converter and this tendency becomes larger as the output current goes to heavier load condition. Due to the full-bridge active clamp structure, the proposed converter can achieve lower maximum voltage stresses on primary switches (Q1 and Q2: 310 V, Q3 and Q4: 238.6 V under experimental conditions) compared to the conventional ACF converter (Qmain and Qaux: 477.7 V). Thus, considering a 30% voltage margin, the proposed converter can adopt Si-MOSFETs with low cost and low on-resistance rather than SiC-MOSFETs having high cost and high voltage rating characteristics (Table2). Moreover, the proposed converter reduces the maximum voltage stresses on D1 and D2 (D1: 29.8 V, D2: 38.8 V without considering voltage ringing under experimental conditions) than the conventional PSFB converter (D1 and D2: 62 V). Therefore, the proposed converter can utilize low voltage and high current rating diodes without bulky and lossy snubber circuit. Energies 2020, 13, 863 12 of 17

Table 1. Components stresses comparison among the conventional and proposed converters. Energies 2019, 12, x FOR PEER REVIEW 12 of 17 Stress Type PSFB ACF Proposed Converter

IO IO The DSP isRMS used currents to implement the outputIO voltage control and the√ switching frequency variation.√ The Q –Q : Qmain: n D Q1,Q4: n D 1 4 √ duty to outputon switches voltage transfer functionn 2 of the proposedQaux :–converter can be derivedQ2,Q3:– like a buck converter Voltageas follows: stress Q : 1 V Q ,Q : V Q –Q :V main 1 D S 1 2 S on switches 1 4V S 1 1− Q ,Q : D V = O Qaux: 1 D VS 3 4 1 D S Gsvd () − , − D LC L D D m,, fly O2 ++D1 m: fly VS D1: VS (23) Voltage stresses 2VS s n(1 D1) n(1 D) D1, D2: 22γγ− − on diodes n nnRO VS VS D2: n D2: n where γ is 1 + Lm,fly/Lm,for. Table 2. Price comparison of the primary switches among the conventional and proposed converters. Table 3. Design Parameters. Price List PSFB ACF Proposed Converter Components Conventional PSFB Proposed Converter Qmain: Primary switch Q1, Q4 : IPW60R080 Q –Q : C3M0065090/9.375 Q ,Q : IPW60R080/3.59 Part number 1 4 1 4 IPW60R105IPW60R105,/3.37 4EA Q : (600 V, 80Q m,QΩ) : IPW60R190/1.74 /PricePrimary ($) Switch aux 2 3 (600 V, 105 mΩ) C3M0120090Q/6.0252, Q3 : IPW60R190 Total price of (600 V, 190 mΩ) 13.48 15.4 10.66 primary switches ($) STPS40170, 6 EA M80QZ12N, 2 EA Secondary diode (170 V, 40 A, VF = 0.79 V) (120 V, 160 A, VF = 0.78 V) 4. ExperimentalClamp Results capacitor – PCPW225 MKP (630V, 1 uF) Core: PQ4730 Core: PQ6640 custom To prove the validity of the proposed converter, a 1.8 kW prototype shown in Figure 11a was Transformer Lm = 140 uH, Llkg = 1.7 uH Lm,for = 50 uH, Lm,fly = 40 uH built with the specification of VS = 200–310 V, VO = 13.6 V, fS = 125 kHz at 200 V input – 150 kHz at Np : Ns = 10:1 Llkg = 5 uH, Np: Ns = 8: 1 310 V input. We also implemented a conventional PSFB converter. Table3 summarizes the details of Core: EER6028 two prototypes.Output In this inductor chapter, the commercialized PSFB converter was– designed for IONIQ HEV LO = 1.7 uH, 5 turns (made by HYUHNDAI motor company) and is used as the conventional converter to compare the Output capacitor MLCC: 17 uF x 4 EA MLCC: 22 uF x 6 EA performance of the proposed converter.

T Tfor fly n:1 n:1 Q1 Q3

Llkg Lm,for Lm,fly iLlkg Cc Co Ro VS Tint, n:1

D1 D2 Q2 Q4

Driver

PWM Digital ADC Function Ramp Comp Gate Mode Change Frequency Modulation Gvc(z) Iref[n] Burst Mode vref[n] TMS320F28069 MCU

(a) (b)

Figure 11. Prototype and control block diagram of proposedproposed converter.converter. (a) Prototype.Prototype. ( b) Control block diagram.

The loop gain (Tv(z)) of the proposed converter adopting the voltage compensator is illustrated in Figure 12. The voltage compensator (Gvc(z)) was designed for minimum 360 Hz bandwidth and 45° phase margin for the prototype of this paper.

Energies 2020, 13, 863 13 of 17

Table 3. Design Parameters.

Components Conventional PSFB Proposed Converter

Q1,Q4: IPW60R080 IPW60R105, 4 EA (600 V, 80 mΩ) Primary Switch (600 V, 105 mΩ) Q2,Q3 : IPW60R190 (600 V, 190 mΩ) STPS40170, 6 EA M80QZ12N, 2 EA Secondary diode (170 V, 40 A, VF = 0.79 V) (120 V, 160 A, VF = 0.78 V) Clamp capacitor – PCPW225 MKP (630 V, 1 uF) Core: PQ4730 Core: PQ6640 custom Transformer Lm = 140 uH, Llkg = 1.7 uH Lm,for = 50 uH, Lm,fly = 40 uH Np: Ns = 10:1 Llkg = 5 uH, Np: Ns = 8: 1

Output inductor Core: EER6028LO = 1.7 uH, 5 turns – Output capacitor MLCC: 17 uF 4 EA MLCC: 22 uF 6 EA × ×

To regulate the output voltage, as shown in Figure 11b, the proposed converter used a DSP that is TMS320F28069PZT with 90 MHz clock frequency and 12-bit analog to digital conversion module. The DSP is used to implement the output voltage control and the switching frequency variation. The duty to output voltage transfer function of the proposed converter can be derived like a buck converter as follows: V 1 G (s) = O , (23) vd L C L D m, f ly O 2 m, f ly 2 s + 2 + 1 n γ n γRO

where γ is 1 + Lm,fly/Lm,for. The loop gain (Tv(z)) of the proposed converter adopting the voltage compensator is illustrated in Figure 12. The voltage compensator (Gvc(z)) was designed for minimum 360 Hz bandwidth and 45◦ Energiesphase 2019 margin, 12, x FOR for PEER the prototype REVIEW of this paper. 13 of 17

FigureFigure 12. 12. LoopLoop gain gain of of the the proposed proposed conv convertererter withwithvoltage voltage compensator. compensator. In addition, since the DSP is placed in the secondary side, the pulse transformer which can transfer In addition, since the DSP is placed in the secondary side, the pulse transformer which can transfer gate signals from the secondary side to the primary side is implemented. In addition, for measuring gatethe signals performance from the of secondary the conventional side to andthe primary proposed side converters, is implemented. NFES2000S In isaddition, used as anfor input measuring power the performancesupply, Chroma of the DC conventional Electronic load and 63203 proposed as an outputconverters, electronic NFES2000S load, YOKOGAWA is used as WT1600an input as power an supply,input Chroma power analyzer, DC Electronic FLUKE load 45A digital63203 as multi-meter an output for electronic the output load, voltage YOKOGAWA and current WT1600 measuring, as an inputand power Wave-runner analyzer, 64xi FLUKE TELEDYNE 45A digital LECROY multi-mete to capturer for the the experimental output voltage waveforms. and current measuring, and Wave-runner 64xi TELEDYNE LECROY to capture the experimental waveforms. Figure 13 shows the experimental waveforms of the proposed converter at the nominal input voltage (VS = 270 V) and full-load condition with the 150 kHz switching frequency. As shown in Figure 13a, due to the ACF structure, there is no circulating current and only small commutation current occurs during the switch transition. Moreover, voltage stresses on the primary switches of the proposed converter is far lower than 650 V which is general breakdown voltage of high-performance Si-MOSFETs. As a result, the primary conduction loss of the proposed converter can be considerably reduced compared to the conventional PSFB converter. Moreover, the propose converter cuts the production cost by utilizing Si-MOSFETs and the integrated transformer with single and inside wounded primary and secondary windings. Figures 14 and 15 present the key experimental waveforms at the minimum and maximum input voltage conditions under the full load condition. As shown in Figure 14, in the minimum input voltage condition (VS = 200 V), since the maximum switch voltage stresses are determined by the actual duty ratio that is sum of the effective duty ratio and the duty loss during the commutation period, the switching frequency varies from 150 kHz to 125 kHz at the minimum input voltage condition to reduce the ratio of the commutation period in the total switching period. As a result, the voltage stresses on the primary switches are well restricted near 400 V, and the secondary diode voltage stresses are under 100 V. Since the duty ratio (D) of the proposed converter can be designed to be over 0.5, the proposed converter well regulates the output voltage at the minimum input voltage condition with D = 0.605. Moreover, as can be seen in Figure 15, the voltage stresses on the switches and diodes are under 400 V and 100 V in the maximum input voltage condition (VS = 310 V). Although the voltage stresses on the switches and diodes varies according to the input voltage conditions, all of them are well controlled and restricted to be suitable for high performance Si-MOSFET with low cost and low on-resistance. Furthermore, the ZVS operation of the proposed converter is achieved even in the worst-case condition such as the high input voltage and full-load conditions shown in Figure 16a. Figure 16b shows the output voltage ripple of the proposed converter. The maximum output voltage ripple is under 500 mV regardless of the input voltage and load conditions (500 mV is the output voltage ripple requirement of LDC converter for vehicle applications). This verifies that the magnetizing inductances of the proposed integrated transformer is adequately designed and chosen. Thus, despite the integrated transformer, the proposed converter can effectively constrain the output current ripple.

Energies 2019, 12, x FOR PEER REVIEW 14 of 17 Energies 2020, 13, 863 14 of 17 Figure 17 shows the measured efficiency of the proposed and conventional PSFB converters. In the minimum input voltage condition, the efficiency of the proposed converter is almost the same as thatFigure of PSFB 13 converter shows the because experimental the PSFB waveforms converter op oferates the proposed with a duty converter ratio near at 0.5. the Meanwhile, nominal input in voltagethe nominal (VS = and270 maximum V) and full-load input voltage condition conditions, with the as previously 150 kHz switching analyzed, frequency.the proposed As converter shown in Figureshows 13 highera, due toefficiency the ACF over structure, the 30% there load is conditio no circulatingns due currentto the reduced and only circulating small commutation and conduction current occursloss of during the Q the2 and switch Q3 switches. transition. On Moreover,the other hand, voltage because stresses of onlarge the core primary loss and switches small of magnetizing the proposed converterinductances is far of lower the integrated than 650 V transformer, which is general the effici breakdownency of the voltage proposed of high-performance converter is similar Si-MOSFETs. to that Asof a the result, conventional the primary PSFB conductionconverter under loss light of the load proposed condition. converter However, can since be the considerably importance reduced of the comparedhigh heavy to theload conventional efficiency is PSFBgradually converter. increased, Moreover, the proposed the propose converter converter is attractive cuts the for production the LDC costconverter by utilizing of the Si-MOSFETs vehicle applications. and the integratedMoreover, transformerthe proposed with converter single is and a very inside promising wounded converter primary andfor secondary other wide windings. input and high output power applications due to its high efficiency and high power density characteristics.

(a) (b)

FigureFigure 13. 13. KeyKey experimental waveforms waveforms at at 270 270 V Vinput input and and 100% 100% load load conditions conditions (D = (0.605).D = 0.605). (a) (a)Primary Primary side side key key experimental experimental waveforms. waveforms. (b) (Secondaryb) Secondary side side key keyexperimental experimental waveforms. waveforms.

Figures 14 and 15 present the key experimental waveforms at the minimum and maximum input voltage conditions under the full load condition. As shown in Figure 14, in the minimum input voltage condition (VS = 200 V), since the maximum switch voltage stresses are determined by the actual duty ratio that is sum of the effective duty ratio and the duty loss during the commutation period, the switching frequency varies from 150 kHz to 125 kHz at the minimum input voltage condition to reduce the ratio of the commutation period in the total switching period. As a result, the voltage stresses on the primary switches are well restricted near 400 V, and the secondary diode voltage stresses are under 100 V. Since the duty ratio (D) of the proposed converter can be designed to be over 0.5, the proposed converter well regulates the output voltage at the minimum input voltage condition with D = 0.605.

Moreover, as can be seen( ina) Figure 15, the voltage stresses on the switches( andb) diodes are under 400 V and 100 V in the maximum input voltage condition (VS = 310 V). Although the voltage stresses on the switchesFigure and 14. diodes Key experimental varies according waveforms to the at input 200 V voltageinput and conditions, 100% load allconditions of them (D are = 0.464). well controlled (a) Primary side key experimental waveforms. (b) Secondary side key experimental waveforms. and restricted to be suitable for high performance Si-MOSFET with low cost and low on-resistance. Furthermore, the ZVS operation of the proposed converter is achieved even in the worst-case condition such as the high input voltage and full-load conditions shown in Figure 16a. Figure 16b shows the output voltage ripple of the proposed converter. The maximum output voltage ripple is under 500 mV regardless of the input voltage and load conditions (500 mV is the output voltage ripple requirement of LDC converter for vehicle applications). This verifies that the magnetizing inductances of the proposed integrated transformer is adequately designed and chosen. Thus, despite the integrated transformer, the proposed converter can effectively constrain the output current ripple.

(a) (b)

Figure 15. Key experimental waveforms at 310 V input and 100% load conditions (D = 0.412). (a) Primary side key experimental waveforms. (b) Secondary side key experimental waveforms.

Energies 2019, 12, x FOR PEER REVIEW 14 of 17 Energies 2019, 12, x FOR PEER REVIEW 14 of 17 Figure 17 shows the measured efficiency of the proposed and conventional PSFB converters. In Figure 17 shows the measured efficiency of the proposed and conventional PSFB converters. In the minimum input voltage condition, the efficiency of the proposed converter is almost the same as the minimum input voltage condition, the efficiency of the proposed converter is almost the same as that of PSFB converter because the PSFB converter operates with a duty ratio near 0.5. Meanwhile, in that of PSFB converter because the PSFB converter operates with a duty ratio near 0.5. Meanwhile, in the nominal and maximum input voltage conditions, as previously analyzed, the proposed converter the nominal and maximum input voltage conditions, as previously analyzed, the proposed converter shows higher efficiency over the 30% load conditions due to the reduced circulating and conduction shows higher efficiency over the 30% load conditions due to the reduced circulating and conduction loss of the Q2 and Q3 switches. On the other hand, because of large core loss and small magnetizing loss of the Q2 and Q3 switches. On the other hand, because of large core loss and small magnetizing inductances of the integrated transformer, the efficiency of the proposed converter is similar to that inductances of the integrated transformer, the efficiency of the proposed converter is similar to that of the conventional PSFB converter under light load condition. However, since the importance of the of the conventional PSFB converter under light load condition. However, since the importance of the high heavy load efficiency is gradually increased, the proposed converter is attractive for the LDC high heavy load efficiency is gradually increased, the proposed converter is attractive for the LDC converter of the vehicle applications. Moreover, the proposed converter is a very promising converter converter of the vehicle applications. Moreover, the proposed converter is a very promising converter for other wide input and high output power applications due to its high efficiency and high power for other wide input and high output power applications due to its high efficiency and high power density characteristics. density characteristics.

(a) (b) (a) (b) Figure 13. Key experimental waveforms at 270 V input and 100% load conditions (D = 0.605). (a) Figure 13. Key experimental waveforms at 270 V input and 100% load conditions (D = 0.605). (a) EnergiesPrimary2020, 13 side, 863 key experimental waveforms. (b) Secondary side key experimental waveforms. 15 of 17 Primary side key experimental waveforms. (b) Secondary side key experimental waveforms.

(a) (b) (a) (b) Figure 14. Key experimental waveforms at 200 V input and 100% load conditions (D = 0.464). (a) FigureFigure 14. 14. KeyKey experimental experimental waveforms waveforms at at200 200 V input V input and and 100% 100% load load conditions conditions (D = ( D0.464).= 0.464). (a) Primary side key experimental waveforms. (b) Secondary side key experimental waveforms. Primary(a) Primary side side key keyexperimental experimental waveforms. waveforms. (b) Secondary (b) Secondary side side key keyexperimental experimental waveforms. waveforms.

(a) (b) (a) (b) Figure 15. 15. KeyKey experimental experimental waveforms waveforms at at310 310 V Vinput input and and 100% 100% load load conditions conditions (D = (D 0.412).= 0.412). (a) Figure 15. Key experimental waveforms at 310 V input and 100% load conditions (D = 0.412). (a) EnergiesPrimary(a 2019) Primary, 12 side, x FOR side key PEER key experimental experimental REVIEW waveforms. waveforms. (b) (Secondaryb) Secondary side side key key experimental experimental waveforms. waveforms. 15 of 17 Primary side key experimental waveforms. (b) Secondary side key experimental waveforms.

(a) (b)

FigureFigure 16. 16. ZVSZVS and and output output voltage voltage ripple ripple waveforms waveforms at at worst worst case case conditions. conditions. ( (aa)) ZVS ZVS waveforms waveforms at at 310310 V V input input and and 100% 100% load load conditions. conditions. ( (bb)) Output Output voltage voltage ripple ripple waveforms waveforms at at 200 200 V V input input and and 100% 100% loadload conditions. conditions.

93.0Figure 17 shows the measured efficiency of the proposed and conventional PSFB converters. In 93.0 92.5 the minimum input voltage condition, the efficiency of92.5 the proposed converter is almost the same as 92.0 92.0 that91.5 of PSFB converter because the PSFB converter operates with a duty ratio near 0.5. Meanwhile, in 91.5 91.0 the nominal and maximum input voltage conditions, as91.0 previously analyzed, the proposed converter 90.5 90.5 90.0 shows higher efficiency over the 30% load conditions90.0 due to the reduced circulating and conduction Efficiency [%]

89.5 Efficiency [%] loss of the Q and Q switches. OnProposed the 200V other hand, because89.5 of large core loss and small magnetizing 89.0 2 3 Proposed 270V PSFB 200V 89.0 88.5 PSFB 270V inductances of the integrated transformer, the efficiency88.5 of the proposed converter is similar to that of 88.0 88.0 the conventional10 20 30 40PSFB 50 converter 60 70 80 90 under 100 110 light 120 130load condition. However, since the importance of the 10 20 30 40 50 60 70 80 90 100 110 120 130 Load [A] high heavy load efficiency is gradually increased, the proposed converter isLoad attractive [A] for the LDC

(a) (b)

93.0 92.5 92.0 91.5 91.0 90.5 90.0 Efficiency [%] 89.5 Proposed 310V 89.0 PSFB 310V 88.5 88.0 10 20 30 40 50 60 70 80 90 100 110 120 130 Load [A]

(c)

Figure 17. Measured efficiency according to input voltage. (a) Minimum input (VS = 200 V, D = 0.605). (b) Nominal input (VS = 270 V, D = 0.464). (c) Maximum input (VS = 310 V, D = 0.412 ).

5. Conclusion In this paper, a novel FBACFF converter with an integrated transformer sharing primary windings is proposed to achieve high efficiency and high power density LDC converter for vehicle applications. The operation principles and features are analyzed and illustrated, and the effectiveness of the proposed converter is verified by the experimental results with 13.6 V and 1.8 kW prototype. In the proposed converter, due to the full-bridge active-clamp structure, the proposed converter can reduce the primary conduction loss by eliminating the circulating current and utilize low cost Si- MOSFETs by relieving burden of the primary voltage stress. In addition, the proposed converter can improve power density through the integrated transformer with the shared and wounded inside windings. Furthermore, the secondary side structure can be simplified and optimized. Based on these advantages, the proposed converter can achieve not only high efficiency and high power density but also low cost. Therefore, the proposed converter is expected to be widely adopted for applications

Energies 2019, 12, x FOR PEER REVIEW 15 of 17

Energies 2020, 13, 863 16 of 17 (a) (b) converterFigure of 16. the ZVS vehicle and output applications. voltage ripple Moreover, waveforms the proposed at worst case converter conditions. is a very(a) ZVS promising waveforms converter at for other310 V wideinput inputand 100% and load high conditions. output power (b) Output applications voltage ripple due waveforms to its high at e ffi200ciency V input and and high 100% power densityload characteristics. conditions.

93.0 93.0 92.5 92.5 92.0 92.0 91.5 91.5 91.0 91.0 90.5 90.5 90.0 90.0 Efficiency [%]

89.5 Efficiency [%] Proposed 200V 89.5 89.0 Proposed 270V PSFB 200V 89.0 88.5 PSFB 270V 88.5 88.0 88.0 10 20 30 40 50 60 70 80 90 100 110 120 130 10 20 30 40 50 60 70 80 90 100 110 120 130 Load [A] Load [A]

(a) (b)

93.0 92.5 92.0 91.5 91.0 90.5 90.0 Efficiency [%] 89.5 Proposed 310V 89.0 PSFB 310V 88.5 88.0 10 20 30 40 50 60 70 80 90 100 110 120 130 Load [A]

(c)

FigureFigure 17.17.Measured Measured e ffiefficiencyciency according according to to input input voltage. voltage. (a) ( Minimuma) Minimum input input (VS =(V200S = 200 V, D V,= 0.605).D = (b0.605).) Nominal (b) Nominal input (V inputS = 270 (V V,S =D 270= 0.464).V, D = 0.464). (c) Maximum (c) Maximum input ( VinputS = 310 (VS V,= 310D = V,0.412). D = 0.412 ).

5. Conclusions 5. ConclusionIn this paper, a novel FBACFF converter with an integrated transformer sharing primary windings is proposedIn this topaper, achieve a novel high effiFBACFFciency andconverter high power with densityan integrated LDC converter transformer for vehicle sharing applications. primary windingsThe operation is proposed principles to andachieve features high are efficiency analyzed and and high illustrated, power anddensity the e ffLDCectiveness converter of the for proposed vehicle applications.converter is verifiedThe operation by the principles experimental and resultsfeatures with are analyzed 13.6 V and and 1.8 illustrated, kW prototype. and the In theeffectiveness proposed ofconverter, the proposed due to converter the full-bridge is verified active-clamp by the experime structure,ntal the results proposed with converter 13.6 V and can reduce1.8 kW theprototype. primary Inconduction the proposed loss converter, by eliminating due to the the circulating full-bridge current active-clamp and utilize structure, low cost the Si-MOSFETs proposed converter by relieving can reduceburden the of theprimary primary conduction voltage stress. loss by In addition,eliminating the the proposed circulating converter current can and improve utilize power low cost density Si- MOSFETsthrough the by integrated relieving burden transformer of the with primary the shared voltag ande stress. wounded In addition, inside the windings. proposed Furthermore, converter can the improvesecondary power side structuredensity through can be simplified the integrated and optimized. transformer Based with on the these shared advantages, and wounded the proposed inside windings.converter canFurthermore, achieve not the only secondary high effi sideciency structure and high can power be simplified density butand also optimized. low cost. Based Therefore, on these the advantages,proposed converter the proposed is expected converter to be can widely achieve adopted not only for high applications efficiency with and wide high input power voltage density range but alsoand low high cost. output Therefore, current suchthe proposed as the LDC converter converter is forexpected vehicle to applications. be widely adopted The efficiency for applications and power density of the proposed converter can be much improved with planar transformer and synchronous rectification techniques.

Author Contributions: J.B. and H.-S.Y. were the main researchers who initiated and organized research reported in the paper. All authors including H.-S.Y. were responsible for making the prototype of the proposed system and carrying out the experiment. All authors have read and agreed to the published version of the manuscript. Funding: This work was supported by Incheon National University (International Cooperative) Research Grant in 2019. Conflicts of Interest: The authors declare not conflict of interest. Energies 2020, 13, 863 17 of 17

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