5V/2A, Synchronous No-Opto Isolated Flyback DC-DC Converter Using MAX17690 and MAX17606 MAXREFDES1022
Introduction Hardware Specification Due to its simplicity and low cost, the flyback converter is An isolated no-opto flyback DC-DC converter using the the preferred choice for low-to-medium isolated DC-DC MAX17690 and MAX17606 is demonstrated for a 5V DC power-conversion applications. However, the use of output application. The power supply delivers up to 2A at an optocoupler or an auxiliary winding on the flyback 5V. Table 1 shows an overview of the design specification. transformer for voltage feedback across the isolation barrier increases the number of components and design Table 1. Design Specification complexity. The MAX17690 eliminates the need for an optocoupler or auxiliary transformer winding and achieves PARAMETER SYMBOL MIN MAX
±5% output voltage regulation over line, load, and tem- Input Voltage VIN 10V 50V perature variations. Frequency fSW 128kHz
The MAX17690 implements an innovative algorithm to Efficiency at Full Load ηMAX 85% accurately determine the output voltage by sensing the Efficiency at Minimum η 55% reflected voltage across the primary winding during the Load MIN flyback time interval. By sampling and regulating this Output Voltage V 4.9V 5.1V reflected voltage when the secondary current is close to O zero, the effects of secondary-side DC losses in the trans- Output Voltage Ripple ∆VO(SS) 100mV former winding, the PCB tracks, and the rectifying diode Output Current IO 0.2A 2.0A on output voltage regulation can be minimized. Maximum Output Power PO 10W The MAX17690 also compensates for the negative tem- perature coefficient of the rectifying diode. Designed–Built–Tested Other features include the following: This document describes the hardware shown in Figure 1. ●● 4.5V to 60V Input Voltage Range It provides a detailed systematic technical guide to design- ●● Programmable Switching Frequency from 50kHz to ing an isolated no-opto flyback DC-DC converter using 250kHz Maxim’s MAX17690 controller. The power supply has been built and tested. ●● Programmable Input Enable/UVLO Feature ●● Programmable Input Overvoltage Protection ●● Adjustable Soft-Start ●● 2A/4A Peak Source/Sink Gate Drive Capability ●● Hiccup Mode Short-Circuit Protection ●● Fast Cycle-by-Cycle Peak Current Limit ●● Thermal Shutdown Protection ●● Space-Saving, 16-Pin, 3mm x 3mm TQFN Package ●● -40°C to +125°C Operating Temperature Range
Figure 1. MAXREFDES1022 hardware.
Rev 0; 10/17 Maxim Integrated │ 1 The Isolated No-Opto Flyback Converter the isolated output voltage by examining the voltage on One of the drawbacks encountered in most isolated the primary-side winding of the flyback transformer. DC-DC converter topologies is that information relating to Other than this uniquely innovative method for regulating the output voltage on the isolated secondary side of the the output voltage, the no-opto isolated flyback converter transformer must be communicated back to the primary using the MAX17690 follows the same general design side to maintain output voltage regulation. In a regular process as a traditional flyback converter. To under- isolated flyback converter, this is normally achieved using stand the operation and benefits of the no-opto flyback an optocoupler feedback circuit or an additional auxiliary converter it is useful to review the schematic and typical winding on the flyback transformer. Optocoupler feedback waveforms of the traditional flyback converter (using the circuits reduce overall power-supply efficiency, and the MAX17595), shown in Figure 2. extra components increase the cost and physical size The simplified schematic in Figure 2 illustrates how infor- of the power supply. In addition, optocoupler feedback mation about the output voltage is obtained across the circuits are difficult to design reliably due to their limited isolation barrier in traditional isolated flyback converters. bandwidth, nonlinearity, high CTR variation, and aging The optocoupler feedback mechanism requires at least effects. Feedback circuits employing auxiliary transformer 10 components including an optocoupler and a shunt reg- windings also exhibit deficiencies. Using an extra wind- ulator, in addition to a primary-side bias voltage, VBIAS, to ing adds to the flyback transformer’s complexity, phys- drive the photo-transistor. The error voltage FB2 connects ical size, and cost, while load regulation and dynamic to the FB pin of the flyback controller. response are often poor. The transformer feedback method requires an additional The MAX17690 is a peak current-mode controller winding on the primary side of the flyback transformer, designed specifically to eliminate the need for optocou- a diode, a capacitor, and two resistors to generate a pler or auxiliary transformer winding feedback in the tra- voltage proportional to the output voltage. This voltage is ditional isolated flyback topology, therefore reducing size, compared to an internal reference in a traditional flyback cost, and design complexity. It derives information about controller to generate the error voltage.
IIN ILP ILS DFR ILO
ICIN TRANSFORMER FEEDBACK ICO VO DAUX RZ CIN VAUX LP LS CO NDRV VIN RL RU
GNDP FB1 CAUX DZ GNDS RL VIN(MAX) x dMAX GNDP GNDS GNDS ΔILP(MAX) = LP x fSW GNDP 1: nSP OPTO-COUPLER FEEDBACK ΔILP GNDS VBIAS VO LLK
VFLYBACK FB 2 x IO(MAX) MAX17595 QP ΔILS(MAX) = (1 – d ) NDRV MAX FB2 ΔILS
CS GNDP
RCS GNDP GNDP
VO + VDFR + (ΔILS x RS) GNDP VIN + VFLYBACK nSP VIN GNDS
t1 t3 t0 t2 t4 t5 t6
Figure 2. Isolated flyback converter topology with typical waveforms.
www.maximintegrated.com Maxim Integrated │ 2 By including additional innovative features internally in the where: MAX17690 no-opto flyback controller, Maxim has enabled VFLYBACK is the QP drain voltage relative to primary ground power-supply designers to eliminate the additional com- ponents, board area, complexity, and cost associated with VDFR(T) is the forward voltage drop of DFR, which has a both the optocoupler and transformer feedback methods. negative temperature coefficient Figure 3 illustrates a simplified schematic and typical ILS(t) is the instantaneous secondary transformer current waveforms for an isolated no-opto flyback DC-DC con- RS(T) is the total DC resistance of the secondary circuit, verter using the MAX17690. which has a positive temperature coefficient By comparing Figure 3 with Figure 2, it is evident that nSP is the secondary to primary turns ratio of the flyback there is no difference in the voltage and current wave- transformer forms in the traditional and no-opto flyback topologies. The voltage of interest is (V - V ) since this is a The difference is in the control method used to maintain FLYBACK IN measure of V . An internal voltage to current amplifier V at its target value over the required load, line, and O O generates a current proportional to (V - V ). This temperature range. The MAX17690 achieves this with FLYBACK IN current then flows through R to generate a ground minimum components by forcing the voltage V SET FLYBACK referenced voltage, V , proportional to (V - V ). during the conduction period of DFR to be precisely the SET FLYBACK IN This requires that: voltage required to maintain a constant VO. When QP turns off, DFR conducts and the drain voltage of Q , rises P V− VV to a voltage V above V . After initial ringing due to FLYBACK IN= SET FLYBACK IN RR transformer leakage inductance and the junction capaci- FB SET tance of DFR and output capacitance of QP, the voltage VFLYBACK is given by: Combining this equation with the previous equation for VFLYBACK, we have: (VO+ V DFR( T) +× I LS( tRT) S( )) VV= + FLYBACK IN n RFB SP VVO= SET × ×−nSP V DFR( T) − I LS( tRT) × S( ) RSET
DFR IIN ILP ILS ILO
ICIN TRANSFORMER FEEDBACK ICO VO DAUX RZ CIN VAUX LP LS CO NDRV VIN RL RU
GNDP FB1 CAUX DZ GNDS RL VIN(MAX) x dMAX GNDP GNDS GNDS ΔILP(MAX) = LP x fSW GNDP 1: nSP OPTO-COUPLER FEEDBACK ΔILP GNDS VBIAS VO LLK RFB VIN VFLYBACK
2 x IO(MAX) ΔILS(MAX) = VIN FB QP (1 – dMAX) FB2 V TO I NDRV ΔILS CONVERTER GNDP TO E/A CS SAMPLING CIRCUIT RCS GNDP RSET MAX17690 VO + VDFR + (ΔILS x RS) VIN + GNDP VFLYBACK V nSP GNDP IN GNDS
RTC RRIN RVCM t1 t3 t0 t2 t4 t5 t6
GNDP GNDP GNDP
Figure 3. Isolated no-opto flyback converter topology with typical waveforms.
www.maximintegrated.com Maxim Integrated │ 3 Temperature Compensation The effect of adding the positive temperature coefficient We need to consider the effect of the temperature depen- current, TC, to the current in RFB is equivalent to adding a positive temperature coefficient voltage in series with dence of VDFR and the time dependence of ILS on the VDFR on the secondary side of value: control system. If VFLYBACK is sampled at a time when ILS is very close to zero, then the term ILS(t) x RS(T) is VTC negligible and can be assumed to be zero in the previous ××RnFB SP expression. This is the case when the flyback converter R TC is operating in, or close to, discontinuous conduction mode. It is very important to sample the VFLYBACK voltage Substituting from the previous expression, this becomes: before the secondary current reaches zero since there is a very large oscillation on V due to the resonance δVDFR δT FLYBACK -VTC ×× between the primary magnetizing inductance of the fly- δδTVTC back transformer and the output capacitance of QP as soon as the current reaches zero in the secondary, as We can now substitute this expression into the expression shown in Figures 2 and 3. The time at which VFLYBACK is for VO as follows: sampled is set by resistor RVCM. δδ The VDFR term has a significant negative temperature RFB VTDFR VVo = SET × ×−nSP V DFR−× V tc × coefficient that must be compensated to ensure accept- RSET δδTVtc able output voltage regulation over the required tem- perature range. This is achieved by internally connecting and finally solve for RFB: a positive temperature coefficient current source to the
VSET pin. The current is set by resistor RTC connected to RSET δVDFR δT RFB = ×+VVO DFR +× V TC × ground. The simplest way to understand the temperature nVSP× SET δδTVTC compensation mechanism is to think about what needs to happen in the control system when temperature increas- Values for RSET, VSET, and δVTC/δT can be obtained from es. In an uncompensated system, as the temperature the MAX17690 data sheet as follows: increases, VDFR decreases due to its negative tempera- RSET = 10kΩ ture coefficient. Since VDFR decreases, VO increases by the same amount, therefore VFLYBACK remains unchanged. VSET = 1V Since V is proportional to V , V also remains SET FLYBACK SET δVTC/δT = 1.85mV/°C unchanged. Since there is no change in V there is no SET Values for V and δV /δT can be obtained from the change in duty cycle demand to bring V back down to DFR DFR O output diode data sheet, and n is calculated when the its target value. What needs to happen in the tempera- SP flyback transformer is designed. ture compensated case is, when VO increases due to the negative temperature coefficient of VDFR, VSET needs to The value of RTC can then be calculated using the expres- increase by an amount just sufficient to bring VO back to sion from earlier, restated below: its target value. This is achieved by designing VSET with a positive temperature coefficient. Expressed mathemat- δT δVTC RTC=−××× Rn FB SP ically as: δδVTDFR
δVR1 δV DFR ×+TC ×FB =0 The calculated resistor values for RFB and RTC should δδTnR SP T TC always be verified experimentally and adjusted, if neces- where: sary, to achieve optimum performance over the required
δVDFR/δT is the diodes forward temperature coefficient temperature range. Note that the reference design described in this document has only been verified at room δV /δT = 1.85mV/°C TC temperature. V = 0.55V is the voltage at the TC pin at +25°C. TC Finally, the internal temperature compensation circuitry Rearranging the above expression gives: requires a current proportional to VIN. RRIN should be cho- sen as approximately: δT δV = ×× ×TC RTC -R FB n SP RRIN = 0.6 x RFB δδVTDFR
www.maximintegrated.com Maxim Integrated │ 4 Setting the VFLYBACK Sampling Instant Part I: Designing the Power Components The MAX17690 generates an internal voltage propor- Step 1: Choose a Maximum Duty Cycle tional to the on-time volt-second product. This enables The maximum duty cycle, d , occurs at maximum out- the device to determine the correct sampling instant for MAX put power, PO(MAX), and minimum input voltage, VIN(MIN). VFLYBACK during the QP off-time. The RVCM resistor is used The MAX17690 no-opto flyback controller uses peak to scale this internal voltage to an acceptable internal current-mode control. Switching power converters using voltage limit in the device. Selection of this resistor is peak current-mode control exhibit subharmonic oscil- described in detail in the MAX17690 data sheet. lations at duty cycles greater than 50% unless slope compensation is added to the sensed primary MOSFET Designing the No-Opto Flyback current. Slope compensation is added internally in the Converter Using MAX17690 MAX17690 to allow stable operation up to duty cycles of Now that the principle difference between a traditional 66%, as specified in the data sheet. Choosing the max- isolated flyback converter using optocoupler or auxiliary imum allowable duty cycle ensures the highest energy transformer winding feedback and the isolated no-opto density for the power converter. For the current design, flyback converter using the MAX17690 is understood, a we have chosen: practical design example can be illustrated. The converter dMAX = 0.65 design process can be divided into three parts: the power stage design, the setup of the MAX17690 no-opto flyback Step 2: Calculate the Minimum Duty Cycle controller, and closing the control loop. This document is The MAX17690 derives the current (ΔILP) in the prima- intended to complement the information contained in the ry magnetizing inductance by measuring the voltage MAX17690 data sheet. (ΔVRCS) across the current-sense resistor (RCS) during the The following design parameters are used throughout this on-time of the MOSFET. So: document: ∆V ∆=RCS SYMBOL FUNCTION ILP RCS VIN Input voltage
VUVLO Undervoltage turn-on threshold ΔILP is a maximum at dMAX and VIN(MIN) and is a minimum at d and V so: VOVI Overvoltage turn-off threshold MIN IN(MAX)
tSS Soft-start time VV∆× f IN(MIN)= RCS(MAX) SW VO Output voltage LP RdCS× MAX ΔVO(SS) Steady-state output ripple voltage
IO Output current and
IO(CL) Maximum current-limit threshold VVIN(MAX) η ∆ RCS(min) f =××max SW PO Nominal output power LPη min Rd cs min η(MAX) Target efficiency at maximum load
η(MIN) Target efficiency at minimum load Solving the two equations above, we have:
PIN Input power η VVIN(MIN)∆ RCS(min) f Switching frequency d=×× d max × SW min max η∆VV d Duty cycle min IN(MAX) RCS(max)
nSP Secondary-primary turns ratio where ΔVRCS(MIN) and ΔVRCS(MAX) correspond to the min- imum current limit threshold (20mV) and the maximum These symbols are sometimes followed by parentheses current limit threshold (100mV) of the MAX17690, respec- to indicate whether minimum or maximum values of the tively. So, for VIN(MIN) = 10V, VIN(MAX) = 50V, and dMAX = 0.65, we have: parameters are intended, for example, the symbol VIN(MIN) is minimum input voltage. In addition, throughout the dMIN ≈ 0.04 design procedure reference is made to the schematic.
www.maximintegrated.com Maxim Integrated │ 5 Step 3: Calculate the Maximum Allowable We also know that the peak current in LP, ΔILP(MAX) occurs Switching Frequency at input voltage VIN(MIN) and MOSFET on-time tON(MAX). So: The isolated no-opto flyback topology requires the pri- ∆I mary side MOSFET to constantly maintain switching, LP( MAX) VLIN( MIN) =P × otherwise there is no way to sense the reflected second- t ON( MAX) ary-side voltage at the drain of the primary-side MOSFET. The MAX17690 achieves this by having a critical mini- Rearranging this equation and squaring, we have: mum on-time, tON(CRIT), for which it drives the MOSFET. Vt22× At a given switching frequency tON(MIN) corresponds to IN( MIN) ON( MAX) ∆=2 dMIN. From the data sheet, the critical minimum on-time I LP( MAX) L2 tON(CRIT) for the MOSFET drive output NDRV is 235ns. We p can therefore calculate the maximum switching frequency and substituting: as follows: Vt22× d IN( MIN) ON( MAX) = MIN ≈ fSW( MAX) 171,000Hz EIN( MAX) = t ON( CRIT) 2L× P we now have: Since dMIN is fixed by ΔVRCS(MIN), ΔVRCS(MAX), dMAX, VIN(MIN), and VIN(MAX), we can choose a ton(MIN), which is arbitrarily Vt22 IN( MIN) × ON( MAX) VIO × O( CL) larger than tON(CRIT) to allow a reasonable design margin. = So, if we choose tON(MIN) = 315ns we obtain a new switch- 2 x LP η×MAXf SW ing frequency as follows: Finally, by rearranging we have an expression for the d primary magnetizing inductance LP: f =MIN ≈ 128,000Hz SW t ON( MIN) η×Vd22 × MAX IN( MIN) MAX LP = Note that the MAX17690 should always be operated in 2V××O IO( CL) × fSW the switching frequency range from 50kHz to 250kHz and If we estimate the power converter efficiency η = 0.85, tON(MIN) must be chosen accordingly to ensure that this MAX constraint is met. then with VIN(MIN) = 10V, dMAX = 0.65, VO = 5V, IO(CL) = 2.2A, and f = 128,000Hz, we have: Step 4: Calculate Primary Magnetizing Inductance SW Maximum input power is given by: LP(MAX) ≈ 12.8µH PO( MAX) VIO × O( CL) ) PIN( MAX) = = This primary inductance represents the maximum pri- ηηMAX MAX mary inductance since it sets the current-limit threshold. Choosing a larger inductance will set the current-limit For the discontinuous flyback converter all the energy threshold at a lower value which would be undesirable. stored in the primary magnetizing inductance, LP, during Assuming a ±10% tolerance for the primary inductance the MOSFET on-time is transferred to the output during gives: the MOSFET off-time, i.e., the full power transfer occurs L ≈ 11.5μH during one switching cycle. Therefore, because E = P x t, P we have: Step 5: Calculate the Secondary to Primary Turns VIO × O( CL) Ratio for the Flyback Transformer EPIN( MAX) = IN( MAX) ×τSW = Assume we are operating at the border between discon- η×MAXf SW tinuous and continuous conduction modes at VIN(MIN) and P . Under this condition, the primary-side MOSFET The maximum input energy must be stored in L during O(MAX) P is conducting for (d x τ ) and the secondary-side the on-time of the MOSFET, so: MAX SW synchronous rectifier (or diode) is conducting for (1 - d ) x τ . Ideally, the primary volt-seconds per turn 1 MAX SW E= × LI ×∆ 2 must balance with the secondary volt-seconds per turn; IN( MAX) P LP( MAX) 2 however, in practice, the primary to secondary coupling of the transformer is not perfect (giving rise to uncoupled leakage inductance) and both windings have series resis- tance. Effectively, this means that to obtain the required
www.maximintegrated.com Maxim Integrated │ 6 volt-seconds per turn on the secondary winding we need Step 8: Summarize the Flyback Transformer more volt-seconds per turn on the primary winding. We Specification introduce a transformer efficiency factor, ηT, so that: We now have all the critical parameters of the flyback transformer: Vd× ×τ IN( MIN) MAX SW (VO+ V F) ×( 1d − MAX) ×τ SW = PARAMETER SYMBOL VALUE η×TPNNS Primary Magnetizing Inductance LP 12µH ±10% and Primary Peak Current ILP(MAX) 4.8A
Primary RMS Current IP(RMS) 2.23A η×(V + V) ×( 1d − ) NS T O F MAX Turns Ratio (N /N ) n 0.25 nSP = = S P SP NP Vd× MAX IN( MIN) Secondary Peak Current ILS(MAX) 14.3A
Secondary RMS Current IS(RMS) 4.9A Assuming ηT = 0.9 and VF = 0.5V (for a synchronous rectifier), then with VO = 5V, dMAX = 0.65, and VIN(MIN) = Using the parameters in the table above, a suitable trans- 10V, we have: former can be designed. n ≈ 0.27 SP Step 9: Calculate Design Parameters for Typical values of ηT range from 0.65 for an inefficient Secondary-Side Rectifying Device transformer design to 0.99 for a very efficient transformer Depending on the output voltage and current, a choice design. can be made for the secondary-side rectifying device. Step 6: Calculate the Peak and RMS Currents in Generally, for output voltages above 12V at low current the Primary Winding of the Flyback Transformer (less than 1A), a Schottky diode is used, and for voltages less than 12V a synchronous switch is used. The current The peak primary winding current occurs at VIN(MIN) and d according to the following equation: design is 5V/2A output, so we will outline a procedure for MAX selecting a suitable MOSFET for the synchronous switch. VdIN( MIN) × MAX Figure 4 shows a simplified schematic with the synchro- ∆= ≈ ILP( MAX) 4.8A nous switch Q . The MAX17606 is a secondary-side syn- LfP× SW S chronous driver and controller specifically designed for The RMS primary winding current can be calculated from the isolated flyback topology operating in Discontinuous Conduction Mode (DCM) or Border Conduction Mode ΔILP(MAX) and dMAX as follows: (BCM). d The important parameters to consider for the synchro- I =∆×≈I MAX 2.23A LP( RMS) LP( MAX) 3 nous rectifying device are the same as those of a regular rectifying diode: peak instantaneous current, RMS cur- rent, voltage stress, and power losses. Since Q and L Step 7: Calculate the Peak and RMS Currents in the S S Secondary Winding of the Flyback Transformer Again, assuming we are operating at the border between IIN ILP ILS IO discontinuous and continuous conduction modes at ICIN L L VIN(MIN) and PO(MAX). The peak secondary winding current P S ICO VO RZ is related to I and d as follows: CIN O(MAX) MAX CO VIN RL
2I× O( MAX) DZ ∆= ≈ 1: n ILS( MAX) 14.28A SP (1d− ) LLK GNDS MAX RFB VFLYBACK
The RMS secondary winding current can be calculated VIN FB QP QS from ΔILS(MAX) and dMAX as follows: NDRV GATE
MAX17690 MAX17606 (1d− MAX) II=∆×≈4.9A CS S( RMS) LS( MAX) 3 RCS
Figure 4. Simplified no-opto flyback schematic with synchro- nous rectification.
www.maximintegrated.com Maxim Integrated │ 7 are in series, they experience the same peak and RMS and PSW is the turn-on voltage-current transition loss that currents, so: occurs as the drain-source voltage decreases and the drain current increases during the turn-on transition: 2I× O( MAX) I = ≈ 14.28A 1 QS( MAX) PSW=×× fI SW QS t− ON × (1d− MAX) 2 ( ) VVGS(PL) −+ GS( TH) Q G( TOT) QGD and × VI GS(PL) DRV (1d− ) I =×≈I MAX 4.9A QS( RMS) QS( MAX) 3 ≈ 2.5mW
where IDRV is the maximum drive current capability of When QS is off, VIN reflected to the secondary side of the the GATE output of the MAX17606 and IQS(t-ON) is the flyback transformer plus (VO +VQS(SAT)) is applied across instantaneous current in QS at turn-on. IQS(t-ON) is equal the drain-source of QS, so: to IQS(MAX). VQS(MAX) = nSP x VIN(MAX) + VO + VQS(SAT) Step 10: Calculate Design Parameters for = 0.25 x 50V + 5V +(14.28A x 32.5mΩ) Primary-Side MOSFET ≈ 18V The important parameters to consider for the primary-side MOSFET (Q ) are peak instantaneous current, RMS cur- Q has both conduction losses due to its R and P S DS(ON) rent, voltage stress, and power losses. Because Q and switching losses. Allowing for reasonable design margin, P L are in series they experience the same peak and RMS Vishay part number SiR836DP was chosen for this design P currents, so from Step 6: with the following specifications: IQP(MAX) = ILP(MAX) ≈ 4.8A PARAMETER VALUE and Maximum D-S Voltage 40V I = I ≈ 2.23A Continuous Drain Current 4.1A QP(RMS) LP(RMS)
Pulsed Drain Current 20A When QP turns off, VO reflected to the primary side of the flyback transformer plus V is applied across the D-S Resistance at VGS = 7.5V 32.5mΩ IN(MAX) drain-source of Q . In addition, until Q starts to conduct, Minimum V Threshold V 1.2V P S GS GSTH there is no path for the leakage inductance energy to flow Typical VGS Plateau VGSPL 2.7V through. This causes the drain-source voltage of QP to Maximum QG(T) 18nC rise even further. The factor of (1.5) in the equation below represents this additional voltage rise; however, this factor Typical QGD 2.1nC can be higher or lower depending on the transformer and Total Output Capacitance C 100pF OSS PCB leakage inductances:
VVO + QS( SAT) The power losses in the Q can be approximated as V≈× 1.5 +V ≈ 83V S QP( MAX) IN( MAX) follows: nSP
PTOT = PCON + PCDS + PSW ≈ 785mW Allowing for reasonable design margin, Vishay part where: number SiR872ADP was chosen for this design with the PCON is the loss due to IQS(RMS) flowing through the drain- following specifications: source on resistance of QS: PARAMETER VALUE 2 PCON = I QS(RMS) x RDS(ON) ≈ 780mW Maximum D-S Voltage 150V P is the loss due to the energy in the drain-source out- CDS Continuous Drain Current 53.7A put capacitance being dissipated in QS at turn-on: Pulsed Drain Current 100A 1 D-S Resistance at V = 7.5V 40mΩ P=××× f C V2 ≈ 2mW GS CDS SW OSS QS( MAX) 2 Minimum VGS Threshold VGSTH 2.5V
Typical VGS Plateau VGSPL 6V
Maximum QG(T) 47nC
Typical QGD 10nC
Total Output Capacitance COSS 327pF
www.maximintegrated.com Maxim Integrated │ 8 The power losses in the QP can be approximated as follows: IIN ILP P = P + P + P ≈ 310mW TOT CON CDS SW L ICIN P where: RSN CSN CD CIN(CER) VIN PCON is the loss due to IQP(RMS) flowing through the drain- RD source on resistance of QP: 2 DSN PCON = I QP(RMS) x RDS(ON) ≈ 200mW
PCDS is the loss due to the energy in the drain-source out- NODE A LLK put capacitance being dissipated in QP at turn-on: NODE B VDS 1 2 P=××× f C V ≈110mW QP CDS2 SW OSS QP( MAX) NDRV COSS
MAX17690 And PSW is the turn-on voltage-current transition loss that occurs as the drain-source voltage decreases and the CS drain current increases during the turn-on transition: RCS 1 P=×× fI− × SW2 SW QP( t ON) VVGS(PL) −+ GS( TH) Q G(TOT) QGD ×≈0mW Figure 5. RCD snubber circuit. VI GS(PL) DRV where IDRV is the maximum drive current capability of So, the voltage across the leakage inductance is: the NDRV output of the MAX17690 and IQP(t-ON) is the instantaneous current in Q at turn-on. Since the flyback P VVOF+ converter is operating in Discontinuous Conduction Mode, VLLK= V CSN +− VV IN IN + nSP IQP(t-ON) is zero and therefore PSW is also zero. VVOF+∆ ISN Step 11: Select the RCD Snubber Components =−=×VLCSN LK ntSPS∆ N Referring to Figure 5, when QP turns off, ILP charges the output capacitance, COSS, of QP. When the voltage across So: C exceeds the input voltage plus the reflected second- OSS ×∆ ary to primary voltage, the secondary-side diode (or syn- LILK SN ∆=t SN chronous switch) turns on. Since the diode (or synchro- VVOF+ VCSN − nous switch) is now on, the energy stored in the primary nSP magnetizing inductance is transferred to the secondary; however, the energy stored in the leakage inductance will continue to charge COSS since there is nowhere else The average power dissipated in the snubber network is: for it to go. Since the voltage across COSS is the same as ∆ ×∆ the voltage across QP, if the energy stored in the leakage ItSN SN PVSN= CSN × inductance charges COSS to a voltage level greater than 2 ×τSW the maximum allowable drain-source voltage of QP, the
MOSFET fails. Substituting ΔtSN into this expression we have: One way to avoid this situation arising is to add a suitable 1 V = × ×∆2 × CSN × RCD snubber across the primary winding of the transform- PSN LILK SN fSW 2 VVOF+ er. In Figure 5, the snubber is labelled RSN, CSN, and DSN. VCSN − nSP In this situation, when QP turns off, the voltage at Node A is: The leakage inductance energy is dissipated in R , so V = V + V SN NODEA CSN IN from: When the secondary-side diode (or synchronous switch) turns on, the voltage at Node B is: 2 V CSN P = SN R VVOF+ SN VVNODEB= IN + nSP
www.maximintegrated.com Maxim Integrated │ 9 We can calculate the required RSN as follows: Step 12: Calculate the Required Current-Sense Resistor 2 V CSN From Step 4 we have the maximum input power given by: R = SN 1 V ×LI ×∆2 × CSN ×f P VI× LK SN SW O( MAX) O O( MAX) 2 VVOF+ P = = VCSN − IN( MAX) ηη nSP For the discontinuous flyback converter all the energy Over one switching cycle we must have: stored in the primary magnetizing inductance, LP, during the MOSFET on-time is transferred to the output during VVCSN ∆ SN ICSN = =SN × the MOSFET off-time, i.e., the full power transfer occurs RSN τSW during one switching cycle. Therefore, since E = P x t, we have: So, we can calculate the required CSN as follows: VIO × O( MAX) = ×τ = VCSN EPIN( MAX) IN( MAX) SW CSN = η×fSW ∆VCSN ×× Rf SN SW
The maximum input energy must be stored in LP during Generally, ΔVCSN should be kept to approximately 10% the on-time of the MOSFET, so: to 30% of VCSN. Figure 6 illustrates VCSN, ΔISN, and ΔtSN. The voltage across the snubber capacitor, VCSN, should 1 2 be selected so that: E= × LIP ×∆ IN( MAX) 2 LP( MAX) VCSN < QP(DSMAX) – VIN(MAX)
Choosing too large a value for VCSN causes the voltage on the drain of QP to get too close its maximum allowable drain-source voltage, while choosing too small a value ∆ILP(MAX) results in higher power losses in the snubber resistor.
A reasonable value should result in a maximum drain ∆ILP voltage on QP that is approximately 75% of its maximum allowable value. The worst-case condition for the snubber circuit occurs at maximum output power when: ∆ISN
ΔISN = ILP(MAX) ∆ISN Assuming the leakage inductance is 2.5% of the primary inductance, then choosing VCSN = 63V and ΔVCSN = 18V, we get the following approximate values: ∆tSN
PSN = 810mW
∆ILS RSN = 5kΩ
CSN = 4.7nF
Finally, we consider the snubber diode, DSN. This diode VCSN VO + VF should have at least the same voltage rating as the VDS VIN + n VIN SP MOSFET, QP. Although the average forward current is very low, it must have a peak repetitive current rating t6 greater than ILP(MAX). Figure 6. RCD snubber circuit waveforms.
www.maximintegrated.com Maxim Integrated │ 10 Therefore: And finally, since:
× 1 VIO O( MAX) 1 fSW ×LI ×∆2 = = P LP( MAX) t−− t 1d 2fη× SW ( 21) ( ) and we have:
×× 2VO IO( MAX) VIOO× 1 (1d− ) ∆=I C = ×× LP IN η×VV ∆ f η×LfP × SW IN CIN SW From Step 2 we have: For maximum high-frequency ripple voltage requirement ΔVCIN, we can now calculate the required minimum CIN. ∆ VRCS An additional high-frequency ripple voltage occurs at the ∆=ILP RCS input due to the ESR of the input capacitor. This ripple voltage is generally much smaller than the amp second so product voltage ripple and can be minimized by choosing a capacitor with low ESR. η×LfP × SW RVCS=∆× RCS There is high-frequency AC current flowing in CIN, as 2V××O IO( MAX) shown in the center waveform of Figure 7. The selected capacitor must be specified to tolerate this maximum Substituting values for ΔVRCS, η, LP, fSW, VO, and IO(MAX) RMS current, ICIN(RMS). From the simplified schematic: we have: ILP = IIN + ICIN R ≈ 21mΩ CS Therefore: where ΔVRCS = 100mV, the maximum CS current-limit threshold of the MAX17690. We can choose a standard I= II22− 20mΩ resistor for RCS. CIN( RMS) LP( RMS) IN( RMS) Step 13: Calculate and Select the Input Capacitors Figure 7 shows a simplified schematic of the primary side where: of the flyback converter and the associated current wave- × forms. In steady-state operation, the converter draws a VIOO IIN( RMS) = pulsed high-frequency current from the input capacitor, η×VIN CIN. This current leads to a high-frequency ripple voltage across the capacitor according to the following expression: and from Step 6:
∆VCIN d IC= × II=∆×LP CIN IN ∆t LP( RMS) 3
So: It is the ripple voltage arising from the amp second prod- 22 uct through the input capacitor. d 2 VIoo× IICIN( RMS) = ×∆LP − 3 η×22 During the QP on-time interval from t0 to t1, the capacitor VIN is supplying current to the primary inductance L of the P The maximum RMS current in the input capacitor occurs flyback transformer and its voltage is decreasing. During at dMAX, ΔILP(MAX), IO(MAX), and VIN(MIN). the QP off-time time interval from t1 to t2, no current is flow- ing in LP, and current is being supplied to capacitor from ICIN(RMS) ≈ 1.6ARMS the input voltage source. According to the charge balance An additional high-frequency ripple voltage is present law, the decrease in capacitor voltage during time t0 to t1 due to the RMS current flowing through the ESR of the must equal the increase in capacitor voltage during time capacitor. Ceramic capacitors are generally used for t1 to t2. So: limiting high-frequency ripple due to their high AC current capability and low ESR. ∆×V VI IC=×=CIN O O CIN[ t12 to t ] IN (tt2− 1) η× V IN
www.maximintegrated.com Maxim Integrated │ 11 we have: ISRC LIN(STRAY) IIN ILP ∆I2 ICIN LP IN( MAX) CLIN = IN( STRAY) × ∆V 2 VIN CIN(ELE) CIN(CER) CIN
We now have two values for CIN. One for input high-fre-
CIN quency ripple-voltage control:
LLK RFB VI× 1 (1d− ) VFLYBACK C =oo ×× IN( CER) η×VV ∆ f VIN FB QP IN CIN SW NDRV and a second for transient input voltage control: MAX17690 CS ∆I2 IN( MAX) = × RCS CLIN( ELE) IN( STRAY) ∆ 2 VCIN
If CIN(ELE) > CIN(CER), both ceramic and electrolytic capac- VIN(MAX) x dMAX itors must be used at the input of the power supply and ΔILP(MAX) = LP x fSW ΔVCIN should be limited to approximately 75mV to keep the AC current in the ESR of the electrolytic capaci- ILP tor within acceptable limits. Otherwise, CIN(ELE) is not required. In this case, the value of CIN(CER) can be signifi- cantly reduced since there is no longer any requirement to limit ΔVCIN to less than 75mV. Based on the current design
VO x IO(MAX) specification, we have: ICIN ΔIIN = η x VIN CIN( CER) ≈ 54µ
And:
CIN( ELE) ≈ 23µ IIN VO + IO(MAX) IIN = η x VIN Since CIN(ELE) < CIN(CER), an electrolytic capacitor is not required. We can now recalculate C based on a t0 t1 t2 IN(CER) ΔVCIN = 400mV: Figure 7. Primary-side circuit and currents. CIN(CER) ≈ 10µ If we allow for a capacitor tolerance of ±10% and a further In addition to using a ceramic capacitor for high-frequency reduction of capacitance of 70% due to the DC bias effect input ripple-voltage control as described above, an elec- (operating an 80V ceramic capacitor at 50V), our final trolytic capacitor is sometimes inserted at the input of a nominal value is: flyback converter to limit the input voltage deviation when there is a rapid output load change. A 100% load change CIN(CER) ≈ 30µ gives rise to an input current transient of: We can achieve this by placing six 4.7µF ceramic capac- VIO × O( MAX) itors (Murata GRM32ER71K475KE14) in parallel. The AC ∆= IIN( MAX) current in each capacitor is: η×VIN( MIN)
During this transient, there is a voltage drop across any ICIN( RMS) ≈ 0.27ARMS series stray inductance, LIN(STRAY), that exists between the 6 input voltage source and the input capacitor of the power supply. So from: which is well within specification for the selected capacitor.
11 ×CV ×∆22 = × L×∆ I 22IN CIN IN( STRAY) IN
www.maximintegrated.com Maxim Integrated │ 12 Step 14: Calculate and Select the Output Capacitor D High-frequency ripple voltage requirements are also used ILS FR ILO to determine the value of the output capacitor in a flyback converter. ICO VO RZ Figure 8 shows a simplified schematic of the secondary CO RL side of the flyback converter and the associated current waveforms. DZ
In steady-state operation, the load draws a DC current GNDS from the secondary side of the flyback converter. By examining the secondary current waveforms, we see that 2 x IO(MAX) CO is supplying the full output current IO to the load during ΔILS(MAX) = (1 – dMAX) the time interval from t2 to t3. During this time interval, ILS the voltage across CO decreases. At time t3, QP has just turned off and the secondary rectifying diode DFR (or the secondary synchronous switch QS) starts to conduct supplying current to the load and to CO. The charging and discharging of CO leads to a high-frequency ripple voltage at the output according to the following expression: ICO IO
∆V IC= × CO CO O ∆t
Again, as with the input capacitor, this is the ripple voltage IO arising from the amp second product through the output IO capacitor.
By the capacitor charge balance law, the decrease in t0 t1 t2 t3 capacitor voltage during time t2 to t3 must equal the increase in capacitor voltage during time t1 to t2. When the Figure 8. Secondary-side circuit and currents. capacitor is discharging, we have:
∆V Also, as with the input capacitor, there is high-frequency IC=×=CO I CO[ t to t ] OO AC current flowing in C as shown in the center waveform 23 (tt32− ) O of Figure 8. The selected capacitor must be specified to Finally, since: tolerate this maximum RMS current, ICO(RMS). From the simplified schematic: 1 f = SW ILS = IO + ICO (tt32− ) d We have: Therefore:
1d I= II22− CIOO=×× CO(RMS) LS(RMS) O(RMS) ∆VfCO SW
At maximum output current, the discontinuous flyback where: converter should ideally operates on the border between IO(RMS) = IO discontinuous and continuous conduction modes and so and from Step 6: dMAX should be substituted in the above equation. For maximum high-frequency ripple voltage requirement 2I× O (1d− ) ILS( RMS) = × ΔVCO, we can now calculate the required minimum CO. (1d− ) 3 C ≈ 220µF O so: As with the input capacitor, an additional high-frequen- cy ripple voltage occurs at the output due to the output 2 1d− 2I× capacitor’s ESR and can be minimized by choosing a II=×−o 2 CO( RMS) − o capacitor with low ESR. 3 1d
www.maximintegrated.com Maxim Integrated │ 13 The maximum RMS current in the output capacitor occurs Step 15: Summarize the Power Component Design at dMAX, ΔILS(MAX), IO(MAX), VIN(MIN), so: We have now made a first pass at calculating all the power components in the no-opto flyback converter using I ≈ 4.2ARMS CO(RMS) the MAX17690. Referring to the schematic we have: If we allow for a capacitor tolerance of ±10% and a fur- POWER QTY DESCRIPTION ther reduction of capacitance of 50% due to the DC bias COMPONENT effect (operating a 6.3V ceramic capacitor at 5V), our final FLYBACK TRANSFORMER nominal value is: PRI. INDUCTANCE = 12µH SEC-PRI TURNS RATIO = 0.25 110µF PEAK PRI. CURRENT = 4.8A CO = ≈ 500µ 90%× 50% T1 1 PEAK SEC. CURRENT = 14.3A MAX. PRI. RMS CURRENT = 2.23A We can achieve this by placing five 100µF ceramic capac- MAX. SEC. RMS CURRENT = 4.9A itors (Murata GRM32EE70J107ME15) in parallel. The AC SWITCHING FREQUENCY = current in each capacitor is: 128kHz INPUT CAPACITORS I C2, C3, CAPACITOR; SMT (1210); CERAM- CO( RMS) 6 ≈ 0.84ARMS C18-C21 IC CHIP; 4.7µF; 80V; 10%; X7R 5 MURATA GRM32ER71K475KE14 which is well within specification for the selected capacitor. OUTPUT CAPACITORS C10, C11, CAPACITOR; SMT (1210); CERAM- C22, C22A, 5 IC CHIP; 100µF; 6.3V; 20%; X7U C22B MURATA GRM32EE70J107ME15 CURRENT-SENSE RESISTOR RESISTOR; 0805; 0.02 OHM; 1%; R12 1 75PPM; 0.25W; THICK FILM VISHAY DALE WSL0805R- 0200FEA18 PRIMARY-SIDE MOSFET TRAN; N-CHANNEL 150V (D-S) MOSFET; NCH; SO-8; PD-(104W); Q1 1 I-(53.7A); V-(150V) VISHAY SILICONIX SIR- 872ADP-T1-GE3 SECONDARY-SIDE SYNCHRO- NOUS MOSFET TRAN; N-CHANNEL 40 V (D-S) Q2 1 MOSFET; NCH; SO-8; PD-(15.6W); I-(21A); V-(40V) VISHAY SILICONIX SIR836DP-T1- GE3
Part II: Setting Up the MAX17690 No-Opto Flyback Controller Step 16: Setting Up the Switching Frequency The MAX17690 can operate at switching frequencies between 50kHz and 250kHz (subject to the consider- ations in Step 3). A lower switching frequency optimizes the design for efficiency, whereas increasing the switch- ing frequency allows for smaller inductive and capacitive components sizes and costs. A switching frequency of 128kHz was chosen in Step 3. R9 sets the switching fre- quency according to the following expression:
www.maximintegrated.com Maxim Integrated │ 14 the stable operation over the full temperature range. 5× 106 R 9 = ≈Ω5 1k Place this capacitor as close as possible to the IC. f SW Step 20: Setting Up the Feedback Components R , R , R , R , and R are all critically important where R9 is in kΩ and fSW is in Hz. SET FB RIN VCM TC to achieving optimum output voltage regulation across all Step 17: Setting Up the Soft-Start Time specified line, load and temperature ranges. The capacitor C6 connected between the SS pin and RSET resistor: This resistor value is optimized based on SGND programs the soft-start time. A precision internal the IC’s internal voltage to current amplifier and should 5μA current source charges the soft-start capacitor C6. not be changed. During the soft-start time, the voltage at the SS pin is used as a reference for the internal error amplifier during start- R5 = RSET = 10kΩ up. The soft-start feature reduces inrush current during RFB resistor: The feedback resistor is calculated accord- startup. Since the reference voltage for the internal error ing to the following equation: amplifier is ramping up linearly, so too is the output volt- age during soft-start. The soft-start capacitor is chosen RSET RFB = × based on the required soft-start time (10ms) as follows: nVSP× SET C6 = 5 x tSS ≈ 50nF δV δT VV+ +× V DFR × where C6 is in nF and t is in ms. A standard 47nF O DFR TC SS δδTVTC capacitor was chosen. Step 18: Setting Up the UVLO and OVI Resistors Since we are using a synchronous MOSFET for rectifica- tion on the secondary side, we can assume that δV / A resistor-divider network of R1, R3, and R2 from V to DFR IN δT = 0, so: SGND sets the input undervoltage lockout threshold and the output overvoltage inhibit threshold. The MAX17690 RSET does not commence its startup operation until the volt- RFB = ×+{VOV DFR} ≈204kΩ age on the EN/UVLO pin (R3/R2 node) exceeds 1.215V nVSP× SET (typical). When the voltage on the OVI pin (R1/R3 node) exceeds 1.215V (typical), the MAX17690 stops switching, From the MAX17690 data sheet, VSET = 1V. The two thus inhibiting the output. Both pins have hysteresis built resistors R4 = 200kΩ and R15 = 3.92kΩ form RFB. Using in to avoid unstable turn-on/turn-off at the UVLO/EN and one high value resistor and one low value resistor in OVI thresholds. After the device is enabled, if the voltage series allows slight adjustment to the series resistance on the UVLO/EN pin drops below 1.1V (typical), the con- combination so that the output voltage can be fine-tuned troller turns off; after the device is OVI inhibited, it turns to its required value, if necessary. back on when the voltage at the OVI pin drops below RRIN resistor: The internal temperature compensation 1.1V (typical). Whenever the controller turns on, it goes circuitry requires a current proportional to VIN. RRIN is cal- through the soft-start sequence. For the current design culated according to the following equation: R1 = 10kΩ, R2 = 365kΩ, and R3 = 40.2kΩ give rise to an R ≈ 0.6 x R UVLO/EN threshold of 9V and an OVI threshold of 51V. RIN FB RVCM resistor: The MAX17690 generates an internal Step 19: Placing Decoupling Capacitors on VIN voltage proportional to the on-time volt-second product. and INTVCC This enables the device to determine the correct sampling As previously discussed, the MAX17690 no-opto flyback instant for VFLYBACK during the QP off-time. Resistor R6 is controller compares the voltage VFLYBACK to VIN. This volt- used to scale this internal voltage to an acceptable inter- age difference is converted to a proportional current that nal voltage limit in the device. To calculate the resistor, we flows in R5. The voltage across R5 is sampled and com- must first calculate a scaling constant as follows: pared to an internal reference by the error amplifier. The output of the error amplifier is used to regulate the output 8 (1−× dMAX) 10 voltage. The V pin should be directly connected to the K = = 120 IN C 3f× input voltage supply. For robust and accurate operation, a SW ceramic capacitor (C14 = 1µF) should be placed between where dMAX = 0.65 and fSW = 128,000. After KC is calcu- VIN and SGND as close as possible to the IC. lated, the R6 value can be selected from the table below VIN powers internal low dropout regulator of the MAX17690. by choosing the resistance value that corresponds to the The regulated output of the LDO is connected to the next largest KC. INTVCC pin. A ceramic capacitor (C4 = 2.2µF min) should be connected between the INTVCC and PGND pins for
www.maximintegrated.com Maxim Integrated │ 15 imum value to its maximum value is the response time, KC R6 τ , of the control loop. For the MAX17690 we have: 640 0Ω RES 320 75kΩ 11 τ≈ + 160 121kΩ RES 3f× C f SW 80 220Ω 40 Open where fC is the bandwidth of the power converter. If we In the present case, R6 = 121kΩ. apply a switching load step of amplitude ΔISTEP, at a fre- quency of (1/τRES) and a 50% duty cycle then, to limit the R resistor: The value of R can then be calculated TC TC output voltage deviation to ±ΔVO(STEP) we must have a using the previous expression, restated below: minimum output capacitance of: τ δT δV ∆×RES R=−×× Rn ×TC ISTEP TC FB SP δδVT 2 DFR CO( MIN) = ∆VO( STEP) Since we are using a synchronous MOSFET for second- Combining the two previous equations, we have: ary-side rectification, we can assume that the temperature coefficient δV /δT is zero so R should be infinite (i.e., 1 DFR TC ×fISW ×∆ O( STEP) open circuit). f = 3 C 2f× × C ×∆ V −∆ I This completes the setup of the MAX17690 no-opto fly- SW O( MIN) O( STEP) O( STEP) back controller. It is normal to specify ΔVO(STEP) for a load step from 50% Part III: Closing the Control Loop to 100% of the maximum output current. We have already calculated CO(MIN) = 220µF in Step 14, fSW = 128,000Hz, Step 21: Determine the Required Bandwidth so based on a 3% maximum ΔVO(STEP): The bandwidth of the control loop determines how quickly fC ≈ 4.3Hz the converter can respond to changes at its input and output. If we have a step change in output current the Step 22: Calculate the Loop Compensation voltage across the output capacitor decreases as shown The MAX17690 uses peak current-mode control and an in Figure 9. internal transconductance error amplifier to compensate The control loop detects this reduction in output voltage the control loop. The control loop is modelled, as shown in Figure 10, by a power modulator transfer function G and increases the duty cycle of QP to supply more current MOD(s) to the output capacitor. The amount of time required by an output-voltage feedback transfer function GFB(s) and an the control loop to increase the duty cycle from its min- error amplifier transfer function GEA(s). The power modulator has a pole located at fp(MOD) deter- mined by the impedance of the output capacitor CO and the load impedance RL. It also has a zero at fz(MOD) ΔIO(STEP) determined by the impedance of CO and the ESR of CO. IOH The DC gain of the power modulator is determined by the
IOL
t
V OH vi Σ GMOD(s) vO ΔVO(STEP) + VO -
VOL GEA(s) GFB(s)
t
Figure 9. Output load step response. Figure 10. Model of control loop.
www.maximintegrated.com Maxim Integrated │ 16 peak primary current ΔILP and the current-sense resistor To achieve stable operation, we must ensure that: RCS. So: fp(MOD) f C< f SW / 20 1 = GMOD(dc) Set the closed loop gain at f equal to 1: ∆×IRLP CS C GMOD(fc)×× GG FB(fc) EA(fc) = 1 1 IO(MAX) fp(MOD) = = 2Cπ×OL × R 2C π× OO × V Place the zero in the error amplifier network at the same and: frequency as the pole in the power modulator transfer 1 function: fz(MOD) = 2π× CO × ESR CO ffZ(EA)= p(MOD) The output voltage feedback transfer function GFB(S) is independent of frequency and has a DC gain determined by VIN, VFLYBACK, and Vset as follows: 1 I = O(MAX) VSET Vn SET× SP 2Cπ×ZZ × R 2C π× OO × V GFB(DC) = = VFlyback−+ V IN VV O DFR Place the pole in the error amplifier network at the same The transconductance error amplifier of the MAX17690 frequency as the zero in the power modulator transfer should be set up in a configuration to compensate for the function: pole at fp(MOD) and the zero at fz(MOD) of the modulator. This can be achieved by type II transconductance error ffp(EA)= z(MOD) amplifier compensation shown in Figure 11. 11 This type of compensation scheme has a low frequency = pole at fp-lf(EA) due to the very large output resistance 2π× CP × R Z 2 π× C O × ESR CO RO (30mΩ - 50MΩ) of the operational transconductance amplifier (OTA). It has a zero at fz(EA) determined by The frequency fz(MOD) at which the zero occurs in the CZ and RZ of the compensation network, and it has an power modulator transfer function depends on the ESR additional pole at fp(EA) determined by CP and RZ of the of CO. If ceramic capacitors are used for CO, fZ(MOD) will compensation network. So: generally be much higher than fC. However, if the ESR of C is large, f could be lower than f . This is a very 1 O Z(MOD) C f − = important point since both the gain of the power modula- P lf(EA) 2π× C × (R + R ) z OZ tor at fC, and the gain of the error amplifier at fC depend 1 on whether fZ(MOD) is greater than or less than fC. This is fz(EA) = illustrated in Figure 12. 2π× CzZ × R) and: By examining the gain plots in Figure 12, we see that: 1 = fp(EA) For f > f : 2Cπ×PZ × R Z(MOD) C fp(MOD) GGMOD(fc)= MOD(DC) × fC
GEA(fc)= gR m(EA) × Z
MAX17690 and for fZ(MOD) < fC: COMP
CZ fp(MOD) GG= × MOD(fc) MOD(DC) f CP z(MOD) RZ fZ(MOD) GEA(fc)= gR m(EA) ×× Z fC
Figure 11. Type II compensation for OTA.
www.maximintegrated.com Maxim Integrated │ 17 and since GFB is independent of frequency, we have:
Vn× GAIN CLOSED LOOP = = SET SP (dB) GGFB(fc) FB(DC) VVO+ DFR POWER MODULA TOR ERROR We can now set the closed-loop gain equal to 1 as follows: AMPLIFIER ××= fc GMOD(fc) GG1 FB(DC) EA(FC) 0dB fpMOD FREQUENCY 1 fP(MOD) VnSET× SP FB × × ×gm(EA) ×= R1 Z DIVIDER ∆×I R f VV+ fzMOD LP CS C O DFR
Simplified Gain Plot for fz(MOD) > fC Rearranging we can calculate:
1 (V+ V ) f R= × O DFR× C ×RI ×∆ Z CS LP gm(EA) Vn SET× SP f p(MOD)
CLO SED LOOP Substituting ΔI from Step 12: GAIN LP (dB) PO WER 1 (V+ V ) f 2V××O I O(MAX) MO DULATO R RR= ×O DFR × C ×× ERRO R Z g V× n f CS η×Lf × AMPLIFIER m(EA) SET SP p(MOD) P SW
Rz = 12kΩ 0dB fpMO D FREQ UENCY Finally, we can calculate the remaining components, CZ and
FB CP, in the error amplifier compensation network as follows: f fc DIVIDER zMO D 1 CZ = = 47nF Simplified Gain Plot for fz(MOD) < fC 2fπ×p(MOD) × R Z and: Figure 12. Simplified gain plot. 1 CP = = 5pF 2fπ×Z(MOD) × R Z For the current design, we have:
I f = O ≈ 370Hz p(MOD) ×π× × 2 VCOO Design Resources Download the complete set of Design Resources and: including the schematics, bill of materials, PCB layout, and test files. 1 f Z(MOD) = ≈ 2.7MHz 2×π× esrCO × C O where CO = 220μF as calculated in Step 14 and esrCO = 200µΩ for five MURATA GRM32EE70J107ME15 capaci- tors in parallel.
Since fZ(MOD) > fC:
ffP(MOD) 1 P(MOD) GGMOD(fc)= MOD(DC) ×= × fC∆× IR LP CS f C
GEA (fc)= gR m(EA) × Z
www.maximintegrated.com Maxim Integrated │ 18 Revision History
REVISION REVISION PAGES DESCRIPTION NUMBER DATE CHANGED 0 10/17 Initial release —
Maxim Integrated www.maximintegrated.com
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
© 2017 Maxim Integrated Products, Inc. All rights reserved. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc., in the United States and other jurisdictions throughout the world. All other marks are the property of their respective owners.