Accelerating XML Processing with Intel® SSE4.2 to Improve Business Solutions

Accelerating XML Processing with Intel® SSE4.2 to Improve Business Solutions White Paper The Intel® XML Software Suite enables solution makers to easily Intel® XML Software Suite deliver faster XML processing with a standards-based solution that outperforms leading open-source implementations, for better results in a diverse range of enterprise solutions. It also simplifies the continued improvement of XML-based solutions through enhanced feature support for upcoming generations of Intel® architecture-based servers. Support for Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) instructions built into the Intel XML Software Suite allows applications to immediately deliver performance improvements of as much as 20 percent or more. White Paper: Intel® XML Software Suite

Table of Contents

Prepare Solutions to Win on Next-Generation Hardware with Intel SSE4.2 ��4

Build Solution Profitability with Intel® XML Software Suite ��5

Improve the Quality of Both Java* and C/C++ Solutions ��6

Accelerate XML Parsing Without Building Anything New ��8

Implement Pre-Optimized Components for Faster XML Schema Validation ��9

Conclusion �� 11

Additional Resources �� 11

2 White Paper: Intel® XML Software Suite

As IT organizations of all sizes struggle to accomplish more with less, many are turning to new types of solutions in areas such as Service-Oriented Architecture (SOA), Software as a Service (SaaS), Web 2.0, and enterprise applications. These novel approaches can help organizations improve return on investment while increasing agility. Because this is new ground for many companies, they look to external expertise to show them the way, which provides a dramatic opportunity for solution providers.

Extensible Markup Language (XML) has become the industry standard for the machine-to-machine communication that underlies these innovative solution approaches. To make the most of this opportunity for itself and its customers, Intel is delivering technologies that increase the performance of XML solutions while also making it faster and less expensive to bring them to market.

The Intel XML Software Suite provides highly optimized building blocks for XML-based solutions that let solution providers focus on Build a Better XML Solution product innovation instead of reinventing the plumbing that underlies The Intel® XML Software Suite streamlines the development of it. This comprehensive suite of high-performance C++ and Java* standards-based XML solutions while improving their quality: software-based runtime libraries for Linux* and Windows* operating • Takes automatic advantage of new Intel® CoreTM i7 systems is engineered to automatically take advantage of new processor features, such as Intel® SSE4.2 Intel® CoreTM i7 processor features, such as Intel SSE4.2. This latest enhancement to Intel’s instruction set architecture builds on previous • Immediately adds as much as 20 percent or more performance improvements without having to recode advances to deliver superior performance and energy efficiency for the application 32-bit and 64-bit applications. • Decreases code maintenance, relative to internally In addition to taking advantage of Intel SSE4.2 instructions, developed components innovative architecture within the Intel XML Software Suite delivers • Improves total cost of ownership for both solution excellent results even on legacy systems that do not support this providers and IT new instruction set architecture. The Intel XML Software Suite has significantly better performance and scalability than many open-source projects, while maintaining compliance with industry specifications. The performance white paper available at http://softwarecommunity.intel.com/isn/downloads/software products/pdfs/XSSPerformancePaper.pdf demonstrates speedups of 2x or more relative to open-source implementations, available from the Intel XML Software Suite on previous server architectures.

3 White Paper: Intel® XML Software Suite

Prepare Solutions to Win on Next-Generation (16 bytes or eight words of two bytes each) that are packed into the Hardware with Intel SSE4.2 same 128-bit XMM registers on which SSE operates. Unlike other Intel SSE 4.2 is a set of seven new instructions supported by the SSE instructions, however, they can leverage parallelism in a second Intel Core i7 processors that power the next generation of server dimension, by performing multiple search or compare operations on and desktop systems. It includes four instructions that use SIMD each character, yielding up to 256 operations in a single instruction. techniques to accelerate string and text processing, which provide This is the source of the greatest potential for speedup, and it enables significant performance benefits in XML processing. a reduction in the number of instructions required.

Intel SSE4.2 requires no new operating system support to save and In addition to exploiting parallelism in two dimensions, these restore the register state beyond what is required by SSE. Moreover, instructions are functionally rich. One input provides the input string, Intel SSE4.2 is fully compatible with software written for previous another provides the reference string against which the input string generations of microprocessors with Intel® 64 and IA-32 architectures. is compared, and an immediate operand specifies parameters that Existing software continues to run correctly without modification control the instruction’s operation. The input strings may be either on microprocessors that incorporate Intel SSE4.2, as well as in the fixed length or null terminated; the variants of the instructions for presence of existing and new applications that incorporate the new those two cases are shown in Table 1. The results of comparison instruction set. Intel SSE4.2 advances software processing of string operations can be either an index of the first or last match, or a mask and text data several ways: of which characters or strings matched. Variants of the instructions are provided that enable developers to select between these two • Generalized 16-byte granularity processing, without 16-byte output data forms, as shown in Table 1. alignment restrictions in terms of memory operations The control parameters specify the operation, as shown in Table 2. • Flexibility in handling explicit-length and null-terminated strings, The equal each operation, which performs a string match (that is, using 8/16-bit character sets a comparison of corresponding characters) is the most intuitively recognizable. The acceleration advantage of these instructions comes • Streamlined looping control using flag updates from doing multiple operations in parallel: equal any compares each • Rich, built-in lexical processing primitives suitable for a wide range of input string character against a set of characters, ranges compares situations, from string search and tokenization to case conversions each input string character against a set of character ranges, and These new instructions include advanced packed-string comparison equal ordered compares a set of substrings against the (shortened) functionality. Like other SSE instructions, they can take advantage reference string. of data-level parallelism by operating on multiple characters at once

Output Data

Return an Index Return a Mask

PCMPESTRI — Packed Compare Explicit Length PCMPESTRM — Packed Compare Explicit Length Strings; Strings; Return an Index. This instruction performs a Compare Explicit Return a Mask. This instruction performs a packed comparison packed comparison of data from two string fragments

InputData Length Strings of string data with explicit lengths, generating a mask and with explicit lengths, generating an index and storing the storing the result in XMM0. result in ECX.

PCMPISTRI — Packed Compare Implicit Length PCMPISTRM — Packed Compare Implicit Length Strings; Compare Implicit Strings; Return an Index. This instruction performs a Return a Mask. This instruction performs a packed comparison Length Strings packed comparison of string data with implicit lengths, of string data with implicit lengths, generating a mask and generating an index and storing the result in ECX. storing the result in XMM0.

Table 1. Intel® SSE4.2 string and text handling instructions.

4 White Paper: Intel® XML Software Suite

Operation Mode Comparison

For each character in the input string, compare against all characters in the reference string. Evaluate per-character comparisons to true if there is any exact match. Equal any: find characters from a set The instruction result is either an index (first or last) of a match when using the pcmpXstri instruction, or a mask indicating whether each character in the input string matched when using pcmpXstrm.

For each character in the input string, compare against all ranges in the reference string. Ranges are specified as a pair, in even and odd slots of the reference string. Ranges: find characters from ranges Evaluate per-character comparisons to true if (lower bound ≤ character ≤ upper bound) for any range. The instruction result is either an index (first or last) of a match when using the pcmpXstri instruction, or a mask indicating whether each character in the input string matched when using pcmpXstrm.

For each character in the input string, compare against corresponding characters in the reference string (that is, byte 0 compared to byte 0, byte 1 to byte 1, and so on). Equal each: string compare The instruction result is either an index (first or last) of the matching characters when using the pcmpXstri instruction, or a mask indicating which characters in the input string matched when using the pcmpXstrm instruction.

For each character in the input string, compare the string starting at that character against the reference string that has been shortened to a corresponding number of characters. Equal ordered: substring search The instruction result is either an index (first or last) of the starting character of a matching substring when using the pcmpXstri instruction, or a mask indicating which substrings of the input string matched, when using the pcmpXstrm instruction.

Table 2. Intel® SSE4.2 string and text handling instruction operations specified in an instruction parameter.

Build Solution Profitability with Intel® XML • Faster Adoption. Because Intel updates the components Software Suite associated with the product in conjunction with new generations To power XML-based solutions, vendors must obtain the underlying of processors, solutions based on the Intel XML Software Suite mechanisms that interpret and process the XML streams from an automatically inherit optimizations for new architectures as they external source, or they must build those mechanisms themselves. are introduced. Engineering and support in conjunction with Intel In the former case, open-source components such as those provided hardware engineers helps to ensure world-class performance, by the Apache Foundation’s Xerces* and Xalan* projects, as well as stability, and support. GNOME’s libXML and libXSLT libraries are a common choice. Although • Simplified Maintenance. That same ongoing update process by these are high-quality components, a significant lag is typical in taking Intel lessens the burden of code maintenance for solution vendors, advantage of new hardware architectures and features, as techniques who are able to focus their resources on activities that add more for taking advantage of those features take some time to become differential value. That capability reduces development cost and known throughout the community. speeds up time to market.

Likewise, those solution vendors that choose to build the XML- processing components for their solutions in-house are faced with ongoing requirements for the maintenance of that code, which can draw out project timelines and drain project resources. The Intel XML Software Suite overcomes both these types of limitations:

5 White Paper: Intel® XML Software Suite

For example, the Intel XML Software Suite is pre-optimized to use the • Intel® XPath Accelerator—evaluates XML Path (XPath) Intel SSE4.2 instructions, supported by Intel Core i7 processor-based expressions. XPath is a language that enables the navigation and server and desktop systems. While continuing to deliver excellent data manipulation of XML documents. The Intel XPath Accelerator results from previous processors, these components dramatically evaluates XPath expressions using XML data and returns a node, improve performance with Intel SSE4.2 string and text processing node set, string, number, or Boolean value. It also supports and functionality. Solution vendors will receive these benefits, particularly resolves user-defined namespace contexts, variables, and functions. for XML parsing and schema validation, without being involved in the Optionally, XPath expressions can be compiled to further enhance deep details of algorithmic and instruction-level optimizations. XML processing performance. The current distribution of the Intel XML Software Suite includes The Intel XML Software Suite is standards compliant, to allow for easy multiple examples that show you how to use the product with your integration into existing XML environments. It is optimized to support application. The examples are packaged with source files, a makefile, complex and large-size XML document processing, with outstanding and sample input documents. You can run the examples over the performance, efficient memory management, and thread-safe sample files shipped with them or over your own files. operation. The suite’s primary components include the following: Improve the Quality of Both Java* • Intel® XML Parsing Accelerator—reads XML files to make and C/C++ Solutions data available to applications. The Intel XML Parsing Accelerator The Intel XML Software Suite provides superior performance while parses data according to several standard models: Simple API conforming to industry standards, enabling solutions to provide for XML (SAX), Streaming API for XML (StAX), Document Object robust feature sets. It also has significantly better performance and Model (DOM), and an internal storage data-stream model for scalability than competing solutions, while maintaining compliance to processing between the Intel XML Software Suite components. industry specifications. As demonstrated in this paper, the Intel XML Parsing Accelerator achieves significant performance gains from the use of Intel To facilitate performance measurement of XML solutions, Intel SSE4.2 instructions. provides the XML Benchmark Tool (XBT), free of charge. It provides a framework that allows a user to analyze the performance of various • Intel® XML Schema Accelerator—verifies validity of XML XML processing engines, such as the Intel XML Software Suite, and to documents. This component compares XML documents against compare the results. The XML Benchmark Tool is currently validated on standards-based rules and constraints specific to the XML 32-bit and 64-bit Intel architecture and compatible platforms and allows application environment to ensure they meet application and testing of Java and C++ based XML processing engines running on environment requirements for processing. The Intel XML Schema Windows and Linux. It supports performance testing of XML parsing Accelerator efficiently validates XML documents in Stream, SAX, (DOM, SAX, StAX), XSLT, XML Schema validation, and XPath operations. StAX, or DOM mode against an XML schema document. Like the Intel Full source code ships with the XML Benchmark Tool to facilitate XML Parsing Accelerator, the Intel XML Schema Accelerator achieves extensibility and to allow users to write their own drivers to test significant performance gains from using Intel SSE4.2 instructions, other XML processing engines, modify workloads, and better as demonstrated in this paper. understand the test methodology. To learn more about the XML • Intel® XSLT Accelerator—transforms XML documents into Benchmark Tool and to download your free copy, please visit other forms. Extensible Stylesheet Language Transformation www.intel.com/software/xmlbenchmarktool. (XSLT) is used to build other types of machine- or human-readable The Intel XML Software Suite facilitates efficient solution development documents from XML. While neither XSLT nor XPath benefits and excellent performance, extensibility, and standards compliance directly from Intel SSE4.2, they nevertheless receive a performance in either Java or C++ for Windows and Linux, and Java on HP-UX* (for benefit indirectly because of the parsing performance benefit Itanium® processors). The relationship between the suite’s components from Intel SSE4.2 instructions under the Intel XML Software Suite, and the rest of the application environment is shown in Figure 1. since parsing is an integral step before these operations can occur. The Intel XSLT Accelerator can be applied to a full range of XML To facilitate efficient development of Java server or client solutions, documents such as a tree (the DOM tree model) or a series of the Intel XML Software Suite uses the standard Java API for XML events (the SAX or StAX models). It supports common operations, Processing (JAXP*) , which enables high compatibility with existing math computations, string manipulations, set handling, and date- solutions, as well as a simple and familiar means of supporting new and-time functions,1 as well as allows developers to access Java development. Interaction between the JAXP interface and the XML class functions. processing components of the suite is facilitated by a thin Java Native Interface (JNI*) layer. 6 White Paper: Intel® XML Software Suite

This Java solution architecture provides high performance and solution compatibility relative to other solutions by processing input Applications XML data in the native core. It uses native memory pools to improve the consumption of system memory, which adds further to the Input Output performance of the overall solution by making memory access less fragmented, creating efficient libraries for XML runtime processing C++ or Java* API in Java environments.

For C/C++ solutions, the Intel XML Software Suite utilizes an easy- to-use C++ API that interfaces with the XML core and communicates with the XML-processing components provided in the suite. This flexible and powerful set of C++ XML functions provides a simple and efficient Intel® XML Intel® Intel® XML Intel® Parsing XPath Schema XSLT way to incorporate the Intel XML Software Suite seamlessly into Accelerator Accelerator Accelerator Accelerator existing C/C++ solutions, as well as to create or customize new ones.

To deliver high performance, the Intel XML Software Suite performs XML processing in the XML core. The design uses an efficient XML Core internal document format for high-speed, internal cross-function communication, which allows for processing large XML files. This Intel® XML Software Suite approach further enhances performance for applications and environments that require complex XML processing; features and Figure 1. The relationship between applications and Intel® XML benefits are summarized in Table 3. Software Suite.

Feature Benefit

The Intel® XML Software Suite has a high degree of XML conformance for reliable and predictable application behavior, High XML Conformance with a 98% pass rate or higher for the W3C* and OASIS* XML Conformance Test Suites. It conforms to the W3C standards for XML functionality, helping to ensure interoperability with applications that follow W3C standards.

The product’s flexible document format support facilitates simple integration with a wide variety of solutions; it supports XML input and output data formatted for XML processing as follows:

Document Format Support • Data Streams: Sequential unbounded XML text format • DOM (Document Object Model): Tree and node structures data format • SAX (Simple API for XML): Event-driven format • StAX (Streaming API for XML): Demand-driven format

Stability Across Because most processing is performed in the XML core, the processing time spent in the Java* layer is relatively small. Different JVMs* Therefore, JVM overhead has minimal impact on overall XML processing performance.

Character sets commonly used with XML documents and processing are supported, for further flexibility. These include Robust Character UTF-8, UTF-16, ISO 8859 series, ASCII, and others. Documents can be based on character encoding, identified by external Encoding Support metadata HTTP headers or internal metadata, a byte-order mark, or encoding declarations.

Support for handling XML files larger than 1 GB facilitates application scalability and reliability with Large XML File Processing sustained throughput.

Extensive QA testing helps create a stable and reliable platform for XML solutions, tailoring the Intel XML Software Suite High Availability for applications that demand heavy XML processing and high availability. Workload testing includes successful completion without failure or performance degradation of over 100 consecutive hours of stress testing at 100% CPU utilization.

Hardware Platform The Intel XML Software Suite is thread-safe,2 supporting multi-threaded applications and taking advantage of new Intel® Optimization Core™ i7 processor features, such as Intel® SSE4.2 for optimal performance and energy efficiency.

Table 3. Features and benefits of Intel® XML Software Suite.

7 White Paper: Intel® XML Software Suite

Accelerate XML Parsing Without Building turn can account for up to 50 percent of an entire application. Intel’s Anything New approach to optimizing character checking was to use the equal any Because of its central role in making data available to business operation to distinguish the different types of XML entities indicated solutions, XML parsing is an important aspect of those solutions, by explicit markup, and then to use the ranges operation to help and parsing performance is a significant contributor to overall check whether they locate in their corresponding encoding area. performance. Intel SSE4.2 string and text processing instructions Parsing throughput is increased through a combination of exploiting are one important means of increasing XML parsing performance. data parallelism and eliminating what is often implemented as a long To make the advantages of these instructions readily available, sequence of branches or table lookups. Intel has incorporated them into the Intel XML Parsing Accelerator, a To test the results of this optimization, Intel tested XML parsing component of the Intel XML Software Suite. By taking advantage of operations on a single test system, with and without the Intel XML this pre-built functionality, solution providers automatically obtain the Software Suite’s use of Intel SSE4.2 functionality. The speedups advantages of Intel SSE4.2. achieved by enabling Intel SSE4.2 were approximately 25 percent and Laboratory testing has suggested that the character-checking 10 percent, respectively, on C++ and Java SAX parsing operations. Those process, which consists of reading bytes and checking whether each results with varying numbers of threads are summarized in Figures 2 is legal for its corresponding entity type, can occupy as much as 60 and 3, demonstrating that XML parsing performance improvements are 3 percent of the CPU cycles consumed by the parsing process, which in available to solution providers without additional optimization effort.

Intel® C++ SAX Parser Throughput (in Mbyte/s) 2000 1800 1.24x Without SSE4.2 1600 With SSE4.2 1400 1200 1000 1.25x 800 600 1.24x 400 1.26x 200 0 1 thread 2 threads 4 threads 8 threads

Figure 2. Speedup of C++ SAX parser performance.3

Intel® Java SAX Parser Throughput (in Mbyte/s) 800 Without SSE4.2 700 1.10x With SSE4.2

600

500

400 1.09x 300

200 1.11x 1.11x 100

0 1 thread 2 threads 4 threads 8 threads

Figure 3. Speedup of Java SAX parser performance.3

8 White Paper: Intel® XML Software Suite

Implement Pre-Optimized Components for Faster The parallel trie approach employed by the Intel XML Schema XML Schema Validation Accelerator, which is illustrated in Figure 5, solves the three problems XML Schema validation is another aspect of XML processing that can noted above: present significant opportunities for performance optimization using • Instead of a large sparse array, each trie is organized as a Intel SSE4.2. This functionality reads an XML document and compares compact string. its contents against a pre-existing XML Schema to verify the legality • Instead of having each successive character slot require its own of its structure and data types. XML Schema validation involves the trie, two characters at a time are combined into a single two-byte lookup of strings from the XML Schema, which are typically stored element (as discussed in this paper, Intel SSE4.2 can operate on in the form of hash tables or a sorted list; this operation can be a two-byte characters). significant source of performance bottlenecks. • The equal any operation is used to operate on many characters in parallel. Similar to the parsing operations described above, XML Schema validation is a good opportunity to improve performance through The result is greater parallelism, lower memory consumption, parallelization using Intel SSE4.2 string and text processing and fewer memory accesses. instructions. To make the most of this opportunity, the Intel XML Schema Accelerator uses a novel parallel trie data structure that reduces memory consumption and increases the efficiency of string Da Do Ga Kn La Ot lookup. (The term “trie” comes from “retrieval” and is pronounced either like “tree” or like “try.”)

Conventionally, each trie layer is represented as a simple array made Data Game Other Document up of 256 elements—one for each possible ASCII character, as shown Knowledge Language in Figure 4. Each entry points either to another trie layer for the

next character in the string or to a list of strings that match the Figure 5. Parallel trie: Each layer is a compact string; two adjacent path through the trie layers traversed so far. This implementation bytes are one two-byte word. is relatively inefficient: Similar to the testing of parsing functionality described above, Intel • The arrays are sparsely populated with pointers tested this optimization by measuring schema validation results on a • Each successive character slot in a string requires its own trie single test system, with and without the Intel XML Software Suite’s use of Intel SSE4.2 functionality. The speedups achieved by using Intel • There is a separate lookup for each character of the string SSE4.2 were approximately 30 percent and 25 percent, respectively, Taking this approach can slow down XML Schema validation as a whole. on C++ and Java SAX schema-validation operations. Those results with varying numbers of threads are summarized in Figures 6 and 7, demonstrating again that performance improvements are available to … D G K L O … solution providers without additional optimization effort.3

Game Knowledge Language Other a o …

Data Document

Figure 4. Original trie: Each layer has a slot per possible ASCII character, and each entry points to either the TRIE for the next character or a list of matching strings.

9 White Paper: Intel® XML Software Suite

Intel® C++ SAX Validator Throughput (in Mbyte/s) 1000 1.37x 900 Without SSE4.2 800 With SSE4.2 700 600

500 1.27x 400 300 1.29x 200 1.33x 100 0 1 thread 2 threads 4 threads 8 threads

Figure 6. Speedup of C++ XML Schema validation performance.3

Intel® Java SAX Validator Throughput (in Mbyte/s)

800 1.25x 700 Without SSE4.2 With SSE4.2 600

500 1.26x 400

300 1.25x 200 1.27x 100

0 1 thread 2 threads 4 threads 8 threads

Figure 7. Speedup of Java* XML Schema validation performance.3

10 White Paper: Intel® XML Software Suite

Conclusion Additional Resources

As the continuing need to do more with less drives IT organizations to The following materials can get you started learning more about explore areas such as SOA, SaaS, Web 2.0, and enterprise applications, XML-related technologies from Intel: XML processing becomes more important in the enterprise. XML • The Intel® XML Software Suite product page provides detailed software solutions need to take full advantage of customer hardware, features and benefits of the product, as well as links to additional and providers need to create that software quickly and at low cost. information and the full set of user guides and other documentation They need to be able to bring these solutions to market quickly to (www.intel.com/software/xmlsoftwaresuite). optimize competitiveness, and they rely on a strong foundation of XML processing components for their success. Likewise, their • The Intel® Software Network XML User Forum is a customers need solutions that not only increase agility and flexibility, community of support around XML solutions, where you can ask but also take maximum advantage of their current and future experts and peers questions to meet the challenges and demands hardware infrastructure. of high performance XML processing (softwarecommunity.intel.com/ isn/Community/en-US/forums/2504/ShowForum.aspx). The Intel XML Software Suite delivers these advantages to solution providers and their customers alike. With robust support for new Intel • The Intel® 64 and IA-32 Architectures Software Developer’s Core i7 processor features, such as Intel SSE4.2, solutions get a head Manual, Volume 2A and 2B, explains the features, capabilities, start on being ready for future platforms, while retaining compatibility and implementation of SSE4 instructions, including the SSE4.2 with current systems. With high standards compliance and drop-in instruction set (developer.intel.com/products/processor/manuals). compatibility, the Intel XML Software Suite provides the means for XML solutions to easily take advantage of new performance advantages, along with ease of use by developers and lower total cost of ownership for everyone concerned.

11 Buy a copy of the Intel XML Software Suite or download an evaluation copy from www.intel.com/software/xmlsoftwaresuite

1 Some of these functions are based on the XSLT 1.0 specifications and others are an extension to XSLT, such as EXSLT. 2 See the user guides at softwarecommunity.intel.com/articles/eng/3891.htm for details. 3 Internal Intel measurements. Note that performance was measured using pre-production CPUs (Nehalem-EP B0), so the performance on the eventual product may vary from the measurements reported in this paper. The test hardware was configured as follows—Chassis: Supermicro* 8252U Rackmount Chassis; Processor: 2x Nehalem-EP B0 – 2.4 95w 5.86 QPI 1066 Turbo – QDF:QGXW or 2.4 80w 5.86 QPI 1066 Turbo – QDF:QGYA; Memory: 6x1GB 1066 DDR3 RDIMMs; Hard Drive: 1x500GB SATA 7200RPM; Baseboard: Supermicro X8DTN+. The operating system used was Red Hat Enterprise Linux* AS 4.0 Kernel: 2.6.9-42.ELsmp IA32. The JVM used was SUN JDK 1.6 Update 2 with the following JVM options selected: -server -Xmx1g -Xms1g.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WAR- RANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products, visit Intel Performance Benchmark Limitations at www.intel.com/performance/resources/benchmark_limitations.htm. This paper is for informational purposes only. THIS DOCUMENT IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. Intel, Intel logo, Intel Core, and Itanium are trademarks or registered trademarks of Intel Corporation in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2008 Intel Corporation. All rights reserved. Printed in USA 1108/LC/MESH/KIN/200 Please Recycle 320949-001US