Barramento PCI
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Barramento PCI PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Mon, 29 Apr 2013 11:40:35 UTC Contents Articles Conventional PCI 1 PCI-X 25 PCI Express 29 References Article Sources and Contributors 46 Image Sources, Licenses and Contributors 47 Article Licenses License 48 Conventional PCI 1 Conventional PCI Conventional PCI PCI Local Bus Three 5-volt 32-bit PCI expansion slots on a motherboard (PC bracket on left side) Year created July 1993 Created by Intel Supersedes ISA, EISA, MCA, VLB Superseded by PCI Express (2004) Width in bits 32 or 64 Capacity 133 MB/s (32-bit at 33 MHz--the standard configuration) 266 MB/s (32-bit at 66 MHz or 64-bit at 33 MHz) 533 MB/s (64-bit at 66 MHz) Style Parallel Hotplugging interface Optional Conventional PCI (PCI is an initialism formed from Peripheral Component Interconnect,[1] part of the PCI Local Bus standard and often shortened to just PCI) is a local computer bus for attaching hardware devices in a computer. The PCI bus supports the functions found on a processor bus, but in a standardized format that is independent of any particular processor. Devices connected to the bus appear to the processor to be connected directly to the processor bus, and are assigned addresses in the processor's address space.[2] Attached devices can take either the form of an integrated circuit fitted onto the motherboard itself, called a planar device in the PCI specification, or an expansion card that fits into a slot. The PCI Local Bus was first implemented in IBM PC compatibles, where it displaced the combination of ISA plus one VESA Local Bus as the bus configuration. It has subsequently been adopted for other computer types. PCI and PCI-X are being replaced by PCI Express,[citation needed] but as of 2011[3], most motherboards are still made with one or more PCI slots, which are sufficient for many uses. The PCI specification covers the physical size of the bus (including the size and spacing of the circuit board edge electrical contacts), electrical characteristics, bus timing, and protocols. The specification can be purchased from the PCI Special Interest Group (PCI-SIG). Typical PCI cards used in PCs include: network cards, sound cards, modems, extra ports such as USB or serial, TV tuner cards and disk controllers. PCI video cards replaced ISA and VESA cards, until growing bandwidth requirements outgrew the capabilities of PCI; the preferred interface for video cards became AGP, and then PCI Express. PCI video cards remain available for use with old PCs without AGP or PCI Express slots.[4] Many devices previously provided on PCI expansion cards are now commonly integrated onto motherboards or available in universal serial bus and PCI Express versions. Conventional PCI 2 History Work on PCI began at Intel's Architecture Development Lab circa 1990. A team of Intel engineers (composed primarily of ADL engineers) defined the architecture and developed a proof of concept chipset and platform (Saturn) partnering with teams in the company's desktop PC systems and core logic product organizations. The original PCI architecture team included, among others, Dave Carson, Norm Rasmussen, Brad Hosler, Ed Solari, Bruce Young, Gary Solomon, Ali Oztaskin, Tom Sakoda, Rich Haslam, Jeff Rabe, and Steve Fischer. PCI (Peripheral Component Interconnect) was immediately put to A typical 32-bit, 5 V-only PCI card, in this case, a use in servers, replacing MCA and EISA as the server expansion SCSI adapter from Adaptec. bus of choice. In mainstream PCs, PCI was slower to replace VESA Local Bus (VLB), and did not gain significant market penetration until late 1994 in second-generation Pentium PCs. By 1996, VLB was all but extinct, and manufacturers had adopted PCI even for 486 computers.[5] EISA continued to be used alongside PCI through 2000. Apple Computer adopted PCI for professional Power Macintosh computers (replacing NuBus) in mid-1995, and the consumer Performa product line (replacing LC PDS) in mid-1996. Later revisions of PCI added new features and performance A motherboard with two 32-bit PCI slots and two improvements, including a 66 MHz 3.3 V standard and 133 MHz sizes of PCI Express slots PCI-X, and the adaptation of PCI signaling to other form factors. Both PCI-X 1.0b and PCI-X 2.0 are backward compatible with some PCI standards. The PCI-SIG introduced the serial PCI Express in 2004. At the same time, they renamed PCI as Conventional PCI. Since then, motherboard manufacturers have included progressively fewer Conventional PCI slots in favor of the new standard. PCI History[6] [7] Spec Year Change Summary PCI 1.0 1992 Original issue PCI 2.0 1993 Incorporated connector and add-in card specification PCI 2.1 1995 Incorporated clarifications and added 66 MHz chapter PCI 2.2 1998 Incorporated ECNs, and improved readability PCI 2.3 2002 Incorporated ECNs, errata, and deleted 5 volt only keyed add-in cards PCI 3.0 2002 Removed support for the 5.0 volt keyed system board connector Conventional PCI 3 Auto configuration PCI provides separate memory and I/O port address spaces for the x86 processor family, 64 and 32 bits, respectively. Addresses in these address spaces are assigned by software. A third address space, called the PCI Configuration Space, which uses a fixed addressing scheme, allows software to determine the amount of memory and I/O address space needed by each device. Each device can request up to six areas of memory space or I/O port space via its configuration space registers. In a typical system, the firmware (or operating system) queries all PCI buses at startup time (via PCI Configuration Space) to find out what devices are present and what system resources (memory space, I/O space, interrupt lines, etc.) each needs. It then allocates the resources and tells each device what its allocation is. The PCI configuration space also contains a small amount of device type information, which helps an operating system choose device drivers for it, or at least to have a dialogue with a user about the system configuration. Devices may have an on-board ROM containing executable code for x86 or PA-RISC processors, an Open Firmware driver, or an EFI driver. These are typically necessary for devices used during system startup, before device drivers are loaded by the operating system. In addition, there are PCI Latency Timers that are a mechanism for PCI Bus-Mastering devices to share the PCI bus fairly. "Fair" in this case means that devices will not use such a large portion of the available PCI bus bandwidth that other devices are not able to get needed work done. Note, this does not apply to PCI Express. How this works is that each PCI device that can operate in bus-master mode is required to implement a timer, called the Latency Timer, that limits the time that device can hold the PCI bus. The timer starts when the device gains bus ownership, and counts down at the rate of the PCI clock. When the counter reaches zero, the device is required to release the bus. If no other devices are waiting for bus ownership, it may simply grab the bus again and transfer more data.[8] Interrupts Devices are required to follow a protocol so that the interrupt lines can be shared. The PCI bus includes four interrupt lines, all of which are available to each device. However, they are not wired in parallel as are the other PCI bus lines. The positions of the interrupt lines rotate between slots, so what appears to one device as the INTA# line is INTB# to the next and INTC# to the one after that. Single-function devices use their INTA# for interrupt signaling, so the device load is spread fairly evenly across the four available interrupt lines. This alleviates a common problem with sharing interrupts. PCI bridges (between two PCI buses) map the four interrupt traces on each of their sides in varying ways. Some bridges use a fixed mapping, and in others it is configurable. In the general case, software cannot determine which interrupt line a device's INTA# pin is connected to across a bridge. The mapping of PCI interrupt lines onto system interrupt lines, through the PCI host bridge, is similarly implementation-dependent. The result is that it can be impossible to determine how a PCI device's interrupts will appear to software. Platform-specific BIOS code is meant to know this, and set a field in each device's configuration space indicating which IRQ it is connected to, but this process is unreliable. PCI interrupt lines are level-triggered. This was chosen over edge-triggering in order to gain an advantage when servicing a shared interrupt line, and for robustness: edge triggered interrupts are easy to miss. Later revisions of the PCI specification add support for message-signaled interrupts. In this system, a device signals its need for service by performing a memory write, rather than by asserting a dedicated line. This alleviates the problem of scarcity of interrupt lines. Even if interrupt vectors are still shared, it does not suffer the sharing problems of level-triggered interrupts. It also resolves the routing problem, because the memory write is not unpredictably modified between device and host. Finally, because the message signaling is in-band, it resolves some synchronization problems that can occur with posted writes and out-of-band interrupt lines. Conventional PCI 4 PCI Express does not have physical interrupt lines at all.