Portland State University PDXScholar Dissertations and Theses Dissertations and Theses 10-27-1994 High Level Preprocessor of a VHDL-based Design System Karthikeyan Palanisamy Portland State University Follow this and additional works at: https://pdxscholar.library.pdx.edu/open_access_etds Part of the Electrical and Computer Engineering Commons Let us know how access to this document benefits ou.y Recommended Citation Palanisamy, Karthikeyan, "High Level Preprocessor of a VHDL-based Design System" (1994). Dissertations and Theses. Paper 4776. https://doi.org/10.15760/etd.6660 This Thesis is brought to you for free and open access. It has been accepted for inclusion in Dissertations and Theses by an authorized administrator of PDXScholar. Please contact us if we can make this document more accessible:
[email protected]. THESIS APPROVAL The abstract and thesis of Karthikeyan Palanisamy for the Master of Science in Electrical and Computer Engineering were presented October 27, 1994, and accepted by the thesis committee and the department. COMMITfEE APPROVALS: Marek A. /erkowski, Chair 1, Bradford R. Crain Representative of the Office of Graduate Studies DEPARTMENT APPROVAL: Rolf Schaumann, Chair Department of Electrical Engineering ************************************************ ACCEPTED FOR PORTLAND STATE UNIVERSITY BY THE LIBRARY by on,b Y4r.£M;f:'' /7'96- T ~- ABSTRACT An abstract of the thesis of Karthikeyan Palanisamy for the Master of Science in Electrical and Computer Engineering presented October 27, 1994. Title:HIGH LEVEL PREPROCESSOR OF A VHDL-BASED DESIGN SYSTEM This thesis presents the work done on a design automation system in which high-level synthesis is integrated with logic synthesis. DIADESfa design automa tion system developed at PSU, starts the synthesis process from a language called ADL.