ECEN 629 – Winter 2018 1 of 2 Exercise 1 – Placement & Routing using VPR

Exercise 1 – Placement & Routing using VPR ECEN 629 – Winter 2018 Due Date: Friday, March 16, 2018 11:59pm

This exercise is developed by Professor Jason Anderson (University of Toronto). I have modified it slightly for our class.

The purpose of this exercise is two-fold: 1) to use an automatic placement tool based on the simulated annealing optimization strategy, and to gain some familiarity with the properties of that strategy; and, 2) to experiment with the negotiated congestion routing algorithm described in class. The placement and routing (P&R) tool you will use in this exercise is called “VPR”’. It is a tool originally created at the University of Toronto by Prof. Vaughn Betz as part of his Ph.D research in the late 90s. It has been enhanced extensively since then by other graduate students, most recently by Dr. Jason Luu and Kevin Murray. As well as being a P&R tool, VPR is a framework for FPGA CAD and architectural research, used by researchers all around the world. VPR takes a text description of the target FPGA architecture as input. The description specifies, among other things, the make-up of the FPGA logic blocks, the routing segment lengths, the switch block style, and the routing delays. By changing the architecture description file, one can evaluate the speed and area-efficiency of different FPGAs. VPR is part of a larger FPGA CAD toolsuite called VTR (Verilog-to-Routing), which, besides placement and routing with VTR, includes RTL synthesis, logic optimization and technology mapping.

Downloading the software

Download and extract the ex1 files.zip archive from the course website. Within these files is the VTR version 7 source code (vtr release 7.0 full.tar.gz). Unzip the archive. In the vpr subdirectory Makefile, change: ENABLE GRAPHICS = true. Go up one directory to the top-level directory of the VTR distribution, and type: make vpr. A binary executable, vpr/vpr will be produced. I have verified this works on my Ubuntu 16.04 machine.

Instruction Manual for VPR

In the vpr sub-directory, youll see a .pdf user manual for VPR.

Netlist Files and Architecture File to Use

Use the architecture file k6 frac N10 mem32K 40nm.xml. You may find reading the architecture file interest- ing, as it gives a description of an FPGA architecture. Take a look at the top of the file. The architecture file describes an FPGA with ten 6-input LUTs per logic block, columns of RAM and columns of multipliers. The routing segments span 4 logic-block tiles. The benchmarks to use for this exercise are also include in the file archive: alu4.blif, diffeq1.blif, ex4p.blif and sha.blif. Unlike in the other course assignments, which used synthetic circuits, these are real circuits. Exercise A - Placement and Simulated Annealing The VPR program allows the user to set various Simulated Annealing parameters: the starting temperature, the ending temperature, the rate at which the temperature decreases, the number of moves per temperature, and the initial random seed. NOTE: For all steps in Exercise A, run VPR with the following parameters: --place (prevent routing) and --place algorithm bounding box (minimize HPWL only).

Updated: March 5, 2018 Author: Prof. Jeffrey Goeders (BYU Dept. of Elec. and Comp. Eng.) ECEN 629 – Winter 2018 2 of 2 Exercise 1 – Placement & Routing using VPR

1. Run the vpr program once, with its default parameters, on four circuit netlists. Plot the score (cost function) versus the temperature. If you turn on the “toggle nets” option, you can see the rats nest of wires become less tangled. Note: to avoid the graphics display, use the --nodisp option. 2. Run VPR 5 times for each circuit with different random seeds. Calculate and report the mean and standard deviation of the resulting final scores. Comment on the sensitivity of the scores to the random seeds? Do all circuits exhibit the same sensitivity to the random seed? 3. For each circuit, run VPR 5 times (with different seeds) with 5 different starting temperatures (25 * 4 circuits = 100 runs in total). Be sure to choose some starting temperatures that are low enough to actually impact the placement results (HINT: you may need to use starting temperatures considerably less than 1!). For each circuit, report the mean and standard deviation of the final score for each starting temperature. 4. In vpr/SRC/place/place.c, find the assess swap() function to see the code that determines if a move should be accepted or rejected. You will see the function call to exp(-delta c/t) that we discussed in class. Hack this function to disable hill climbling in the placer. Repeat step #2 above with the new acceptance function. Report the mean and standard deviation of the resulting scores. Discuss quality differences observed versus the results for #2 above. 5. On top of your changes in #4, find the try swap() function in the same file. VPR implements range limits for move distances, as discussed in class. This is done through the rlim parameter passed into the try swap() function. Hack the code to disable range limiting i.e., moves anywhere on the die are always permitted. Repeat step #2 above. Report the mean and standard deviation of the resulting scores. Discuss quality differences observed versus the results for #2 and #4 above. Exercise B - Timing-Driven Routing Note: For this part of the Exercise, please use the original place.c for VPR and not the new one you hacked up in Part A. 1. VPR also implements timing-driven routing using an improved version of the PathFinder approach described in class. Run the placement tool with the default options and the timing-driven router. Report the post-routing critical path delay and the router run-time (see VPR output). NOTE: Do not set --place or --place algorithm for Exercise B. Set the #tracks/channel (W) to 40 using --route chan width 40 for alu4, set W to 60 for diffeq1, set W to 50 for ex4p, and set W to 60 for sha. 2. Using the same parameters as in the previous step, explore the different parameters of the router and try to improve the critical path delay for the four circuits. Comment on the parameters you experimented with and their effect on the critical path delay. Be sure to vary the “present congestion” (--pres fac mult) and “historical congestion” (--acc fac) parameters talked about in class. 3. VPR implements A* routing. In 2-3 sentences, describe what this is. Disable A* routing using the using --astar fac 0 on the VPR command line. Repeat step #1. Comment on how router run-time and quality is affected by disabling A* routing. Submission Send your report to [email protected] with the subject: 629 Excercise 1

Updated: March 5, 2018 Author: Prof. Jeffrey Goeders (BYU Dept. of Elec. and Comp. Eng.)