DOCSLIB.ORG

Using MDA to Automate the Integration of Virtual Platforms for System-Level Simulation

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Using MDA to Automate the Integration of Virtual Platforms for System-Level Simulation Using MDA to Automate the Integration of Virtual Platforms for System-Level Simulation David Perillo Marco Di Natale Elettronica SpA, Roma Scuola Superiore S. Anna, Pisa Email: [email protected] Email: [email protected] Abstract—This paper presents the work performed at and virtual platforms supported by an eclipse-based frame- (removed for blind review) to automate the integration work. The framework includes the Papyrus modeller to of virtual systems development (VSD) and simulation describe the system, its interfaces and components ac- in its embedded software development process. The approach is based on a combination of meta- tivation rules in SysML, following the Platform Based models, model transformations and design patterns, Design (PBD) approach. A generation chain, integrated the SysML standard and the use of the open source in the framework and based on the Acceleo open toolset, Eclipse framework. The purpose is to derive all the synthetizes hardware-software interfaces and glue code design refinements, including the production code and implementing virtual hardware elements on top of the the code used for simulation and verification from a SIMICS full system simulator. single set of SysML models. Stereotypes and model transformations are defined The main contribution of the proposed methodology is to allow the integration of automatically generated to derive the design refinements and the configuration of interfaces and manually produced code implementing the virtual platform from a single set of SysML models, virtual platforms for the simulation of HW/SW hetero- representing the system at a higher level of abstraction. geneous systems on the SIMICS platform. The production code and the code used for simulation I. Introduction and verification are derived from these models together Embedded software runs in a tight interaction with with the hardware documentation. The single source of the hardware, often codesigned or codeveloped. When the information guarantees the alignment of interfaces. complexity of the system grows, the difficulty to inves- The SysML models make use of purposely developed tigate malfunctionings and errors increases. Hardware- profiles and stereotypes containing concepts related to the software interactions provide some of the most critical representation of low-level details of interface to firmware challenges in the verification process since they may be (FPGA) components, functional and mapping elements the source of two types of errors: misalignment between that are not directly available in the standard SysML or components interfaces, and components interoperability in the Marte [15] profile. and behavioral interaction errors. II. Background and State Of the Art The traditional debugging approach is to run the em- Our framework is based on a customized profile realized bedded software on the target hardware to perform the on top of SysML, code generation templates and the use test cases and collect traces to identify errors in the source of the SIMICS simulator and provides support for the code. This strategy is inefficient: it occurs late; it requires following activities: several iterations before the bug is fixed; and it keeps the target hardware busy for a long time just to solve • System Modelling, concerning the use of (semi)formal clerical errors in the code. Most of the times the target languages to describe systems at different levels of hardware is not dedicated to only one software team or granularity. is physically not available because it has not been yet • System-Level Synthesis, consisting in a framework for realized. In addition, hardware-software interaction errors the automatic generation of software and firmware are typically very difficult to discover and replicate. components. The use of virtual platforms (VPs) allows testing and • Hardware/Software cosimulation, by means of Virtual verification long before the hardware is available; gives Platforms (VPs). the possibility to run complex tests, inject faults and In the Platform-based design (PBD) methodology func- test the software in conjunction with multiple hardware tional elements are put in correspondence with platform configurations. These considerations make the use of VPs a elements through a mapping model, defining allocation critical tool for developing and debugging the interactions rules and implementation (refinement) constraints. The of the software with the hardware layer, the HW/SW Metropolis design environment for Heterogeneous Systems partitioning and the analysis of the interfaces. uses the Platform-based design methodology [17] for the We defined a design, implementation and verification representation, analysis, and synthesis of systems repre- methodology based on SysML models, code generators, sented in SystemC. Metropolis supports several compu- tation models (MOC) by refinement on an underlying ilarly to VHDL and Verilog, the library comes with a generic metamodel [13]. Ptolemy is an environment for simulation kernel that allows both Loosely-Timed (LT) modelling and simulating heterogeneous systems. Ptolemy and Approximately-Timed (AT) coding styles depending [14] is mostly targeted at simulation. Code generation of on the required timing accuracy and simulation speed. implementations is supported only for the Java language. An intermediate solution is the software-timed accuracy PBD System models can also be described using the (ST), implemented in the WindRiver Simics simulator [3], SysML modelling standard [23], which extends UML to which is in essence event-based simulation. Events (such provide a language for Systems Engineering specification, as for instance a read operation from a memory register) analysis, design, verification, and validation. The Marte are handled by the simulation kernel and result in the profile extends UML and SysML to provide standard execution of a simulated behavior. stereotypes specific for the embedded systems domain. Several solutions and commercial tools are available to The Complex framework [6] enables HW/SW co-design support the creation of Virtual Platforms (VPs), capable and Design-Space Exploration (DSE) of embedded so- of executing the same binary software as the physical hard- lutions with a platform based design approach. It is ware being simulated. Instruction Set Simulation tools based on UML/MARTE models describing SW and HW (ISS) allow to execute the binary software unmodified, components and Use case diagrams. M2T generation fa- including a full Operating System stack. Differently from cilities convert UML models into IP-Xact specifications cycle-accurate (CAS), phase-accurate (PAS) and timing- and SystemC code implementing the simulation platform. accurate (TAS) simulators, which can emulate the proces- A simulation monitor supports the design exploration sor at the physical signal level [11], ISS cannot simulate process by providing numerical estimates of WCETs and superscalar ordering effects [2]. SystemC-TLM implemen- power consumptions. The Complex framework enables fast tations of Instruction Set Simulators (ISS) are also avail- DSE iterations deriving the design refinements from UML able. QEMU [16] is an Open Source ISS emulating a large and Simulink models but requires significant SystemC number of microprocessor and devices. New devices can be programming for increasing the accuracy of HW models. modelled in C code using QDev and connected in a device The SPRIT consortium formalized the IP-XACT speci- tree in which devices are recursively connected via busses. fication of IP component interfaces through an XSD meta- Direct connection between devices is not possible. QBox model. SPRIT can be used to model hardware-software and TLMu integrate a SystemC bridge on QEMU ISS, interfaces but lacks low-level details like dual page memory enabling the possibility to increase the timing accuracy. banks and default register values. OVPSim (Open Virtual Platform Simulator) is another Manually editing IP-XACT XML models is complex, open solution available only for ARM processors. Simics error prone and time consuming. The Kactus2 framework provides a large set of processors and integrated devices [7] extends IP-XACT to support SW and HW mapping. plus a model builder tool for creating models of IP cores The tool provides export facilities to ModelSim; Altera using the DML device modelling language. Quartus and Verilog. The need to express timing require- Our workflow is based on the Model Driven Architecture ments and to integrate IP-XACT specification in Papyrus (MDA) OMG standard, enabling the user to describe is addressed in [8], providing a partial UML/MARTE rep- complex application logics with a formal semantic, in- resentation of IP-XACT. The elements in our UML profile dependently from the specific execution platform. OMG provides concepts not directly available in IP-XACT or has defined the standard specifications for transformation MARTE, and OCL constraints to validate models. languages: model-to-text, as described in MOFM2T [19] An example of System-Level Synthesis is the IP-based and model-to-model, as described in MOF/QVT [20]. design methodology providing automatic generation of Transformation languages are based on the OCL syntax HW/SW interface components[12]. Plaintext files, Excel [18] to constraint expressions on UML models. We decided sheets, custom XML formats, IP-XACT specifications, to implement profiles and transformations on the Eclipse and SystemRDL code can be used to describe hardware- platform [22] because it provides an open implementation software interfaces
Load more

Recommended publications
  • Wind River Vxworks Platforms 3.8
    Wind River VxWorks Platforms 3.8 The market for secure, intelligent, Table of Contents Build System ................................ 24 connected devices is constantly expand- Command-Line Project Platforms Available in ing. Embedded devices are becoming and Build System .......................... 24 VxWorks Edition .................................2 more complex to meet market demands. Workbench Debugger .................. 24 New in VxWorks Platforms 3.8 ............2 Internet connectivity allows new levels of VxWorks Simulator ....................... 24 remote management but also calls for VxWorks Platforms Features ...............3 Workbench VxWorks Source increased levels of security. VxWorks Real-Time Operating Build Configuration ...................... 25 System ...........................................3 More powerful processors are being VxWorks 6.x Kernel Compatibility .............................3 considered to drive intelligence and Configurator ................................. 25 higher functionality into devices. Because State-of-the-Art Memory Host Shell ..................................... 25 Protection ..................................3 real-time and performance requirements Kernel Shell .................................. 25 are nonnegotiable, manufacturers are VxBus Framework ......................4 Run-Time Analysis Tools ............... 26 cautious about incorporating new Core Dump File Generation technologies into proven systems. To and Analysis ...............................4 System Viewer ........................
    [Show full text]
  • Simics* Model Library for Eagle Stream Simulation Environment
    Simics* Model Library for Eagle Stream Simulation Environment Release Notes May 2020 Revision V0.6.00 Intel Confidential Notice: This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Learn more at intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.
    [Show full text]
  • Intel Quartus Prime Pro Edition User Guide: Programmer Send Feedback
    Intel® Quartus® Prime Pro Edition User Guide Programmer Updated for Intel® Quartus® Prime Design Suite: 21.2 Subscribe UG-20134 | 2021.07.21 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Intel® Quartus® Prime Programmer User Guide..............................................................4 1.1. Generating Primary Device Programming Files........................................................... 5 1.2. Generating Secondary Programming Files................................................................. 6 1.2.1. Generating Secondary Programming Files (Programming File Generator)........... 7 1.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box)............................................................................................. 11 1.3. Enabling Bitstream Security for Intel Stratix 10 Devices............................................ 18 1.3.1. Enabling Bitstream Authentication (Programming File Generator)................... 19 1.3.2. Specifying Additional Physical Security Settings (Programming File Generator).............................................................................................. 21 1.3.3. Enabling Bitstream Encryption (Programming File Generator).........................22 1.4. Enabling Bitstream Encryption or Compression for Intel Arria 10 and Intel Cyclone 10 GX Devices.................................................................................................. 23 1.5. Generating Programming Files for Partial Reconfiguration.........................................
    [Show full text]
  • A Superscalar Out-Of-Order X86 Soft Processor for FPGA
    A Superscalar Out-of-Order x86 Soft Processor for FPGA Henry Wong University of Toronto, Intel [email protected] June 5, 2019 Stanford University EE380 1 Hi! ● CPU architect, Intel Hillsboro ● Ph.D., University of Toronto ● Today: x86 OoO processor for FPGA (Ph.D. work) – Motivation – High-level design and results – Microarchitecture details and some circuits 2 FPGA: Field-Programmable Gate Array ● Is a digital circuit (logic gates and wires) ● Is field-programmable (at power-on, not in the fab) ● Pre-fab everything you’ll ever need – 20x area, 20x delay cost – Circuit building blocks are somewhat bigger than logic gates 6-LUT6-LUT 6-LUT6-LUT 3 6-LUT 6-LUT FPGA: Field-Programmable Gate Array ● Is a digital circuit (logic gates and wires) ● Is field-programmable (at power-on, not in the fab) ● Pre-fab everything you’ll ever need – 20x area, 20x delay cost – Circuit building blocks are somewhat bigger than logic gates 6-LUT 6-LUT 6-LUT 6-LUT 4 6-LUT 6-LUT FPGA Soft Processors ● FPGA systems often have software components – Often running on a soft processor ● Need more performance? – Parallel code and hardware accelerators need effort – Less effort if soft processors got faster 5 FPGA Soft Processors ● FPGA systems often have software components – Often running on a soft processor ● Need more performance? – Parallel code and hardware accelerators need effort – Less effort if soft processors got faster 6 FPGA Soft Processors ● FPGA systems often have software components – Often running on a soft processor ● Need more performance? – Parallel
    [Show full text]
  • EDN Magazine, December 17, 2004 (.Pdf)
    ᮋ HE BEST 100 PRODUCTS OF 2004 encompass a range of architectures and technologies Tand a plethora of categories—from analog ICs to multimedia to test-and-measurement tools. All are innovative, but, of the thousands that manufacturers announce each year and the hundreds that EDN reports on, only about 100 hot products make our readers re- ally sit up and take notice. Here are the picks from this year's crop. We present the basic info here. To get the whole scoop and find out why these products are so compelling, go to the Web version of this article on our Web site at www.edn.com. There, you'll find links to the full text of the articles that cover these products' dazzling features. ANALOG ICs Power Integrations COMMUNICATIONS NetLogic Microsystems Analog Devices LNK306P Atheros Communications NSE5512GLQ network AD1954 audio DAC switching power converter AR5005 Wi-Fi chip sets search engine www.analog.com www.powerint.com www.atheros.com www.netlogicmicro.com D2Audio Texas Instruments Fulcrum Microsystems Parama Networks XR125 seven-channel VCA8613 FM1010 six-port SPI-4,2 PNI8040 add-drop module eight-channel VGA switch chip multiplexer www.d2audio.com www.ti.com www.fulcrummicro.com www.paramanet.com International Rectifier Wolfson Microelectronics Motia PMC-Sierra IR2520D CFL ballast WM8740 audio DAC Javelin smart-antenna IC MSP2015, 2020, 4000, and power controller www.wolfsonmicro.com www.motia.com 5000 VoIP gateway chips www.irf.com www.pmc-sierra.com www.edn.com December 17, 2004 | edn 29 100 Texas Instruments Intel DISCRETE SEMICONDUCTORS
    [Show full text]
  • Introduction to Intel® FPGA IP Cores
    Introduction to Intel® FPGA IP Cores Updated for Intel® Quartus® Prime Design Suite: 20.3 Subscribe UG-01056 | 2020.11.09 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Introduction to Intel® FPGA IP Cores..............................................................................3 1.1. IP Catalog and Parameter Editor.............................................................................. 4 1.1.1. The Parameter Editor................................................................................. 5 1.2. Installing and Licensing Intel FPGA IP Cores.............................................................. 5 1.2.1. Intel FPGA IP Evaluation Mode.....................................................................6 1.2.2. Checking the IP License Status.................................................................... 8 1.2.3. Intel FPGA IP Versioning............................................................................. 9 1.2.4. Adding IP to IP Catalog...............................................................................9 1.3. Best Practices for Intel FPGA IP..............................................................................10 1.4. IP General Settings.............................................................................................. 11 1.5. Generating IP Cores (Intel Quartus Prime Pro Edition)...............................................12 1.5.1. IP Core Generation Output (Intel Quartus Prime Pro Edition)..........................13 1.5.2. Scripting IP Core Generation....................................................................
    [Show full text]
  • North American Company Profiles 8X8
    North American Company Profiles 8x8 8X8 8x8, Inc. 2445 Mission College Boulevard Santa Clara, California 95054 Telephone: (408) 727-1885 Fax: (408) 980-0432 Web Site: www.8x8.com Email: [email protected] Fabless IC Supplier Regional Headquarters/Representative Locations Europe: 8x8, Inc. • Bucks, England U.K. Telephone: (44) (1628) 402800 • Fax: (44) (1628) 402829 Financial History ($M), Fiscal Year Ends March 31 1992 1993 1994 1995 1996 1997 1998 Sales 36 31 34 20 29 19 50 Net Income 5 (1) (0.3) (6) (3) (14) 4 R&D Expenditures 7 7 7 8 8 11 12 Capital Expenditures — — — — 1 1 1 Employees 114 100 105 110 81 100 100 Ownership: Publicly held. NASDAQ: EGHT. Company Overview and Strategy 8x8, Inc. is a worldwide leader in the development, manufacture and deployment of an advanced Visual Information Architecture (VIA) encompassing A/V compression/decompression silicon, software, subsystems, and consumer appliances for video telephony, videoconferencing, and video multimedia applications. 8x8, Inc. was founded in 1987. The “8x8” refers to the company’s core technology, which is based upon Discrete Cosine Transform (DCT) image compression and decompression. In DCT, 8-pixel by 8-pixel blocks of image data form the fundamental processing unit. 2-1 8x8 North American Company Profiles Management Paul Voois Chairman and Chief Executive Officer Keith Barraclough President and Chief Operating Officer Bryan Martin Vice President, Engineering and Chief Technical Officer Sandra Abbott Vice President, Finance and Chief Financial Officer Chris McNiffe Vice President, Marketing and Sales Chris Peters Vice President, Sales Michael Noonen Vice President, Business Development Samuel Wang Vice President, Process Technology David Harper Vice President, European Operations Brett Byers Vice President, General Counsel and Investor Relations Products and Processes 8x8 has developed a Video Information Architecture (VIA) incorporating programmable integrated circuits (ICs) and compression/decompression algorithms (codecs) for audio/video communications.
    [Show full text]
  • Intel® Arria® 10 Device Overview
    Intel® Arria® 10 Device Overview Subscribe A10-OVERVIEW | 2020.10.20 Send Feedback Latest document on the web: PDF | HTML Contents Contents Intel® Arria® 10 Device Overview....................................................................................... 3 Key Advantages of Intel Arria 10 Devices........................................................................ 4 Summary of Intel Arria 10 Features................................................................................4 Intel Arria 10 Device Variants and Packages.....................................................................7 Intel Arria 10 GX.................................................................................................7 Intel Arria 10 GT............................................................................................... 11 Intel Arria 10 SX............................................................................................... 14 I/O Vertical Migration for Intel Arria 10 Devices.............................................................. 17 Adaptive Logic Module................................................................................................ 17 Variable-Precision DSP Block........................................................................................18 Embedded Memory Blocks........................................................................................... 20 Types of Embedded Memory............................................................................... 21 Embedded Memory Capacity in
    [Show full text]
  • Demystifying Internet of Things Security Successful Iot Device/Edge and Platform Security Deployment — Sunil Cheruvu Anil Kumar Ned Smith David M
    Demystifying Internet of Things Security Successful IoT Device/Edge and Platform Security Deployment — Sunil Cheruvu Anil Kumar Ned Smith David M. Wheeler Demystifying Internet of Things Security Successful IoT Device/Edge and Platform Security Deployment Sunil Cheruvu Anil Kumar Ned Smith David M. Wheeler Demystifying Internet of Things Security: Successful IoT Device/Edge and Platform Security Deployment Sunil Cheruvu Anil Kumar Chandler, AZ, USA Chandler, AZ, USA Ned Smith David M. Wheeler Beaverton, OR, USA Gilbert, AZ, USA ISBN-13 (pbk): 978-1-4842-2895-1 ISBN-13 (electronic): 978-1-4842-2896-8 https://doi.org/10.1007/978-1-4842-2896-8 Copyright © 2020 by The Editor(s) (if applicable) and The Author(s) This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Open Access This book is licensed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made. The images or other third party material in this book are included in the book’s Creative Commons license, unless indicated otherwise in a credit line to the material.
    [Show full text]
  • Moore's Law Motivation
    Motivation: Moore’s Law • Every two years: – Double the number of transistors CprE 488 – Embedded Systems Design – Build higher performance general-purpose processors Lecture 8 – Hardware Acceleration • Make the transistors available to the masses • Increase performance (1.8×↑) Joseph Zambreno • Lower the cost of computing (1.8×↓) Electrical and Computer Engineering Iowa State University • Sounds great, what’s the catch? www.ece.iastate.edu/~zambreno rcl.ece.iastate.edu Gordon Moore First, solve the problem. Then, write the code. – John Johnson Zambreno, Spring 2017 © ISU CprE 488 (Hardware Acceleration) Lect-08.2 Motivation: Moore’s Law (cont.) Motivation: Dennard Scaling • The “catch” – powering the transistors without • As transistors get smaller their power density stays melting the chip! constant 10,000,000,000 2,200,000,000 Transistor: 2D Voltage-Controlled Switch 1,000,000,000 Chip Transistor Dimensions 100,000,000 Count Voltage 10,000,000 ×0.7 1,000,000 Doping Concentrations 100,000 Robert Dennard 10,000 2300 Area 0.5×↓ 1,000 130W 100 Capacitance 0.7×↓ 10 0.5W 1 Frequency 1.4×↑ 0 Power = Capacitance × Frequency × Voltage2 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 Power 0.5×↓ Zambreno, Spring 2017 © ISU CprE 488 (Hardware Acceleration) Lect-08.3 Zambreno, Spring 2017 © ISU CprE 488 (Hardware Acceleration) Lect-08.4 Motivation Dennard Scaling (cont.) Motivation: Dark Silicon • In mid 2000s, Dennard scaling “broke” • Dark silicon – the fraction of transistors that need to be powered off at all times (due to power + thermal
    [Show full text]
  • Hardware Mechanisms for Distributed Dynamic Software Analysis
    Hardware Mechanisms for Distributed Dynamic Software Analysis by Joseph Lee Greathouse A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Computer Science and Engineering) in The University of Michigan 2012 Doctoral Committee: Professor Todd M. Austin, Chair Professor Scott Mahlke Associate Professor Robert Dick Associate Professor Jason Nelson Flinn c Joseph Lee Greathouse All Rights Reserved 2012 To my parents, Gail and Russell Greathouse. Without their support throughout my life, I would never have made it this far. ii Acknowledgments First and foremost, I must thank my advisor, Professor Todd Austin, for his help and guid- ance throughout my graduate career. I started graduate school with the broad desire to “research computer architecture,” but under Professor Austin’s watch, I have been able to hone this into work that interests us both and has real applications. His spot-on advice about choosing topics, performing research, writing papers, and giving talks has been an invaluable introduction to the research world. The members of my committee, Professors Robert Dick, Jason Flinn, and Scott Mahlke, also deserve special gratitude. Their insights, comments, and suggestions have immea- surably improved this dissertation. Together their expertise spans low-level hardware to systems software and beyond. This meant that I needed to ensure that any of my ideas were defensible from all sides. I have been fortunate enough to collaborate with numerous co-authors. I have often published with Professor Valeria Bertacco, who, much like Professor Austin, has given me invaluable advice during my time at Michigan. I am extremely lucky to have had the chance to work closely with Ilya Wagner, David Ramos, and Andrea Pellegrini, all of whom have continued to be good friends even after the high-stress publication process.
    [Show full text]
  • Case Studies: Memory Behavior of Multithreaded Multimedia and AI Applications
    Case Studies: Memory Behavior of Multithreaded Multimedia and AI Applications Lu Peng*, Justin Song, Steven Ge, Yen-Kuang Chen, Victor Lee, Jih-Kwon Peir*, and Bob Liang * Computer Information Science & Engineering Architecture Research Lab University of Florida Intel Corporation {lpeng, peir}@cise.ufl.edu {justin.j.song, steven.ge, yen-kuang.chen, victor.w.lee, bob.liang}@intel.com Abstract processor operated as two logical processors [3]. Active threads on each processor have their own local states, Memory performance becomes a dominant factor for such as Program Counter (PC), register file, and today’s microprocessor applications. In this paper, we completion logic, while sharing other expensive study memory reference behavior of emerging components, such as functional units and caches. On a multimedia and AI applications. We compare memory multithreaded processor, multiple active threads can be performance for sequential and multithreaded versions homogenous (from the same application), or of the applications on multithreaded processors. The heterogeneous (from different independent applications). methodology we used including workload selection and In this paper, we investigate memory-sharing behavior parallelization, benchmarking and measurement, from homogenous threads of emerging multimedia and memory trace collection and verification, and trace- AI workloads. driven memory performance simulations. The results Two applications, AEC (Acoustic Echo Cancellation) from the case studies show that opposite reference and SL (Structure Learning), were examined. AEC is behavior, either constructive or disruptive, could be a widely used in telecommunication and acoustic result for different programs. Care must be taken to processing systems to effectively eliminate echo signals make sure the disruptive memory references will not [4].
    [Show full text]