Using MDA to Automate the Integration of Virtual Platforms for System-Level Simulation David Perillo Marco Di Natale Elettronica SpA, Roma Scuola Superiore S. Anna, Pisa Email: [email protected] Email: [email protected] Abstract—This paper presents the work performed at and virtual platforms supported by an eclipse-based frame- (removed for blind review) to automate the integration work. The framework includes the Papyrus modeller to of virtual systems development (VSD) and simulation describe the system, its interfaces and components ac- in its embedded software development process. The approach is based on a combination of meta- tivation rules in SysML, following the Platform Based models, model transformations and design patterns, Design (PBD) approach. A generation chain, integrated the SysML standard and the use of the open source in the framework and based on the Acceleo open toolset, Eclipse framework. The purpose is to derive all the synthetizes hardware-software interfaces and glue code design refinements, including the production code and implementing virtual hardware elements on top of the the code used for simulation and verification from a SIMICS full system simulator. single set of SysML models. Stereotypes and model transformations are defined The main contribution of the proposed methodology is to allow the integration of automatically generated to derive the design refinements and the configuration of interfaces and manually produced code implementing the virtual platform from a single set of SysML models, virtual platforms for the simulation of HW/SW hetero- representing the system at a higher level of abstraction. geneous systems on the SIMICS platform. The production code and the code used for simulation I. Introduction and verification are derived from these models together Embedded software runs in a tight interaction with with the hardware documentation. The single source of the hardware, often codesigned or codeveloped. When the information guarantees the alignment of interfaces. complexity of the system grows, the difficulty to inves- The SysML models make use of purposely developed tigate malfunctionings and errors increases. Hardware- profiles and stereotypes containing concepts related to the software interactions provide some of the most critical representation of low-level details of interface to firmware challenges in the verification process since they may be (FPGA) components, functional and mapping elements the source of two types of errors: misalignment between that are not directly available in the standard SysML or components interfaces, and components interoperability in the Marte [15] profile. and behavioral interaction errors. II. Background and State Of the Art The traditional debugging approach is to run the em- Our framework is based on a customized profile realized bedded software on the target hardware to perform the on top of SysML, code generation templates and the use test cases and collect traces to identify errors in the source of the SIMICS simulator and provides support for the code. This strategy is inefficient: it occurs late; it requires following activities: several iterations before the bug is fixed; and it keeps the target hardware busy for a long time just to solve • System Modelling, concerning the use of (semi)formal clerical errors in the code. Most of the times the target languages to describe systems at different levels of hardware is not dedicated to only one software team or granularity. is physically not available because it has not been yet • System-Level Synthesis, consisting in a framework for realized. In addition, hardware-software interaction errors the automatic generation of software and firmware are typically very difficult to discover and replicate. components. The use of virtual platforms (VPs) allows testing and • Hardware/Software cosimulation, by means of Virtual verification long before the hardware is available; gives Platforms (VPs). the possibility to run complex tests, inject faults and In the Platform-based design (PBD) methodology func- test the software in conjunction with multiple hardware tional elements are put in correspondence with platform configurations. These considerations make the use of VPs a elements through a mapping model, defining allocation critical tool for developing and debugging the interactions rules and implementation (refinement) constraints. The of the software with the hardware layer, the HW/SW Metropolis design environment for Heterogeneous Systems partitioning and the analysis of the interfaces. uses the Platform-based design methodology [17] for the We defined a design, implementation and verification representation, analysis, and synthesis of systems repre- methodology based on SysML models, code generators, sented in SystemC. Metropolis supports several compu- tation models (MOC) by refinement on an underlying ilarly to VHDL and Verilog, the library comes with a generic metamodel [13]. Ptolemy is an environment for simulation kernel that allows both Loosely-Timed (LT) modelling and simulating heterogeneous systems. Ptolemy and Approximately-Timed (AT) coding styles depending [14] is mostly targeted at simulation. Code generation of on the required timing accuracy and simulation speed. implementations is supported only for the Java language. An intermediate solution is the software-timed accuracy PBD System models can also be described using the (ST), implemented in the WindRiver Simics simulator [3], SysML modelling standard [23], which extends UML to which is in essence event-based simulation. Events (such provide a language for Systems Engineering specification, as for instance a read operation from a memory register) analysis, design, verification, and validation. The Marte are handled by the simulation kernel and result in the profile extends UML and SysML to provide standard execution of a simulated behavior. stereotypes specific for the embedded systems domain. Several solutions and commercial tools are available to The Complex framework [6] enables HW/SW co-design support the creation of Virtual Platforms (VPs), capable and Design-Space Exploration (DSE) of embedded so- of executing the same binary software as the physical hard- lutions with a platform based design approach. It is ware being simulated. Instruction Set Simulation tools based on UML/MARTE models describing SW and HW (ISS) allow to execute the binary software unmodified, components and Use case diagrams. M2T generation fa- including a full Operating System stack. Differently from cilities convert UML models into IP-Xact specifications cycle-accurate (CAS), phase-accurate (PAS) and timing- and SystemC code implementing the simulation platform. accurate (TAS) simulators, which can emulate the proces- A simulation monitor supports the design exploration sor at the physical signal level [11], ISS cannot simulate process by providing numerical estimates of WCETs and superscalar ordering effects [2]. SystemC-TLM implemen- power consumptions. The Complex framework enables fast tations of Instruction Set Simulators (ISS) are also avail- DSE iterations deriving the design refinements from UML able. QEMU [16] is an Open Source ISS emulating a large and Simulink models but requires significant SystemC number of microprocessor and devices. New devices can be programming for increasing the accuracy of HW models. modelled in C code using QDev and connected in a device The SPRIT consortium formalized the IP-XACT speci- tree in which devices are recursively connected via busses. fication of IP component interfaces through an XSD meta- Direct connection between devices is not possible. QBox model. SPRIT can be used to model hardware-software and TLMu integrate a SystemC bridge on QEMU ISS, interfaces but lacks low-level details like dual page memory enabling the possibility to increase the timing accuracy. banks and default register values. OVPSim (Open Virtual Platform Simulator) is another Manually editing IP-XACT XML models is complex, open solution available only for ARM processors. Simics error prone and time consuming. The Kactus2 framework provides a large set of processors and integrated devices [7] extends IP-XACT to support SW and HW mapping. plus a model builder tool for creating models of IP cores The tool provides export facilities to ModelSim; Altera using the DML device modelling language. Quartus and Verilog. The need to express timing require- Our workflow is based on the Model Driven Architecture ments and to integrate IP-XACT specification in Papyrus (MDA) OMG standard, enabling the user to describe is addressed in [8], providing a partial UML/MARTE rep- complex application logics with a formal semantic, in- resentation of IP-XACT. The elements in our UML profile dependently from the specific execution platform. OMG provides concepts not directly available in IP-XACT or has defined the standard specifications for transformation MARTE, and OCL constraints to validate models. languages: model-to-text, as described in MOFM2T [19] An example of System-Level Synthesis is the IP-based and model-to-model, as described in MOF/QVT [20]. design methodology providing automatic generation of Transformation languages are based on the OCL syntax HW/SW interface components[12]. Plaintext files, Excel [18] to constraint expressions on UML models. We decided sheets, custom XML formats, IP-XACT specifications, to implement profiles and transformations on the Eclipse and SystemRDL code can be used to describe hardware- platform [22] because it provides an open implementation software interfaces