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Notes VLSI DESIGN NOTES (Subject Code: 7EC5) COMPUCOM INSTITUTE OF TECHNOLOGY & MANAGEMENT, JAIPUR (DEPARTMENT OF ELECTRONICS & COMMUNICATION) Notes VLSI DESIGN NOTES (Subject Code: 7EC5) Prepared By: MANVENDRA SINGH Class: B. Tech. IV Year, VII Semester VLSI DESIGN BASIC ELECTRICAL PROPERTIES OF MOS CIRCUITS Syllabus UNIT 2: BASIC ELECTRICAL PROPERTIES OF MOS CIRCUITS- Ids versus Vds relationship, Aspects of threshold voltage, Transistor Transconductance gm. The nMOS inverter, Pull up to Pull-down ratio for a NMOS Inverter and CMOS Inverter (Bn/Bp), MOS transistor circuit Model, Noise Margin. Prepared By: MANVENDRA SINGH Page 2 VLSI DESIGN BASIC ELECTRICAL PROPERTIES OF MOS CIRCUITS Unit -2 BASIC ELECTRICAL PROPERTIES OF MOS CIRCUITS Derivation of the iD -vDS relationship Now that we have developed the essential physical intuition underlying MOSFET operation, we derive a mathematical description (equations) of operation. • In other words, i-v curves that are pretty much shaped correctly are good, but exact equations for these lines are even better. • Consider an NMOS operating in triode mode: vGS > Vt and vDS < vGS − Vt (1) • Consider an infinitesimal segment of the channel of length dx at a point x from the source and let the channel voltage at this point be v(x). • Figure: Illustration to aid in the derivation of the iD - vDS characteristic of the NMOS transistor. Fig. 1 vDS characteristic of the NMOS Prepared By: MANVENDRA SINGH Page 3 VLSI DESIGN BASIC ELECTRICAL PROPERTIES OF MOS CIRCUITS • The gate to channel voltage at this point is vGS − v(x). • The electron charge dq(x) in this infinitesimal portion of the channel is: dq(x) = −CoxW dx [vGS − v(x) − Vt] (2) where: – Recall good old Q = CV? – The negative sign is due to negative electron charge. – Cox is the capacitance per unit area of the parallel-plate capacitor formed by the gate electrode and the channel, and is given by: Cox =(1/ tox) (3) – ox is the permittivity of SiO2 (3.5 × 10−13F/cm). – tox is the thickness of the oxide layer (0.02 to 0.1 µm). – Recall good old C= d for a parallel plate A capacitor? – W (channel width) times dx (infinitesimal length along channel) has units of area. – [vGS − v(x) − Vt] is the voltage driving charge aggregation on the capacitor plates. • vDS produces an electric field (E ) along the channel in the negative x direction (leftward). • Recall that electric field is the negative gradient of the potential: E (x) = - (dv(x)/dx) (4) Prepared By: MANVENDRA SINGH Page 4 VLSI DESIGN BASIC ELECTRICAL PROPERTIES OF MOS CIRCUITS •Also recall that electrons (negative charge carriers) move against the electric field. An electron located at x will, therefore, move with a velocity dx/dt Thus, we can relate electron velocity to channel potential: dx/dt= −µnE (x) (5) dx/dt = µn(dv(x)/dx) (6) where µn is the electron mobility in the channel. Charged carriers moving by virtue of electric fields constitutes drift current. Drift current (i) can be found by multiplying the charge per unit length dq(x)/dx by the drift velocity: i = −µnCoxW[vGS − v(x) − Vt] (dv(x)/dx) (7) • Note that current is constant at all points along the channel (due to conservation of charge). • Thus we can write the drain-to-source current (iD ) is simply the negative of i (which is positive for current flowing from source-to-drain): iD = −µnCoxW[vGS − v(x) − Vt] (dv(x)/dx) (8) • Solving this differential equation is quite simple. First, rearrange as: iDdx = µnCoxW[vGS − Vt− v(x)] (dv(x)/dx) (9) Second, integrate both sides along the channel (e.g., from x = 0 where v(0) = 0 to x = L where v(L) = vDS : ∫iDdx = ∫µnCoxW[vGS − Vt− v(x)] (dv(x)/dx) (10) Finally, evaluating the integral yields: Prepared By: MANVENDRA SINGH Page 5 VLSI DESIGN BASIC ELECTRICAL PROPERTIES OF MOS CIRCUITS iD = (µnCox) (W/L)(Vgs-Vt)Vds-Vds/2 (11) • This is the iD − vDS characteristic in the triode region. • The expression for the saturation region is found by substituting vDS = vGS - Vt into the triode equation, yielding: iD= 1/2(µnCox) W/L(vGS − Vt)2 (12) Note that saturation current is independent of vDS as expected. • Note that current is proportional to the MOSFET channel aspect ratio ( W/L ); both parameters can be specified during circuit design in order to achieve the desired i − v characteristic. • µnCox is a constant determined by the process technology and is known as the process transconductance parameter (kn with units A/V2): k n= µnCox (13) – Cutoff region (vGS < Vt) iD = 0 (14) – Saturation region (vDS ≥ vGS − Vt): iD= 1/2k n W/L(vGS − Vt)2 (15) Aspects of threshold voltage The threshold voltage of a MOSFET is usually defined as the gate voltage where an inversion layer forms at the interface between the insulating layer (oxide) and the substrate (body) of Prepared By: MANVENDRA SINGH Page 6 VLSI DESIGN BASIC ELECTRICAL PROPERTIES OF MOS CIRCUITS the transistor. The purpose of the inversion layer's forming is to allow the flow of electrons through the gate-source junction. The creation of this layer is described next. Fig. 2 When VGS > VTHN (nMOSFET), the semiconductor/oxide interface is inverted, i.e., the inversion layer is formed. In an n-MOSFET the substrate of the transistor is composed of p-type silicon (see doping (semiconductor)), which has positively charged mobile holes as carriers. When a positive voltage is applied on the gate, an electric field causes the holes to be repelled from the interface, creating a depletion region containing immobile negatively charged acceptor ions. A further increase in the gate voltage eventually causes electrons to appear at the interface, in what is called an inversion layer, or channel. Historically the gate voltage at which the electron density at the interface is the same as the hole density in the neutral bulk material is called the threshold voltage. Practically speaking the threshold voltage is the voltage at which there are sufficient electrons in the inversion layer to make a low resistance conducting path between the MOSFET source and drain. In the figures, the source (left side) and drain (right side) are labeled n+ to indicate heavily − doped (blue) n-regions. The depletion layer dopant is labeled NA to indicate that the ions in the (pink) depletion layer are negatively charged and there are very few holes. In the (red) bulk the number of holes p = NA making the bulk charge neutral. If the gate voltage is below the threshold voltage (top figure), the transistor is turned off and ideally there is no current from the drain to the source of the transistor. In fact, there is a current Prepared By: MANVENDRA SINGH Page 7 VLSI DESIGN BASIC ELECTRICAL PROPERTIES OF MOS CIRCUITS even for gate biases below threshold (subthreshold leakage) current, although it is small and varies exponentially with gate bias. If the gate voltage is above the threshold voltage (lower figure), the transistor is turned on, due to there being many electrons in the channel at the oxide-silicon interface, creating a low-resistance channel where charge can flow from drain to source. For voltages significantly above threshold, this situation is called strong inversion. The channel is tapered when VD > 0 because the voltage drops due to the current in the resistive channel reduces the oxide field supporting the channel as the drain is approached. Transistor Transconductance gm The small-signal drain current due to vgs is therefore given by Prepared By: MANVENDRA SINGH Page 8 VLSI DESIGN BASIC ELECTRICAL PROPERTIES OF MOS CIRCUITS Fig. 3 Transistor Model and Characteristics of MOS ■ Evaluating the partial derivative: ■ In order to find a simple expression that highlights the dependence of gm on the DC drain current, we neglect the (usually) small error in writing: For typical values and what find that An NMOS inverter In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. The truth table is shown on the right. Prepared By: MANVENDRA SINGH Page 9 VLSI DESIGN BASIC ELECTRICAL PROPERTIES OF MOS CIRCUITS This represents perfect switching behavior, which is the defining assumption in Digital electronics. In practice, actual devices have electrical characteristics that must be carefully considered when designing inverters. In fact, the non-ideal transition region behavior of a CMOS inverter makes it useful in analog electronics as a class A amplifier (e.g., as the output stage of an operational amplifier) Figure: 4 An NMOS inverter The gate of the depletion mode transistor is connected to its drain, to keep the transistor permanently turned on. The depletion mode transistor is used as a ``pull-up'' resistor, and the enhancement mode transistor is used as a switch to ``pull down'' the output when the switch is turned on. Note that in this technology, the resistance of the permanently turned on depletion mode transistor must be large compared with the ``on'' resistance of the enhancement mode transistor, but small compared with the ``off'' resistance of the transistor. This type of logic is often called a ``ratioed logic'', since the ratio of the pull-up resistance to the pull-down resistance effectively determines the voltage at which the output of the device changes state. Typically, . The large resistive pull-up transistor causes three particular problems with this technology: 1. The depletion mode transistor must be made large ( i.e., long and thin) to create the large ``on'' resistance. Prepared By: MANVENDRA SINGH Page 10 VLSI DESIGN BASIC ELECTRICAL PROPERTIES OF MOS CIRCUITS 2. When driving a capacitive output load such as the gate of another transistor, the charging time (proportional to ) will be long compared to the discharging time (proportional to ).
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