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Random-Access Memory (RAM) Random-Access Memory (RAM) Key features Lecture 13 RAM is packaged as a chip. Basic storage unit is a cell (one bit per cell). The Memory Hierarchy Multiple RAM chips form a memory. Static RAM (SRAM) See Lecture 7B CA2 page 12 Each cell stores bit with a six-transistor circuit. Topics Retains value indefinitely, as long as it is kept powered. Relatively insensitive to disturbances such as electrical noise. Storage technologies and trends Faster and more expensive than DRAM. Locality of reference Dynamic RAM (DRAM) Caching in the memory hierarchy Each cell stores bit with a capacitor and transistor. Value must be refreshed every 10-100 ms. Sensitive to disturbances. Slower and cheaper than SRAM. F13 – 2 – Datorarkitektur 2009 SRAM vs DRAM Summary Conventional DRAM Organization d x w DRAM: dw total bits organized as d supercells of size w bits Tran. Access 16 x 8 DRAM chip per bit time Persist? Sensitive? Cost Applications cols 0 1 2 3 2 bits 0 SRAM 6 1X Yes No 100X cache memories / addr 1 DRAM 1 10X No Yes 1X Main memories, rows memory frame buffers 2 supercell controller (to CPU) (2,1) 3 8 bits / data internal row buffer F13 – 3 – Datorarkitektur 2009 F13 – 4 – Datorarkitektur 2009 Reading DRAM Supercell (2,1) Reading DRAM Supercell (2,1) Step 2(a): Column access strobe (CAS) selects column 1. Step 1(a): Row access strobe (RAS) selects row 2. Step 2(b): Supercell (2,1) copied from buffer to data lines, and Step 1(b): Row 2 copied from DRAM array to row buffer. eventually back to the CPU. 16 x 8 DRAM chip 16 x 8 DRAM chip cols cols 0 1 2 3 0 RAS = 2 CAS = 1 1 2 3 2 2 0 / / 0 addr addr 1 To CPU 1 memory rows memory rows 2 controller controller 2 8 3 supercell 8 3 / (2,1) / data data internal row buffer supercell internal row buffer (2,1) internal buffer F13 – 5 – Datorarkitektur 2009 F13 – 6 – Datorarkitektur 2009 Memory Modules Enhanced DRAMs addr (row = i, col = j) All enhanced DRAMs are built around the conventional : supercell (i,j) DRAM core. DRAM 0 64 MB Fast page mode DRAM (FPM DRAM) memory module Access contents of row with [RAS, CAS, CAS, CAS, CAS] instead of DRAM 7 consisting of [(RAS,CAS), (RAS,CAS), (RAS,CAS), (RAS,CAS)]. eight 8Mx8 DRAMs Extended data out DRAM (EDO DRAM) Enhanced FPM DRAM with more closely spaced CAS signals. Synchronous DRAM (SDRAM) bits bits bits bits bits bits bits bits 56-63 48-55 40-47 32-39 24-31 16-23 8-15 0-7 Driven with rising clock edge instead of asynchronous control signals. Double data-rate synchronous DRAM (DDR SDRAM) 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 Memory Enhancement of SDRAM that uses both clock edges as control controller signals. 64-bit doubleword at main memory address A Video RAM (VRAM) Like FPM DRAM, but output is produced by shifting row buffer 64-bit doubleword Dual ported (allows concurrent reads and writes) F13 – 7 – Datorarkitektur 2009 F13 – 8 – Datorarkitektur 2009 Typical Bus Structure Connecting Nonvolatile Memories CPU and Memory DRAM and SRAM are volatile memories A bus is a collection of parallel wires that carry address, Lose information if powered off. data, and control signals. Nonvolatile memories retain value even if powered off. Generic name is read-only memory (ROM). Buses are typically shared by multiple devices. Misleading because some ROMs can be read and modified. Types of ROMs CPU chip Programmable ROM (PROM) register file Eraseable programmable ROM (EPROM) Electrically eraseable PROM (EEPROM) ALU Flash memory system bus memory bus Firmware Program stored in a ROM I/O main bus interface Boot time code, BIOS (basic input/ouput system) bridge memory graphics cards, disk controllers. F13 – 9 – Datorarkitektur 2009 F13 – 10 – Datorarkitektur 2009 Memory Read Transaction (1) Memory Read Transaction (2) CPU places address A on the memory bus. Main memory reads A from the memory bus, retreives word x and places it on the bus. register file register file Load operation: movl A, %eax Load operation: movl A, %eax ALU ALU %eax %eax main memory main memory I/O bridge 0 0 A I/O bridge x bus interface x A bus interface x A F13 – 11 – Datorarkitektur 2009 F13 – 12 – Datorarkitektur 2009 Memory Read Transaction (3) Memory Write Transaction (1) CPU read word x from the bus and copies it into register %eax. CPU places address A on bus. Main memory reads it and waits for the corresponding data word to arrive. register file register file Load operation: movl A, %eax Store operation: movl %eax, A ALU ALU %eax x %eax y main memory main memory I/O bridge 0 I/O bridge 0 A bus interface x A bus interface A F13 – 13 – Datorarkitektur 2009 F13 – 14 – Datorarkitektur 2009 Memory Write Transaction (2) Memory Write Transaction (3) CPU places data word y on the bus. Main memory read data word y from the bus and stores it at address A. register file register file Store operation: movl %eax, A Store operation: movl %eax, A ALU ALU %eax y %eax y main memory main memory 0 I/O bridge 0 I/O bridge y bus interface A bus interface y A F13 – 15 – Datorarkitektur 2009 F13 – 16 – Datorarkitektur 2009 Disk Geometry Disk Geometry (Muliple-Platter View) Disks consist of platters, each with two surfaces. Aligned tracks form a cylinder. Each surface consists of concentric rings called tracks. cylinder k Each track consists of sectors separated by gaps. surface 0 platter 0 tracks surface 1 surface surface 2 track k gaps platter 1 surface 3 surface 4 platter 2 surface 5 spindle spindle sectors F13 – 17 – Datorarkitektur 2009 F13 – 18 – Datorarkitektur 2009 Disk Capacity Computing Disk Capacity Capacity = (# bytes/sector) x (avg. # sectors/track) x Capacity: maximum number of bits that can be stored. Vendors express capacity in units of gigabytes (GB), where 1 GB = 10^9. (# tracks/surface) x (# surfaces/platter) x (# platters/disk) Capacity is determined by these technology factors: (# platters/disk) Recording density (bits/in): number of bits that can be squeezed into a 1 Example: inch segment of a track. 512 bytes/sector Track density (tracks/in): number of tracks that can be squeezed into a 1 300 sectors/track (on average) inch radial segment. 20,000 tracks/surface 2 surfaces/platter Areal density (bits/in2): product of recording and track density. 5 platters/disk Modern disks partition tracks into disjoint subsets called recording zones Capacity = 512 x 300 x 20000 x 2 x 5 Each track in a zone has the same number of sectors, determined by the circumference of innermost track. = 30,720,000,000 Each zone has a different number of sectors/track = 30.72 GB F13 – 19 – Datorarkitektur 2009 F13 – 20 – Datorarkitektur 2009 Disk Operation (Single-Platter View) Disk Operation (Multi-Platter View) The read/write head read/write heads move in unison The disk surface is attached to the end from cylinder to cylinder spins at a fixed of the arm and flies over rotational rate the disk surface on a thin cushion of air. arm s e p l e l d n i p i s n d n d spindi le l e p s spindle By moving radially, the arm can position the read/write head over any track. F13 – 21 – Datorarkitektur 2009 F13 – 22 – Datorarkitektur 2009 Disk Access Time Disk Access Time Example Given: Average time to access some target sector approximated by : Rotational rate = 7,200 RPM Taccess = Tavg seek + Tavg rotation + Tavg transfer Average seek time = 9 ms. Avg # sectors/track = 400. Seek time (Tavg seek) Derived: Time to position heads over cylinder containing target sector. Tavg rotation = 1/2 x (60 secs/7200 RPM) x 1000 ms/sec = 4 ms. Typical Tavg seek = 9 ms Tavg transfer = 60/7200 RPM x 1/400 secs/track x 1000 ms/sec = 0.02 ms Rotational latency (Tavg rotation) Taccess = 9 ms + 4 ms + 0.02 ms Time waiting for first bit of target sector to pass under r/w head. Important points: Access time dominated by seek time and rotational latency. Tavg rotation = 1/2 x 1/RPMs x 60 sec/1 min First bit in a sector is the most expensive, the rest are free. Transfer time (Tavg transfer) SRAM access time is about 4 ns/doubleword, DRAM about 60 ns Time to read the bits in the target sector. Disk is about 40,000 times slower than SRAM, Tavg transfer = 1/RPM x 1/(avg # sectors/track) x 60 secs/1 min. 2,500 times slower then DRAM. F13 – 23 – Datorarkitektur 2009 F13 – 24 – Datorarkitektur 2009 Logical Disk Blocks I/O Bus CPU chip Modern disks present a simpler abstract view of the complex register file sector geometry: ALU The set of available sectors is modeled as a sequence of b-sized system bus memory bus logical blocks (0, 1, 2, ...) I/O main Mapping between logical blocks and actual (physical) bus interface sectors bridge memory Maintained by hardware/firmware device called disk controller. Converts requests for logical blocks into (surface,track,sector) triples. I/O bus Expansion slots for other devices such USB graphics disk Allows controller to set aside spare cylinders for each zone. as network adapters. controller adapter controller Accounts for the difference in “formatted capacity” and “maximum capacity”. mouse keyboard monitor disk F13 – 25 – Datorarkitektur 2009 F13 – 26 – Datorarkitektur 2009 Reading a Disk Sector (1) Reading a Disk Sector (2) CPU chip CPU chip CPU initiates a disk read by writing a Disk controller reads the sector and performs register file register file command, logical block number, and a direct memory access (DMA) transfer into ALU destination memory address to a port ALU main memory.
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