DOCSLIB.ORG

Towards a Reconfigurable Nanocomputer Platform

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Towards a Reconfigurable Nanocomputer Platform Towards a Reconfigurable Nanocomputer Platform Paul Beckett School of Electrical & Computer Engineering, RMIT University 124 Latrobe St., Melbourne, Australia, 3000 [email protected] Abstract striking a balance between logic and interconnect is Some ideas are presented for achieving low- often difficult. overhead reconfigurability in systems built from The continued scaling of devices into the deep-sub- nanoscale components. Via three example circuits, it micron region will have a number of consequences is demonstrated how it will be possible to exploit a for reconfigurable systems. For example, it appears number of alternative “dimensions” – apart from the likely that only arrays of simple cells with highly obvious spatial dimension - to construct compact localised interconnect will be available. This will be configurable cells. Configurability based on dual the inevitable result of the reduced fanout, power gate transistors using RTD-based multi-valued logic handling capacity, gain and reliability of DSM and the variable resistance of phase-change films are devices. Thus it is likely that the boundaries between shown. A high-density non-volatile reconfigurable logic and interconnect will become increasingly cell is proposed in which a double junction spin filter difficult to identify. tunnel junction is built on a vertical conducting pillar On the other hand, as a result of scaling novel and integrated into a nearest neighbour-connected circuit techniques are becoming available: vertically mesh. Some brief comments are made about how integrated and thin-film based transistors, computing applications might exploit such a heterogenous resonant tunnelling devices, single- homogenous non-volatile processing mesh. electron quantum dots and spin filter devices to name just a few. 1 Introduction This paper addresses the basic question: how can Reconfigurable architectures are of great interest to low-overhead reconfigurable systems be built with system designers because they offer a way of nanoscale technology? It is proposed that the answer achieving power and performance efficiency by to this question is really the same as that for matching algorithmic constructs with the appropriate achieving high fabrication density – to exploit the architectures [1]. The traditional approach to “3rd dimension” wherever available. reconfiguration, in FPGAs for example, has been to The use of aggressive vertical integration is build separate areas of programmable logic gates and resulting in some extremely compact circuits (e.g. interconnection blocks from transistors and to [5]) and 3D or spatially stacked techniques promise manage the two resources more-or-less separately to increase this significantly [6]. However, this is not during the synthesis process. Much of the work on the only “dimension” available. High density, high constructing reconfigurable platforms has therefore functionality configurable building blocks can also be been directed towards answering the questions “how achieved by simultaneously exploiting a number of much of each and in what form?” [2], [3]. This is available physical variables (voltage, current, largely because reconfiguration is expensive – it threshold voltage; magnetic field, electron spin, etc). increases the area and power requirements, while Three plausible configurable building blocks will reducing the performance of a system compared to be described that illustrate how this might be purpose-built solutions1. It also places constraints on achieved. In Section 2, an example is presented of the solution space accessible to the synthesis process how transistor logic scaled into the nanometer that are unique to the particular platform, reducing domain can be combined with RTD-based multi- the generality of system solutions. Achieving valued logic to support fine-grained configurability. optimum performance in a reconfigurable system by A second example, in Section 3, exploits the characteristics of phase transition thin-films and vertical integration to reduce the size of the cell and 1 This has been stated as the “Law” of FPGAs vs. ASICs: at the same time support non-volatile operation. In ”for any FPGA-based application, there is an ASIC Section 4, a cell based on magnetic tunnelling implementation of the system that is AT LEAST as fast, technology is described that exploits a number of dense, power-efficient, and cheap in (very) high volumes as physical variables to merge logic and configuration the FPGA based solution” [4] into a single space. The fabrication of these building To merge this into the processing mesh will involve blocks will not be described in exhaustive detail. matching the VG1 values required to set the MITT Rather, the intention is to explore how the particular into its three operating domains with the RTD techniques might offer high functionality within tunnelling voltages V1-3 which are set, in turn, by dense structures. adjusting the (AlAs) barrier thicknesses of both Finally, Section 5 briefly outlines a general RTDs [19]. direction that computing applications might take on The top gate connections form the contact point to such a homogenous non-volatile processing mesh. the RTD memory cells. In the configuration shown, memory cells are paired with each pair setting the 2 A Multi-valued SRAM Based Platform configuration for the two-input NOR gate below. This example mesh brings together the Resonant The cell layout depicted in Figure 5 is based on a Tunnelling based multi-valued SRAM described in similar layout described in [8] and illustrates how the [7] and more recently in [8] and [9], the metal- heterojunction RTDs might be assembled on a insulator tunnel transistor (MITT) [10], [11] and a substrate grown over an insulator layer containing the some of the 3D interconnection ideas described, for MITTs. example, in [12], [13] and [14]. The resulting Top Gate structure forms a large planar logic mesh of simple gate insulator (2-input) logic gates in two of its dimensions, which Source Drain can be configured into a interconnected logic structure via a vertically stacked (multi-valued) RTD- gate insulator Back Gate Tunnel based RAM array. Insulator Although their characteristics are similar, the substrate MITT device [10] operates quite differently to a standard FET. The gate voltage modulates the tunnel Figure 1 Proposed Double-Gate Metal Insulator barrier thickness, changing the Fowler-Nordheim Tunnel Transistor tunnelling currents that flow through the metal/insulator junction. In the proposed device 1.0 0.0V (Figure 1), a second (back) gate has been added so A VDD that the tunnelling current becomes a function of 0.8 both. A number of dual-gate transistors have been 0.6 -0.1V RL described (e.g. [15], [16], [17], [18]) but none based 2 B on MITT technology . This idea has the advantage 0.4 that the all-metal devices are compatible with current -0.2V 0.2 VG1 VG2 fabrication processes and can be easily extended to -0.3V C multi-layer 3D topologies. 0 -0.4V Accessing the two gates independently allows the -0.6 -0.4 -0.2 0.0 0.2 upper gate to be used to set the operating point of the Second-Gate Voltage transistor – effectively setting the threshold voltage of the lower gate that provides the logic connection. Figure 2 Typical Dual Gate Transfer By setting the transistor bias points appropriately, a Characteristics logic gate can be built that exhibits three operating Word Line I regions (Figure 2) – always on (VG1>0.1), always off D VDD3 IP (VG1<-0.4) and inverting operation with a logic swing of 0.4V (-0.2 <VG1< -0.1). The top-gate voltage VG1 will become the reconfiguration voltage for the homogenous logic mesh. IV The 3-state memory cell proposed by Wei et al [7] Bit Line VD and more recently by van der Wagt [8] provides a VSS V1 V2 V3 VDD3 VSS useful mechanism for generating the three threshold voltages required. The basic memory cell is redrawn Figure 3 RTD-Based SRAM Cell (from [7]) in Figure 3 along with its (idealised) load-line curves. A major problem with RTDs is the need to closely control the growth of the tunnelling layers as the 2 tunnelling current depends exponentially on the the back-gate is not intrinsically necessary in this case as tunnel barrier thicknesses. For large scale integration the operation would be the same with any dual-gate III/V technology appears to be the most promising, transistor. The back-gate makes the cell layout denser. although a number of significant processing For optical disk applications, the difference in optical challenges remain [20]. At present the integration characteristics between the crystalline and amorphous density is limited by the minimum lateral feature states defines the logic state of an individual cell, sizes for RTD devices (about 1 µm) and their whereas for RAM applications it is the resistance of operating currents (peak currents are about 5mA). the film that is measured [23]. The Nanotechnology Roadmap [20] predicts that they The chalcogenide alloy material is compatible with will scale to about 200nm by 2006 and around 50nm current (CMOS) logic fabrication, adding only 2 - 4 by 2012. At this point, these RTD-based memory late, low temperature mask steps to a standard cells could be built with dimensions down to about process [24]. The technology scales well as smaller 300nm x 100nm, and the MITT based logic cells memory cells use less power during the phase should scale to ~10nm gate lengths. This represents a change, operate at lower voltages, are less prone to density in the order of 3 x 109 cells/cm2,
Load more

Recommended publications
  • Nano Computing Revolution and Future Prospects
    Recent Research in Science and Technology 2012, 4(3): 16-17 ISSN: 2076-5061 Available Online: http://recent-science.com/ Nano computing revolution and future prospects Deepti Hirwani and Anuradha Sharma Maharaja Agrasen International College, Raipur C.G, India Abstract There are several ways nanocomputers might be built, using mechanical, electronic, biochemical, or quantum technology. It is unlikely that nanocomputers will be made out of semiconductor transistors (Microelectronic components that are at the core of all modern electronic devices), as they seem to perform significantly less well when shrunk to sizes under 100 nanometers.The research results summarized here also suggest that many useful, yet strikingly different solutions may exist for tolerating defects and faults within nanocomputing systems. Also included in the survey are a number of software tools useful for quantifying the reliability of nanocomputing systems in the presence of defects and faults. Keywords: Nano computing, electronic devices, technology INTRODUCTION classical computer would have to repeat 2 x input numbers, Nanocomputer is the logical name for the computer smaller performing the same task that a classical computer would have to then the microcomputer, which is smaller than the minicomputer. repeat 2 x times or use 2 xprocessors working in parallel. In other (The minicomputer is called “mini” because it was a lot smaller than words a quantum computer offers an enormous gain in the use of the original (mainframe) computers.) More technically, it is a computational resources such as time and memory. This becomes computer whose fundamental part is no bigger than a few mind boggling when you think of what 32 qubits can accomplish.
    [Show full text]
  • 1. Types of Computers Contents
    1. Types of Computers Contents 1 Classes of computers 1 1.1 Classes by size ............................................. 1 1.1.1 Microcomputers (personal computers) ............................ 1 1.1.2 Minicomputers (midrange computers) ............................ 1 1.1.3 Mainframe computers ..................................... 1 1.1.4 Supercomputers ........................................ 1 1.2 Classes by function .......................................... 2 1.2.1 Servers ............................................ 2 1.2.2 Workstations ......................................... 2 1.2.3 Information appliances .................................... 2 1.2.4 Embedded computers ..................................... 2 1.3 See also ................................................ 2 1.4 References .............................................. 2 1.5 External links ............................................. 2 2 List of computer size categories 3 2.1 Supercomputers ............................................ 3 2.2 Mainframe computers ........................................ 3 2.3 Minicomputers ............................................ 3 2.4 Microcomputers ........................................... 3 2.5 Mobile computers ........................................... 3 2.6 Others ................................................. 4 2.7 Distinctive marks ........................................... 4 2.8 Categories ............................................... 4 2.9 See also ................................................ 4 2.10 References
    [Show full text]
  • Advanced Technology and the Future of U.S. Manufacturing
    Advanced Technology and the Future of U.S. Manufacturing Proceedings of a Georgia Tech research and policy workshop Edited by Philip Shapira, Jan Youtie, and Aselia Urmanbetova Georgia Tech Policy Project on Industrial Modernization School of Public Policy and the Georgia Tech Economic Development Institute Georgia Institute of Technology Atlanta, GA 30332-0345, USA SRI International, Prime Contractor Center for Science Technology and Economic Development Arlington, VA 22209-3915, USA April 2004 Table of Contents Preface.............................................................................................................................................. i Summary........................................................................................................................................ iv Participants in the Workshop on Advanced Technology and the Future of US Manufacturing .... x 1. A Brief History of the Future of Manufacturing: U.S. Manufacturing Technology Forecasts in Retrospective, 1950-present........................................................................................................ 1 2. Technological Opportunities to Develop New Capabilities: Manufacturing, Strategic Engineering, Adaptive Technologies, and Controls ................................................................. 29 2.1. Manufacturing Directions from Manufacturing Research Center (MARC) Perspective .. 29 2.2. Strategic Engineering on the Integrated Design of Products and Processes...................... 32 2.3. Additive Manufacturing
    [Show full text]
  • Nanowire Nanocomputer As a Finite-State Machine
    Nanowire nanocomputer as a finite-state machine Jun Yaoa, Hao Yana, Shamik Dasb,1, James F. Klemicb, James C. Ellenbogenb, and Charles M. Liebera,c,1 aDepartment of Chemistry and Chemical Biology and cSchool of Engineering and Applied Science, Harvard University, Cambridge, MA 02138; and bNanosystems Group, The MITRE Corporation, McLean, VA 22102 Contributed by Charles M. Lieber, December 20, 2013 (sent for review December 12, 2013) Implementation of complex computer circuits assembled from the Previous efforts have yielded circuit elements that perform bottom up and integrated on the nanometer scale has long been simple logic functions using small numbers of individual nano- a goal of electronics research. It requires a design and fabrication electronic devices (8–17), but have fallen far short of demon- strategy that can address individual nanometer-scale electronic strating the combination of arithmetic and register elements devices, while enabling large-scale assembly of those devices into required to realize a FSM. Specifically, integration of distinct highly organized, integrated computational circuits. We describe functional circuit elements necessitates the capability to fabricate how such a strategy has led to the design, construction, and and precisely organize circuit systems that interconnect large demonstration of a nanoelectronic finite-state machine. The sys- numbers of addressable nanometer-scale electronic devices in tem was fabricated using a design-oriented approach enabled by a readily extensible manner. As a result, implementation of a deterministic, bottom–up assembly process that does not require a nanoelectronic FSM (nanoFSM) via bottom–up assembly of individual nanowire registration. This methodology allowed con- individually addressable nanoscale devices has been well beyond struction of the nanoelectronic finite-state machine through mod- the state of the art.
    [Show full text]
  • International Roadmap for Devices and Systems
    INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2020 EDITION BEYOND CMOS THE IRDS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS OR EQUIPMENT. ii © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. THE INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS: 2020 COPYRIGHT © 2020 IEEE. ALL RIGHTS RESERVED. iii Table of Contents Acknowledgments .............................................................................................................................. vi 1. Introduction .................................................................................................................................. 1 1.1. Scope of Beyond-CMOS Focus Team .............................................................................................. 1 1.2. Difficult Challenges ............................................................................................................................ 2 1.3. Nano-information Processing Taxonomy........................................................................................... 4 2. Emerging Memory Devices ..........................................................................................................
    [Show full text]
  • Wires, Switches, and Wiring. a Route Toward a Chemically Assembled Electronic Nanocomputer*
    Pure Appl. Chem., Vol. 72, Nos. 1–2, pp. 11–20, 2000. © 2000 IUPAC Wires, switches, and wiring. A route toward a chemically assembled electronic nanocomputer* James R. Heath† Department of Chemistry and Biochemistry, UCLA, 405 Hilgard Ave., Los Angeles, CA 90095-1569 USA Abstract: A Boolean logic, nonreversible computing machine should, in principle, be capable of 1018 bit operations per second at a power consumption of 1 W. In order to build such a machine that can even approach this benchmark for efficiency, the development of a robust quantum-state switch capable of ambient operation, as well as a bottom–up manufacturing technology, will be necessary. My group, in collaboration with Hewlett Packard, has developed much of the architecture for such a machine, which we call a chemically assembled electronic nanocomputer (CAEN). More recently, in a collaborative effort with Fraser Stoddart’s group at UCLA, we have begun to build it. The fundamental unit of the machine is a field- programmable molecular switch, and the fundamental architecture is a hierarchical organization of wire/switch lattices called crossbars. Electronically, singly configurable molecular-based switch devices based on rotaxane molecular compounds have been fabricated in high yield. These switches were used to construct simple molecular-based logic structures and read-only memory elements. INTRODUCTION In the early 1960s Rolf Landauer began to consider the physics of information manipulation [1]. All modern computers are Boolean logic, nonreversible machines. This implies that the states ‘1’ and ‘0’ need to be energetically distinct from one another. Furthermore, in a nonreversible machine, information is lost.
    [Show full text]
  • Clocking Nanocircuits for Nanocomputers and Other Nanoelectronic Systems
    Clocking Nanocircuits for Nanocomputers and Other Nanoelectronic Systems Shamik Das and Matthew F. Bauwens Nanosystems Group The MITRE Corporation 7515 Colshire Dr., McLean, VA 22102, USA {sdas,mbauwens}@mitre.org nanodevice clock frequency VDD # stages ref. Abstract— Prospective performance bounds are determined by simulation for a class of all-nanoelectronic clocking circuits. multiple CNTs 5Hz 1.5 V 3 [5] multiple CNTs 220 Hz 4V 3 [36] Such nanocircuits could be utilized as on-chip master clocks for nanowire transistors 11.7 MHz 43 V 3 [37] stand-alone nanosystems, as local clocks within nanoelectronic single CNT 52 MHz 0.92 V 5 [38] computers, or as local oscillators in mixed-signal nanoelectronic applications. Designs and simulation results are presented for TABLE I. Experimentally demonstrated clock circuits using nanoelectronic these nanocircuits, which are intended to be manufacturable devices. These circuits consist of ring oscillators built from nanoscale tran- using presently available nanodevices and nanofabrication tech- sistors and conventional lithographic-scale interconnects. niques. The results presented here indicate that such clocking nanocircuits, if built using presently available devices, could achieve operating frequencies up to approximately 1 GHz for structures and signals also are needed. One control structure analog applications and 150 MHz for digital nanoelectronic that must satisfy stringent performance constraints is the systems. clock generation and distribution structure for a nanoelectronic I. INTRODUCTION system. Analysis of an all-nanoelectronic clock circuit would provide insight into the challenges and the prospective perfor- There has been much progress over the past several years mance of a nanoelectronic computer system. in the design and development of nanocomputer systems inte- In Section II of this paper, designs and simulation results grated on the molecular scale [1–35].
    [Show full text]
  • Compiling Mechanical Nanocomputer Components
    P a g e | 36 Vol. 10 Issue 2 (Ver 1.0), April 2010 Global Journal of Computer Science and Technology Compiling Mechanical Nanocomputer Components GJCST Computing Classification Thomas Way, Tao Tao and Bryan Wagner D.2.2, C.5.3 & B.1.4 Department of Computing Sciences Villanova University Villanova, PA, USA [email protected] Abstract- Computer component fabrication is approaching Modern compilers for high performance computer physical limits of traditional photolithographic fabrication architectures apply a sequence of sophisticated analyses and techniques. Alternative computer architectures are being optimizations to translate a source language program into enabled by the rapidly maturing field of nanotechnology, and efficient binary machine code. Machine specific range from nanoelectronics and bioelectronics to nano- optimizations, customized to the particular target mechanical computational machines and other nanoscale components. In this study, the design of a nanocompiler, which architecture, are required to achieve significant speedup on targets a simulated hydrocarbon assembler, is presented. The modern, high-performance architectures [2,9]. In spite of compiler framework demonstrates the feasibility of a hardware public announcements made in early 2007 of advances in compiler to produce building block components, a necessary feature-size reduction by Intel and AMD, heat dissipation first step in full molecular assembly of nano-mechanical and barriers of physics remain as problems [1,5]. computers. As a proof of concept, the resulting nano- Nanotechnology, manufacturing performed through mechanical machine components are simulated using a manipulation of atoms and molecules, or through other Colored Petri Net model of a 32-bit adder and an atomic-level nanoscale manufacturing techniques, is capable of gate simulator.
    [Show full text]
  • Technology Directions for the 21St Century Volume IV
    NASA/CR--1998-207408 Technology Directions for the 21st Century Volume IV Giles Crimi, Henry Verheggen, Robert Botta, Heywood Paul, and Xuyen Vuong Science Applications International Corporation, McLean, Virginia Prepared under Contract NAS3-26565 National Aeronautics and Space Administration Lewis Research Center May 1998 PREFACE In this rapidly changing world, effective governmental organizations must constantly anticipate and regularly plan for the future. For NASA, the process of doing this has become particularly challenging. Global economic strategies have greatly increased the need for cooperative partnerships to provide adequate resources for space science and exploration programs. Today's technological advances provide ample opportunities to improve the ways in which NASA carries out its responsibilities and serves its customers. NASA's future technology emphasis must focus on dual-use activities; that is, technology must be transferred or leveraged with other government agencies, industrial partners, international counterparts, and academia to share costs, exchange technical knowledge, support a growing economy, and provide technological leadership for our Nation. The competitiveness of commercial ventures, such as those ignited by the deregulation of the telephone industry, has shifted the burden of continuously developing cutting-edge technology from government to the commercial sector. This is the fourth volume of a series of technology trends and applications reports. These reports focus on the continuing effort to predict and understand technology trends to better plan research and development strategies. The objectives of this series of documents are to: (1) validate, revise or expand relevant technology forecasts; (2) develop applications strategies to incorporate new technologies into our programs; and, (3) accomplish Agency goals while stimulating and encouraging development of commercial technology sources.
    [Show full text]
  • Molecules, Gates, Circuits, Computers
    Molecules, Gates, Circuits, Computers Seth Goldstein and Mihai Budiu March 7, 2003 Contents 4.6 Reliability and Electronic- Nanotechnology Computer Systems 36 1 Introduction 2 5 Reconfigurable Hardware 37 2 The Switch 4 5.1 RH Circuits . ............ 38 2.1 Information ............. 4 5.2 Circuit Structures .......... 39 2.2 Boolean Logic Gates ........ 6 5.3 Using RH . ............ 40 2.3 Transistors .............. 8 5.4 Designing RH Circuits . ...... 41 2.4 Manufacturing and Fabrication . 10 5.5 RH Advantages ........... 42 2.5 Moore’s Law . ......... 11 5.6 RH Disadvantages .......... 45 2.6 The Future .............. 12 5.7 RH and Fault Tolerance . ...... 46 2.7 A New Regime . ......... 12 6 Molecular Circuit Elements 49 3 Processor Architecture 14 6.1 Devices . ............ 50 3.1 Computer Architecture . .... 14 6.2 Wires ................ 52 3.2 Instruction Set Architectures .... 16 7 Fabrication 53 3.3 Processor Evolution ......... 17 7.1 Techniques . ............ 54 3.4 Problems Faced by Computer Archi- tecture . ............... 25 7.2 Implications . ............ 55 7.3 Scale Matching ........... 56 4 Reliability in Computer System Architec- 7.4 Hierarchical Assembly of a ture 27 Nanocomputer ............ 59 4.1 Introduction ............. 27 8 Circuits 60 4.2 Reliability .............. 28 8.1 Diode-Resistor Logic . ...... 60 4.3 Increasing Reliability ........ 30 8.2 RTD-Based Logic .......... 61 4.4 Formal Verification ......... 32 8.3 Molecular Latches . ...... 61 4.5 Exposing Unreliability to Higher Layers . ............... 33 8.4 Molecular Circuits . ...... 66 1 March 7, 2003– 10 : 27 8.5 Molecular Transistor Circuits .... 67 architecture–have essentially cut the cost of proces- sor performance in half every 18 months.
    [Show full text]
  • Nanoelectronics, Nanophotonics, and Nanomagnetics Report of the National Nanotechnology Initiative Workshop February 11–13, 2004, Arlington, VA
    National Science and Technology Council Committee on Technology Nanoelectronics, Subcommittee on Nanoscale Science, Nanophotonics, and Nanomagnetics Engineering, and Technology National Nanotechnology Report of the National Nanotechnology Initiative Workshop Coordination Office February 11–13, 2004 4201 Wilson Blvd. Stafford II, Rm. 405 Arlington, VA 22230 703-292-8626 phone 703-292-9312 fax www.nano.gov About the Nanoscale Science, Engineering, and Technology Subcommittee The Nanoscale Science, Engineering, and Technology (NSET) Subcommittee is the interagency body responsible for coordinating, planning, implementing, and reviewing the National Nanotechnology Initiative (NNI). The NSET is a subcommittee of the Committee on Technology of the National Science and Technology Council (NSTC), which is one of the principal means by which the President coordinates science and technology policies across the Federal Government. The National Nanotechnology Coordination Office (NNCO) provides technical and administrative support to the NSET Subcommittee and supports the subcommittee in the preparation of multi- agency planning, budget, and assessment documents, including this report. For more information on NSET, see http://www.nano.gov/html/about/nsetmembers.html . For more information on NSTC, see http://www.ostp.gov/cs/nstc . For more information on NNI, NSET and NNCO, see http://www.nano.gov . About this document This document is the report of a workshop held under the auspices of the NSET Subcommittee on February 11–13, 2004, in Arlington, Virginia. The primary purpose of the workshop was to examine trends and opportunities in nanoscale science and engineering as applied to electronic, photonic, and magnetic technologies. About the cover Cover design by Affordable Creative Services, Inc., Kathy Tresnak of Koncept, Inc., and NNCO staff.
    [Show full text]
  • Sms208: Computer Appreciation for Managers
    SMS208: COMPUTER APPRECIATION FOR MANAGERS NATIONAL OPEN UNIVERSITY OF NIGERIA SMS 208 COMPUTER APPRECIATION FOR MANAGERS COURSE GUIDE SMS 208 COMPUTER APPRECIATION FOR MANAGERS Course Developer Gerald C. Okeke Eco Communication Inc. Ikeja, Lagos Course Editor/Coordinator Adegbola, Abimbola Eunice National Open University of Nigeria Programme Leader Dr. O.J. Onwe National Open University of Nigeria NATIONAL OPEN UNIVERSITY OF NIGERIA 2 SMS 208 COMPUTER APPRECIATION FOR MANAGERS National Open University of Nigeria Headquarters 14/16 Ahmadu Bello Way Victoria Island Lagos Abuja Office No. 5 Dar es Salaam Street Off Aminu Kano Crescent Wuse II, Abuja Nigeria e-mail: [email protected] URL: www.nou.edu.ng Published by National Open University of Nigeria 2008 Printed 2008 ISBN: 978-058-198-7 All Rights Reserved 3 SMS 208 COMPUTER APPRECIATION FOR MANAGERS CONTENTS PAGE Introduction………………………………………………….. 1 Course Objectives…………………………………………… 1 Credit Units………………………………………………….. 2 Study Units………………………………………………….. 2 Course Assessment………………………………………….. 2 Introduction This course is designed to avail managers in business, governance and education with what computer is and its applications in carrying out their every day assignments. This course goes on to acquaint them with the basic component parts of a personal computer and the types available. The emphasis is for them to understand the application of computer in information technology and in information communications technology that translates to effectiveness and efficiency in business and
    [Show full text]