Towards a Reconfigurable Nanocomputer Platform Paul Beckett School of Electrical & Computer Engineering, RMIT University 124 Latrobe St., Melbourne, Australia, 3000 [email protected] Abstract striking a balance between logic and interconnect is Some ideas are presented for achieving low- often difficult. overhead reconfigurability in systems built from The continued scaling of devices into the deep-sub- nanoscale components. Via three example circuits, it micron region will have a number of consequences is demonstrated how it will be possible to exploit a for reconfigurable systems. For example, it appears number of alternative “dimensions” – apart from the likely that only arrays of simple cells with highly obvious spatial dimension - to construct compact localised interconnect will be available. This will be configurable cells. Configurability based on dual the inevitable result of the reduced fanout, power gate transistors using RTD-based multi-valued logic handling capacity, gain and reliability of DSM and the variable resistance of phase-change films are devices. Thus it is likely that the boundaries between shown. A high-density non-volatile reconfigurable logic and interconnect will become increasingly cell is proposed in which a double junction spin filter difficult to identify. tunnel junction is built on a vertical conducting pillar On the other hand, as a result of scaling novel and integrated into a nearest neighbour-connected circuit techniques are becoming available: vertically mesh. Some brief comments are made about how integrated and thin-film based transistors, computing applications might exploit such a heterogenous resonant tunnelling devices, single- homogenous non-volatile processing mesh. electron quantum dots and spin filter devices to name just a few. 1 Introduction This paper addresses the basic question: how can Reconfigurable architectures are of great interest to low-overhead reconfigurable systems be built with system designers because they offer a way of nanoscale technology? It is proposed that the answer achieving power and performance efficiency by to this question is really the same as that for matching algorithmic constructs with the appropriate achieving high fabrication density – to exploit the architectures [1]. The traditional approach to “3rd dimension” wherever available. reconfiguration, in FPGAs for example, has been to The use of aggressive vertical integration is build separate areas of programmable logic gates and resulting in some extremely compact circuits (e.g. interconnection blocks from transistors and to [5]) and 3D or spatially stacked techniques promise manage the two resources more-or-less separately to increase this significantly [6]. However, this is not during the synthesis process. Much of the work on the only “dimension” available. High density, high constructing reconfigurable platforms has therefore functionality configurable building blocks can also be been directed towards answering the questions “how achieved by simultaneously exploiting a number of much of each and in what form?” [2], [3]. This is available physical variables (voltage, current, largely because reconfiguration is expensive – it threshold voltage; magnetic field, electron spin, etc). increases the area and power requirements, while Three plausible configurable building blocks will reducing the performance of a system compared to be described that illustrate how this might be purpose-built solutions1. It also places constraints on achieved. In Section 2, an example is presented of the solution space accessible to the synthesis process how transistor logic scaled into the nanometer that are unique to the particular platform, reducing domain can be combined with RTD-based multi- the generality of system solutions. Achieving valued logic to support fine-grained configurability. optimum performance in a reconfigurable system by A second example, in Section 3, exploits the characteristics of phase transition thin-films and vertical integration to reduce the size of the cell and 1 This has been stated as the “Law” of FPGAs vs. ASICs: at the same time support non-volatile operation. In ”for any FPGA-based application, there is an ASIC Section 4, a cell based on magnetic tunnelling implementation of the system that is AT LEAST as fast, technology is described that exploits a number of dense, power-efficient, and cheap in (very) high volumes as physical variables to merge logic and configuration the FPGA based solution” [4] into a single space. The fabrication of these building To merge this into the processing mesh will involve blocks will not be described in exhaustive detail. matching the VG1 values required to set the MITT Rather, the intention is to explore how the particular into its three operating domains with the RTD techniques might offer high functionality within tunnelling voltages V1-3 which are set, in turn, by dense structures. adjusting the (AlAs) barrier thicknesses of both Finally, Section 5 briefly outlines a general RTDs [19]. direction that computing applications might take on The top gate connections form the contact point to such a homogenous non-volatile processing mesh. the RTD memory cells. In the configuration shown, memory cells are paired with each pair setting the 2 A Multi-valued SRAM Based Platform configuration for the two-input NOR gate below. This example mesh brings together the Resonant The cell layout depicted in Figure 5 is based on a Tunnelling based multi-valued SRAM described in similar layout described in [8] and illustrates how the [7] and more recently in [8] and [9], the metal- heterojunction RTDs might be assembled on a insulator tunnel transistor (MITT) [10], [11] and a substrate grown over an insulator layer containing the some of the 3D interconnection ideas described, for MITTs. example, in [12], [13] and [14]. The resulting Top Gate structure forms a large planar logic mesh of simple gate insulator (2-input) logic gates in two of its dimensions, which Source Drain can be configured into a interconnected logic structure via a vertically stacked (multi-valued) RTD- gate insulator Back Gate Tunnel based RAM array. Insulator Although their characteristics are similar, the substrate MITT device [10] operates quite differently to a standard FET. The gate voltage modulates the tunnel Figure 1 Proposed Double-Gate Metal Insulator barrier thickness, changing the Fowler-Nordheim Tunnel Transistor tunnelling currents that flow through the metal/insulator junction. In the proposed device 1.0 0.0V (Figure 1), a second (back) gate has been added so A VDD that the tunnelling current becomes a function of 0.8 both. A number of dual-gate transistors have been 0.6 -0.1V RL described (e.g. [15], [16], [17], [18]) but none based 2 B on MITT technology . This idea has the advantage 0.4 that the all-metal devices are compatible with current -0.2V 0.2 VG1 VG2 fabrication processes and can be easily extended to -0.3V C multi-layer 3D topologies. 0 -0.4V Accessing the two gates independently allows the -0.6 -0.4 -0.2 0.0 0.2 upper gate to be used to set the operating point of the Second-Gate Voltage transistor – effectively setting the threshold voltage of the lower gate that provides the logic connection. Figure 2 Typical Dual Gate Transfer By setting the transistor bias points appropriately, a Characteristics logic gate can be built that exhibits three operating Word Line I regions (Figure 2) – always on (VG1>0.1), always off D VDD3 IP (VG1<-0.4) and inverting operation with a logic swing of 0.4V (-0.2 <VG1< -0.1). The top-gate voltage VG1 will become the reconfiguration voltage for the homogenous logic mesh. IV The 3-state memory cell proposed by Wei et al [7] Bit Line VD and more recently by van der Wagt [8] provides a VSS V1 V2 V3 VDD3 VSS useful mechanism for generating the three threshold voltages required. The basic memory cell is redrawn Figure 3 RTD-Based SRAM Cell (from [7]) in Figure 3 along with its (idealised) load-line curves. A major problem with RTDs is the need to closely control the growth of the tunnelling layers as the 2 tunnelling current depends exponentially on the the back-gate is not intrinsically necessary in this case as tunnel barrier thicknesses. For large scale integration the operation would be the same with any dual-gate III/V technology appears to be the most promising, transistor. The back-gate makes the cell layout denser. although a number of significant processing For optical disk applications, the difference in optical challenges remain [20]. At present the integration characteristics between the crystalline and amorphous density is limited by the minimum lateral feature states defines the logic state of an individual cell, sizes for RTD devices (about 1 µm) and their whereas for RAM applications it is the resistance of operating currents (peak currents are about 5mA). the film that is measured [23]. The Nanotechnology Roadmap [20] predicts that they The chalcogenide alloy material is compatible with will scale to about 200nm by 2006 and around 50nm current (CMOS) logic fabrication, adding only 2 - 4 by 2012. At this point, these RTD-based memory late, low temperature mask steps to a standard cells could be built with dimensions down to about process [24]. The technology scales well as smaller 300nm x 100nm, and the MITT based logic cells memory cells use less power during the phase should scale to ~10nm gate lengths. This represents a change, operate at lower voltages, are less prone to density in the order of 3 x 109 cells/cm2,