Received August 3, 2020, accepted September 14, 2020, date of publication September 21, 2020, date of current version October 6, 2020. Digital Object Identifier 10.1109/ACCESS.2020.3025367 Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA CARLO SAU 1, (Member, IEEE), TIZIANA FANNI 2, CLAUDIO RUBATTU 2,3, (Member, IEEE), LUCA FANNI2, LUIGI RAFFO1, (Member, IEEE), AND FRANCESCA PALUMBO 2, (Member, IEEE) 1Department of Electrical and Electronic Engineering (DIEE), University of Cagliari, 09123 Cagliari, Italy 2Department of Chemistry and Pharmacy, University of Sassari, 07100 Sassari, Italy 3IETR UMR CNRS 6164, INSA Rennes, University of Rennes 1, 35700 Rennes, France Corresponding author: Carlo Sau (
[email protected]) This work was supported by the European Union's Horizon 2020 Research and Innovation Programme under Grant 732105. The work of Francesca Palumbo was supported by the University of Sassari through the Fondo di Ateneo per la Ricerca 2019. ABSTRACT Modern embedded computing platforms used within Cyber-Physical Systems (CPS) are nowadays leveraging more and more often on heterogeneous computing substrates, such as newest Field Programmable Gate Array (FPGA) devices. Compared to general purpose platforms, which have a fixed datapath, FPGAs provide designers the possibility of customizing part of the computing infrastructure, to better shape the execution on the application needs/features, and offer high efficiency in terms of timing and power performance, while naturally featuring parallelism. In the context of FPGA-based CPSs, this article has a two fold mission. On the one hand, it presents an analysis of the Damped Least Square (DLS) algorithm for a perspective hardware implementation.