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Datasheet Search Engine External Cache for the RM5271 Application Note Introduction Quantum Effect Devices, Inc. (QED) was founded in 1991 to design and develop MIPS RISC microprocessors to MIPS Technologies, Inc. (MTI) specifications. MTI sub-licensed those designs to MIPS licensees. In 1996 QED obtained a license to manufacture and sale MIPS microprocessor. QED is currently producing three 64-bit MIPS microprocessors that support external cache; the RM5270, RM5271, and RM7000. The R5000, a QED designed and licensed product, also supports external cache. This paper is applicable to all four devices, but only the RM5271 will be directly reference herein. This paper will discuss only the external cache, its implementation, and enhancements made to the secondary cache controller. For the RM5270, RM5271, and R5000 the external cache is a second level cache. For the RM7000 the external cache is a third level cache. The RM5271 provides an on-chip controller for external second level cache. The second level cache is a unified direct- mapped block write-through cache with byte parity protection. It requires two types of pipelined synchronous burst SRAM, a Tag SRAM and a Data SRAM. The Tag SRAM is used to maintain a list of cache lines stored in the Data SRAM plus a single bit with each Tag to define whether the cache line that tag points to, or indexes, in the data SRAM contains valid data or not. The Data SRAM must have a parity bit for each byte since the system interface uses even parity to protect data transfers. Not all transactions on the System Interface reference the external secondary cache. The external cache is not accessed for a double word, partial double word, word, or partial word read or write. The external cache is accessed only for memory space with the cache coherency of “Write Back”. Memory space with cache coherency of “Write Through With Allocate”, “Write Through Without Allocate” or “Uncached” do not make use of the external cache. Cache coherency and data movements are charted on the last page of this document. Pipeline Burst SRAM verses Flow-through SRAM Synchronous Burst (SyncBurst) SRAMs come in two flavors. Flow-through SRAM latches the address on one clock cycle and drives the data on the next clock cycle. Because of this timing they tend to be bandwidth limited. None of QED’s microprocessor can operate with Flow-Through Burst SRAM, so they will not be discussed further. Pipeline Burst SRAM latches both the input and output data lines. For a read, on the first clock cycle following the latching of the address, the data is latched into the output latch. On the following cycle the data is driven out. This means that for a burst of 32-bytes, first data is fetched in three cycles, with each sequential double word fetched in a single cycle. This results in a cache line being read from memory in 3-1-1-1 clock cycles. There are two types of Pipeline Burst SRAM – Single Cycle Deselect (SCD) and Dual Cycle Deselect (DCD). The R5000, being an early design, can only operate with Dual Cycle Deselect (DCD) SyncBurst SRAM. The RM5270, RM5271, and RM7000 can operate with either Dual Cycle Deselect (DCD) or Single Cycle Deselect (SCD) Synchronous Burst SRAM. Single Cycle Deselect (SCD) is the commodity SyncBurst SRAM. Mode bit 15 is set to a one to select SCD timing for SyncBurst SRAM. To find out more about SyncBurst SRAM visit Micron Technology’s web site at www.micron.com. They have about half a dozen technical papers on Synchronous Burst SRAM. Synchronous Burst SRAMs for the Data portion of the external cache are supplied by Micron Technology www.micron.com, Motorola (www.moto.com), GSI Technology (www.gigasemi.com), and Galvantech (www.gvti.com). Motorola (MCM69T618), Galvantech (GVT7164T18), and GSI Technology (GS84118T/B) supply tag SRAMs. There may be other suppliers of these two types of SRAMs. QUANTUM EFFECT DEVICES, INC., 2500-5 AUGUSTINE DRIVE, SUITE 200, SANTA CLARA, CA 95054 408.565.0300 www.qedinc.com External Cache for the RM5271 To understand how to implement an external cache you first have to become familiar with the interactions between it and the RM5271. Secondary Cache Transactions The RM5271 performs only five operations on the external cache. Three of these operations are initiated by the CACHE instructions while the other two operations are block read and block write. The secondary cache is not accessed for non-block transfers. For a read the RM5271 performs a sub-block ordered interleaved access. This allows critical data to be returned first (refer to section 11.20.2 of the RM5200 Family User Manual) allowing the RM5271 to resume execution when it receives the first double word of a requested block of data. For a block write the RM5271 performs a linear sequential access. Reads A block read takes place in external cache following an attempt to fetch instruction from the primary instruction cache or data from the primary data cache. When a read attempt fails to find the requested data in the primary caches, the RM5271 issues a speculative block read to both the external cache and the External Agent. If the block is present in the external cache, (i.e. the cache read hits) the external cache Tag SRAM will assert ScMatch telling the CPU the requested data are found in the external cache and telling the External Agent to abort its read attempt. If the block is not present in the external cache, (i.e. the cache read misses) the ScMatch signal is not asserted. Seeing ScMatch negated at the third cycle, the CPU gives up on reading the data out of the external cache, and yields the system interface to the External Agent so that it can provide the requested data. The data fetched by the external agent will be written to both the external cache and the RM5271. When the RM5271 requires instructions or data that is not in the primary caches, then it presents the physical address to the tag SRAM, the data SRAM, and to the External Agent. All three start a read cycle with this address and read command. If the required data or instruction is in the external data SRAM, then there will be a matching tag in the tag SRAM. This match within the tag SRAM will cause it to drive the ScMatch signal. This signal tells the external agent to cease its read efforts and tells the processor that the secondary cache will be supplying the requested data. When the external cache drives data onto the SysAD bus, it does not have the ability to generate a ValidIn* signal. Therefore, the external cache SRAMs must adhere to the timing requirements of the RM5271. To reduce the time to read the 4 double words from external cache, the data SRAM drives the first of four double words on the same cycle that the Tag SRAM asserts ScMatch. A read that hits in external cache only takes 7 system clock cycles; one for the address, one to give bus ownership to the external cache, one for the first data double-word and ScMatch, 3 for the remaining 3 data double-words, and one to return bus ownership back to the RM5271. If the required data or instruction is not present in the external cache, that is, the cache read misses, then the tag SRAM will not assert ScMatch two cycles after receiving the Index portion of the address. In this case the RM5271 gives bus ownership to the external agent, which continues its read. When the external agent has the data at its system interface, it will cause it to be written both into the data SRAM and the RM5271. The RM5271 will drive the signals necessary to write the corresponding new tag into the tag SRAM. Issuance of the external cache read is controlled by the normal RdRdy* flow control mechanism. External cache read responses always proceed at the maximum data transfer rate. The External Agent read responses to the external cache proceed at the data rate generated by the External Agent. Writes The RM5271 uses a block write-through protocol to write data into the external cache. The RM5271 issues a block write operation that is directed to both the external cache and the external agent. On the same cycle that it drives the address, the processor also drives the cache line’s tag on SysAD[35:19] and the external valid bit, ScValid. This causes a valid Tag to be placed in the tag SRAM. The RM5271 then drives four double words of data onto the system interface and causes them to be latched into both external cache and the external agent. Since external cache writes also go to the external agent, they proceed at the data transfer rate specified in the boot time mode bits (4:1) for write back data rates. Like non-block writes, their issuance is controlled by the normal WrRdy* flow control 2 QUANTUM EFFECT DEVICES, INC., 2500-5 AUGUSTINE DRIVE, SUITE 200, SANTA CLARA, CA 95054 408.565.0300 www.qedinc.com External Cache for the RM5271 mechanism. It is these writes going to both the external cache and the external agent that causes the external cache to be referred to as a block write through cache. That is, block writes go through the external cache to the external agent. Block reads and block writes are two of five operations that can be transacted with the external cache. The other three operations - cache invalidate, cache clear and cache probe - involve only the RM5271 and the external Cache.
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