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MC9S08PB16 Data Sheet: Technical Data Rev NXP Semiconductors Document Number MC9S08PB16 Data Sheet: Technical Data Rev. 2.1, 11/2019 MC9S08PB16 MC9S08PB16 Data Sheet Supports: MC9S08PB16 and MC9S08PB8 Key features • Peripherals – ADC - 12-channel, 12-bit resolution; 2.5 µs • 8-Bit S08 central processor unit (CPU) conversion time; eight-level data FIFO with optional – Up to 20 MHz bus at 2.7 V to 5.5 V across operating watermark; automatic compare function; 1.7 mV/ºC temperature range temperature sensor; internal bandgap reference – Supporting up to 30 interrupt/reset sources channel; operation in stop; optional hardware trigger – Supporting up to four-level nested interrupt – FTM - Two flex timer modulators (FTM) modules – On-chip memory including one 6-channel (FTM2) and one 2-channel – Up to 16 KB flash read/program/erase over full (FTM0) backward compatible with TPM modules; operating voltage and temperature 16-bit counter; each channel can be configured for – Up to 1 KB random-access memory (RAM) input capture, output compare, edge- or center- – Flash and RAM access protection aligned PWM mode • Power-saving modes – FDS - Shut down output pin upon fault detection; – One low power stop mode; reduced power wait the fault sources can be optional enabled separately; mode the output pin can be configured as output 1,0 and – Peripheral clock enable register can disable clocks to high impedance when a fault occurs based on unused modules, reducing currents; allows clocks to module configuration remain enabled to specific peripherals in stop3 mode – MTIM - Two modulo timers with 8-bit prescaler and overflow interrupt • Clocks – PWT — One pulse width timer used to captures a – Internal Clock Source (ICS) — Internal clock source pulse width and pulse period module containing a frequency-locked-loop (FLL) – SCI - One serial communications interface (SCI/ controlled by internal or external reference; UART) modules optional 13-bit break; Full duplex precision trimming of internal reference allows 0.2% non-return to zero (NRZ); LIN extension support resolution; 1% deviation across temperature range of – I2C - One inter-integrated circuit module; up to 400 0 ºC to 70ºC, 1.5% deviation across temperature kbps; multi-master operation; programmable slave range of –40 ºC to 105 ºC and 2% deviation across address; supporting broadcast mode and 10-bit temperature range of –40 ºC to 125 ºC; Up to 20 addressing; supporting SMBUS MHz – ACMP - Two analog comparators with both positive – Oscillator (XOSC) — Loop-controlled Pierce and negative inputs; selectable voltage reference oscillator; crystal or ceramic resonator range of provided by on-chip 6-bit DAC; separately 31.25 kHz to 39.0625 kHz or 4 MHz to 20 MHz selectable interrupt on rising and falling comparator • System protection output – Watchdog with independent clock source – OPAMP — One analog amplifier (OPAMP) with – Low-voltage detection with reset or interrupt; fixed gain x20, supporting up to 100 mV single- selectable trip points ended input. – Illegal opcode detection with reset – RTC - 16-bit real timer counter (RTC) – Illegal address detection with reset – CRC - Cyclic Redundancy Check with programmable 16-/32-bit polynomial generator – KBI — Up to 8 keyboard interrupt inputs NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. • Development support – Single-wire background debug interface – Breakpoint capability to allow three breakpoints setting during in-circuit debugging – On-chip in-circuit emulator (ICE) debug module containing two comparators and nine trigger modes • Input/Output – Up to 18 GPIOs including one output-only pin (PTA4) – One 8-bit keyboard interrupt modules (KBI) – One true open drain pin (PTB0) • Package options – 20-pin TSSOP – 16-pin TSSOP MC9S08PB16 Data Sheet, Rev. 2.1, 11/2019 2 NXP Semiconductors Table of Contents 1 Overview............................................................................................4 6.2 Switching specifications............................................................ 17 1.1 MCU block diagram.................................................................. 4 6.2.1 Control timing..............................................................17 1.2 Peripheral register addresses......................................................5 6.2.2 Debug trace timing specifications................................18 1.3 System interconnection..............................................................6 6.2.3 FTM module timing.....................................................19 2 Orderable part numbers......................................................................7 6.3 Thermal specifications...............................................................20 3 Part identification...............................................................................7 6.3.1 Thermal characteristics................................................ 20 3.1 Description.................................................................................7 7 Peripheral operating requirements and behaviors..............................20 3.2 Format........................................................................................8 7.1 External oscillator (XOSC) and ICS characteristics..................20 3.3 Fields..........................................................................................8 7.2 NVM specifications...................................................................22 3.4 Example..................................................................................... 8 7.3 Analog........................................................................................23 4 Parameter Classification.....................................................................8 7.3.1 ADC characteristics..................................................... 23 5 Ratings................................................................................................9 7.3.2 Analog comparator (ACMP) electricals...................... 26 5.1 Thermal handling ratings...........................................................9 7.3.3 Operational amplifier (OPAMP) electricals................ 26 5.2 Moisture handling ratings..........................................................9 7.3.4 Inter-Integrated Circuit Interface (I2C) timing............27 5.3 ESD handling ratings.................................................................9 8 Dimensions.........................................................................................28 5.4 Voltage and current operating ratings........................................10 8.1 Obtaining package dimensions..................................................28 6 General............................................................................................... 11 9 Pinout................................................................................................. 28 6.1 Nonswitching electrical specifications...................................... 11 9.1 Signal multiplexing and pin assignments.................................. 28 6.1.1 DC characteristics........................................................ 11 9.2 Device pin assignment...............................................................29 6.1.2 Supply current characteristics......................................15 10 Hardware design consideration..........................................................30 6.1.3 EMC performance........................................................16 11 Revision history................................................................................. 31 MC9S08PB16 Data Sheet, Rev. 2.1, 11/2019 NXP Semiconductors 3 Overview 1 Overview 1.1 MCU block diagram The block diagram below shows the structure of the MCUs. PTA0/KBI0P0/FTM0CH0/FDSOUT6/ACMP0IN0/ADP0 HCS08 CORE PTA1/KBI0P1/FTM0CH1/FDSOUT7/ACMP0IN1/ADP1 PTA2/KBI0P2/RxD0/SDA/PWT/ADP2 PTA3/KBI0P3/TxD0/SCL/ACMP1IN0/OPAMP+/ADP3 Port A Port 1 BDCCPU PTA4/FTM0CH1O/ACMP0O/BKGD/MS KEYBOARD INTERRUPT PTA5/IRQ/FTM0CH0/TCLK0/RESET_b 2 MODULE (KBI00) PTB0/KBI0P4/RxD0/ADP4 SYSTEM CONTROL PTB1/KBI0P5/TxD0/ACMP1IN1/ADP5 INTER-INTEGRATED MODULE (SYS) PTB2/KBI0P6/SDA/FDSIN/ADP6 CIRCUIT BUS (IIC) PTB3/KBI0P7/SCL/TCLK2/ADP7 PTB4/FTM2CH4/FDSOUT4 Port B Port WCOP IRQ 8-BIT MODULO TIMER PTB5/FTM2CH5/FDSOUT5 ( MTIM0) PTB6/SDA/XTAL 1 kHz OSC LVD PTB7/SCL/EXTAL 8-BIT MODULO TIMER INTERRUPT PRIORITY (MTIM1) PTC0/FTM2CH0/FDSOUT0/ADP8 CONTROLLER(IPC) PTC1/FTM2CH1/FDSOUT1/ADP9 2-CH FLEX TIMER PTC2/FTM2CH2/FDSOUT2/ADP10 ON-CHIP ICE AND MODULE (FTM0) C Port PTC3/FTM2CH3/FDSOUT3/ADP11 DEBUG MODUE (DBG) 6-CH FLEX TIMER USER FLASH MODULE (FTM2) MC9S08PB16 = 16,384 bytes MC9S08PB8 = 8,192 bytes SERIAL COMMUNICATION INTERFACE (SCI0) USER RAM MC9S08PB16 = 1,024 bytes ANALOG COMPARATOR MC9S08PB8 = 1,024 bytes (ACMP0) ANALOG COMPARATOR (ACMP1) REAL-TIME CLOCK 20 MHz INTERNAL CLOCK (RTC) SOURCE (ICS) OPERATIONAL EXTAL AMPLIFIER (OPAMP) EXTERNAL OSCILLATOR XTAL SOURCE (XOSC) PULSE WIDTH TIMER (PWT) VDD POWER MANAGEMENT VSS CONTROLLER (PMC) FAULT DETECTION &SHUTDOWN (FDS) 12-CH 12-BIT VDD ANALOG-TO-DIGITAL VSS CONVERTER(ADC) CYCLIC REDUNDANCY CHECK (CRC) 1. PTA4/FTM0CH1O/ACMP0O/BKGD/MS is an output-only pin when used as port pin. 2. PTB0 operates as true-open drain when working as output. Figure 1. MCU block diagram MC9S08PB16 Data Sheet, Rev. 2.1, 11/2019 4 NXP Semiconductors Overview 1.2 Peripheral register addresses The register definitions vary in different memory sizes. The register addresses of unused peripherals are reserved. The
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