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MPC8572E Powerquicc III Integrated Processor Hardware Specifications

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MPC8572E Powerquicc III Integrated Processor Hardware Specifications NXP Semiconductors Document Number: MPC8572EEC Technical Data Rev. 7, 03/2016 MPC8572E PowerQUICC III Integrated Processor Hardware Specifications Contents 1 Overview 1. Overview . 1 2. Electrical Characteristics . 10 This section provides a high-level overview of the features 3. Power Characteristics . 15 of the MPC8572E processor. Figure 1 shows the major 4. Input Clocks . 16 functional units within the MPC8572E. 5. RESET Initialization . 18 6. DDR2 and DDR3 SDRAM Controller . 19 7. DUART . 27 1.1 Key Features 8. Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 28 9. Ethernet Management Interface The following list provides an overview of the MPC8572E Electrical Characteristics . 50 feature set: 10. Local Bus Controller (eLBC) . 53 11. Programmable Interrupt Controller . 65 • Two high-performance, 32-bit, Book E-enhanced 12. JTAG . 65 2 cores that implement the Power Architecture® 13. I C . 67 technology: 14. GPIO . 70 15. High-Speed Serial Interfaces (HSSI) . 72 — Each core is identical to the core within the 16. PCI Express . 83 MPC8572E processor. 17. Serial RapidIO . 91 18. Package Description . 101 — 32-Kbyte L1 instruction cache and 32-Kbyte L1 19. Clocking . 120 data cache with parity protection. Caches can be 20. Thermal . 125 locked entirely or on a per-line basis, with 21. System Design Information . 127 22. Ordering Information . 137 separate locking for instructions and data. 23. Document Revision History . 139 — Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive instruction set for vector (64-bit) integer and fractional operations. These instructions use both NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ¬© 2008-2011, 2014, 2016 NXP B.V. Overview the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU. — Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set for single-precision (32-bit) floating-point instructions. — Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit) floating-point instructions that use the 64-bit GPRs. — 36-bit real addressing — Memory management unit (MMU). Especially designed for embedded applications. Supports 4-Kbyte to 4-Gbyte page sizes. — Enhanced hardware and software debug support — Performance monitor facility that is similar to, but separate from, the MPC8572E performance monitor The e500 defines features that are not implemented on this device. It also generally defines some features that this device implements more specifically. An understanding of these differences can be critical to ensure proper operation. • 1 Mbyte L2 cache/SRAM — Shared by both cores. — Flexible configuration and individually configurable per core. — Full ECC support on 64-bit boundary in both cache and SRAM modes — Cache mode supports instruction caching, data caching, or both. — External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing). – 1, 2, or 4 ways can be configured for stashing only. — Eight-way set-associative cache organization (32-byte cache lines) — Supports locking entire cache or selected lines. Individual line locks are set and cleared through Book E instructions or by externally mastered transactions. — Global locking and Flash clearing done through writes to L2 configuration registers — Instruction and data locks can be Flash cleared separately. — Per-way allocation of cache region to a given processor. — SRAM features include the following: – 1, 2, 4, or 8 ways can be configured as SRAM. – I/O devices access SRAM regions by marking transactions as snoopable (global). – Regions can reside at any aligned location in the memory map. – Byte-accessible ECC is protected using read-modify-write transaction accesses for smaller-than-cache-line accesses. • e500 coherency module (ECM) manages core and intrasystem transactions • Address translation and mapping unit (ATMU) — Twelve local access windows define mapping within local 36-bit address space. — Inbound and outbound ATMUs map to larger external address spaces. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 2 NXP Semiconductors Overview – Three inbound windows plus a configuration window on PCI Express – Four inbound windows plus a default window on Serial RapidIO® – Four outbound windows plus default translation for PCI Express – Eight outbound windows plus default translation for Serial RapidIO with segmentation and sub-segmentation support • Two 64-bit DDR2/DDR3 memory controllers — Programmable timing supporting DDR2 and DDR3 SDRAM — 64-bit data interface per controller — Four banks of memory supported, each up to 4 Gbytes, for a maximum of 16 Gbytes per controller — DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports — Full ECC support — Page mode support – Up to 32 simultaneous open pages for DDR2 or DDR3 — Contiguous or discontiguous memory mapping — Cache line, page, bank, and super-bank interleaving between memory controllers — Read-modify-write support for RapidIO atomic increment, decrement, set, and clear transactions — Sleep mode support for self-refresh SDRAM — On-die termination support when using DDR2 or DDR3 — Supports auto refreshing — On-the-fly power management using CKE signal — Registered DIMM support — Fast memory access through JTAG port — 1.8-V SSTL_1.8 compatible I/O — Support 1.5-V operation for DDR3. The detail is TBD pending on official release of appropriate industry specifications. — Support for battery-backed main memory • Programmable interrupt controller (PIC) — Programming model is compliant with the OpenPIC architecture. — Supports 16 programmable interrupt and processor task priority levels — Supports 12 discrete external interrupts — Supports 4 message interrupts per processor with 32-bit messages — Supports connection of an external interrupt controller such as the 8259 programmable interrupt controller — Four global high resolution timers/counters per processor that can generate interrupts — Supports a variety of other internal interrupt sources MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 NXP Semiconductors 3 Overview — Supports fully nested interrupt delivery — Interrupts can be routed to external pin for external processing. — Interrupts can be routed to the e500 core’s standard or critical interrupt inputs. — Interrupt summary registers allow fast identification of interrupt source. • Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec, IKE, SSL/TLS, SRTP, 802.16e, and 3GPP — Four crypto-channels, each supporting multi-command descriptor chains – Dynamic assignment of crypto-execution units through an integrated controller – Buffer size of 256 bytes for each execution unit, with flow control for large data sizes — PKEU—public key execution unit – RSA and Diffie-Hellman; programmable field size up to 4096 bits – Elliptic curve cryptography with F2m and F(p) modes and programmable field size up to 1023 bits — DEU—Data Encryption Standard execution unit – DES, 3DES – Two key (K1, K2, K1) or three key (K1, K2, K3) – ECB, CBC and OFB-64 modes for both DES and 3DES — AESU—Advanced Encryption Standard unit – Implements the Rijndael symmetric key cipher – ECB, CBC, CTR, CCM, GCM, CMAC, OFB-128, CFB-128, and LRW modes – 128-, 192-, and 256-bit key lengths — AFEU—ARC four execution unit – Implements a stream cipher compatible with the RC4 algorithm – 40- to 128-bit programmable key — MDEU—message digest execution unit – SHA-1 with 160-bit message digest – SHA-2 (SHA-256, SHA-384, SHA-512) – MD5 with 128-bit message digest – HMAC with all algorithms — KEU—Kasumi execution unit – Implements F8 algorithm for encryption and F9 algorithm for integrity checking – Also supports A5/3 and GEA-3 algorithms — RNG—random number generator — XOR engine for parity checking in RAID storage applications — CRC execution unit – CRC-32 and CRC-32C • Pattern Matching Engine with DEFLATE decompression MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7 4 NXP Semiconductors Overview — Regular expression (regex) pattern matching – Built-in case insensitivity, wildcard support, no pattern explosion – Cross-packet pattern detection – Fast pattern database compilation and fast incremental updates – 16000 patterns, each up to 128 bytes in length – Patterns can be split into 256 sets, each of which can contain 16 subsets — Stateful rule engine enables hardware execution of state-aware logic when a pattern is found – Useful for contextual searches, multi-pattern signatures, or for performing additional checks after a pattern is found – Capable of capturing and utilizing data from the data stream (such as LENGTH field) and using that information in subsequent pattern searches (for example, positive match only if pattern is detected within the number of bytes specified in the LENGTH field) – 8192 stateful rules — Deflate engine – Supports decompression of DEFLATE compression format including zlib and gzip – Can work independently or in conjunction with the Pattern Matching Engine (that is decompressed data can be passed directly to the Pattern Matching Engine without further software involvement or memory copying) • Two Table Lookup Units (TLU) — Hardware-based lookup engine offloads table searches from e500 cores — Longest prefix match, exact match, chained hash, and flat data table formats
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