LOW TOTAL HARMONIC DISTORTION (THD) RESONANT CONVERTER FOR COOKER MAGNETRON POWER SUPPLY

A thesis presented to the faculty of the Graduate School of Western Carolina University in partial fulfillment of the requirements for the degree of Master of Science in Technology.

By

Yang Zhou

Director: Dr. Robert Adams Associate Professor Department of Engineering and Technology

Committee Members: Dr. H. Bora Karayaka, Department of Engineering and Technology Dr. Paul Yanik, Department of Engineering and Technology

June 2016

©2016 by Yang Zhou ACKNOWLEDGEMENTS

Firstly, I am sincerely grateful to all the faculty members of Kimmel School for their assistance and support during the past two years. My gratitude is extended to my committee members Dr.

H. Bora Karayaka and Dr. Paul Yanik for their guidance and encouragement.

Many thanks go to my fellow graduate students, all other classmates for their patience and help during my past two years of study.

My utmost thanks go to my advisor, Dr. Robert Adams. Thank you for your encourage- ment, willingness to help and advise on issues far beyond this degree. You are not just the advisor during my study in the Kimmel School, but also an example of excellence as a researcher, mentor, instructor, and role model for my life.

Finally, I would like to thank and dedicate this thesis to my family for their endless support.

ii TABLE OF CONTENTS

List of Tables ...... v ListofFigures ...... vi Abstract ...... viii CHAPTER 1. Introduction ...... 1 1.1 Traditional Oven ...... 1 1.1.1 Magnetron Characteristics ...... 1 1.1.2 Traditional Power Supply of the Magnetron in . . . . . 2 1.1.3 Advantages and Disadvantages of the Traditional Power Supply ...... 4 1.2 A New Magnetron Power Supply ...... 5 1.2.1 LLC (-Inductor-) Resonant Converter ...... 6 1.2.2 A New Magnetron Power Supply Based on LLC Resonant Converter . . . 6 1.3 Other Studies on LLC Resonant Based Magnetron Power Supplies ...... 8 CHAPTER 2. LLC based Main Circuit Analysis ...... 9 2.1 Topology Selection ...... 9 2.1.1 Series Resonant Converter (SRC) ...... 9 2.1.2 Parallel Resonant Converter (PRC) ...... 11 2.1.3 Series-Parallel Resonant Converter (SPRC) ...... 12 2.2 Mathematical Derivation of Main Circuit Voltage Gain ...... 14 2.3 Analysis of Main Circuit ...... 18 2.3.1 Voltage Gain Analysis ...... 18 2.3.2 Operation at the Resonant Point (f 1) ...... 20 n = 2.3.3 Zero-Voltage Switching (ZVS) ...... 23 2.4 Design Implementation ...... 24 CHAPTER 3. Hardware Design ...... 26 3.1 Integration Design ...... 26 3.1.1 The List of Transformer Parameters ...... 26 3.1.2 Core Selection ...... 27 3.1.3 Loss Limited Flux Swing ...... 29 3.1.4 Primary and Secondary Turns Calculation ...... 29 3.1.5 Define the Winding Structure ...... 30 3.1.6 The Real Designed Transformer ...... 32 3.2 EMI Filter, Input Rectifier and Output Rectifier Design ...... 32 3.2.1 EMI Filter ...... 33 3.2.2 Input Rectifier ...... 34 3.2.3 Output Rectifier ...... 34 3.3 Main Circuit Design ...... 35 3.3.1 MOSFET Bridge Selection, Loss Calculation, Selection . . . . 35 3.4 Resonant Network ...... 41 3.5 Driver Circuit Design ...... 42 3.5.1 Driver IC Selection ...... 42 3.5.2 Charging and Discharging Path ...... 44 3.5.3 Bootstrap Capacitor Calculation ...... 45 3.5.4 PWM (Pulse Width Modulation) Signal Filtering ...... 48 3.6 Protection and Feedback ...... 49 3.6.1 Detect the Short Circuit Condition ...... 50 3.6.2 Fault Indication and Restart ...... 51 3.6.3 Input Current and Zero-crossing Point of Input Voltage ...... 52 3.7 Layout of PCB () ...... 54 3.7.1 PCB Calculations ...... 54 3.7.2 EMI Suppression ...... 54 CHAPTER 4. Simulation and Experiment ...... 56 4.1 Simulation Results Discussion ...... 56 4.1.1 The Simulation of the Operation of the Resonant Network ...... 57 4.1.2 The Simulation of the Operation of the Resonant Network ...... 58 4.1.3 The Output Voltages at Different Switching Frequencies ...... 59

4.1.4 The Resonant Currents Under Different Inductor Ratio Ln (Lm/Lr ) . . . 62 4.1.5 Soft Switching Realization ...... 62 4.1.6 Soft Start ...... 64 4.2 Experiment Results Discussion ...... 66 CHAPTER 5. Conclusion and Future Work ...... 71 Bibliography ...... 72

iv LIST OF TABLES

1.1 Harmonic Results from Lab Test ...... 4 3.1 Lr and Lm Test Results ...... 32 3.2 Key Performance Parameters of the IPW60R041P6 ...... 37

v LIST OF FIGURES

1.1 Magnetron Structure ...... 2 1.2 Magnetron Voltage and Current ...... 2 1.3 The Picture of Traditional Magnetron Power Supply ...... 3 1.4 A Circuit Diagram of Traditional Magnetron Power Supply ...... 3 1.5 Input Current of MW (Microwave) Oven and Its Fast Fourier Transform . . . . . 5 1.6 LLC Resonant Network ...... 6 1.7 Simplified Main Circuit ...... 7 2.1 Series Resonant Converter ...... 10 2.2 SRC Voltage Gain [1] ...... 10 2.3 Parallel Resonant Converter ...... 11 2.4 PRC Voltage Gain [1] ...... 12 2.5 LCC Series-Parallel Resonant Converter ...... 13 2.6 LCC Resonant Converter Voltage Gain [1] ...... 13 2.7 LLC Series-Parallel Resonant Converter ...... 14 2.8 LLC Resonant Converter Voltage Gain ...... 14 2.9 LLC Based Main Circuit ...... 15 2.10 Secondary Side Equivalent ...... 15 2.11 Equivalent Main Circuit ...... 16 2.12 M vs. L (L 6.5) ...... 19 g n n = 2.13 M vs. L (L 3.5) ...... 19 g n n = 2.14 Main Circuit with Stray Capacitance ...... 21

2.15 Operation of LLC Resonant Converter at f0 [2] ...... 21 2.16 LLC Network Input Impedance ...... 23 3.1 PC40 Material Characteristics [3]...... 27 3.2 PC40 Core Loss vs. Freq at 60 Hz [3]...... 27 3.3 EE Core Diagram [4] ...... 28 3.4 The Transformer Winding Structure...... 31 3.5 The Real Transformer...... 32 3.6 EMI Filter ...... 33 3.7 Input Filter ...... 34 3.8 Output Rectifier ...... 35 3.9 MOSFET Bridge and LLC network ...... 36 3.10 Turn-off Transition Waveform ...... 38 3.11 Heating Sink Dissipation Features ...... 41 3.12 Resonant Network ...... 41 3.13 Voltage on the Resonant Capacitor Cr ...... 42 3.14 Parasite Capacitance in the MOSFET ...... 43 3.15 Typical Gate Charge Diagram [5] ...... 44 3.16 MOSFET Driver Circuit ...... 45 3.17 Bootstrap Power Supply Circuit [6] ...... 46

3.18 VBS under 100 kHz Switching Frequency ...... 47

3.19 VBS under 500 kHz Switching Frequency ...... 48 3.20 RC Low Pass Filter ...... 49 3.21 Over Current Sensor ...... 51 3.22 Flip-Flop Circuit for Fault Indication and Restart ...... 52 3.23 Input Voltage Zero Cross Detection and Input Current Sensor ...... 53 3.24 PCB Layout ...... 55 4.1 Simulation Diagram of the Main Circuit in Pspice ...... 56 4.2 Simulation of the Operation of the Resonant Network ...... 57 4.3 Simulation of the Operation of the Resonant Network ...... 58 4.4 Output Voltages under Different Switching Frequencies ...... 60

4.5 Resonant Current Ir and Magnetizing Current Im under Different Ln ...... 61 4.6 MOSFET(Q2) Turn on at Zero Voltage ...... 63 4.7 Rectifier (D3) Turn off at Zero Current ...... 63 4.8 Start Resonant Current under Different Frequencies ...... 65 4.9 Picture of the System Prototype ...... 66 4.10 Two Complementary PWM Signals from DSP ...... 67 4.11 Two Complementary PWM Signals from Driver IC ...... 67 4.12 MOSFET Switching Waveform ...... 68 4.13 The Voltage on the Secondary Side of the Transformer(yellow);PWM signal (blue) 69 4.14 DC Output Voltage ...... 69

vii ABSTRACT

LOW TOTAL HARMONIC DISTORTION (THD) RESONANT CONVERTER FOR COOKER MAG- NETRON POWER SUPPLY

Yang Zhou, M.S.T.

Western Carolina University (June 2016)

Director: Dr. Robert Adams

The traditional cooker magnetron power supply consists industrial frequency transformer, which is bulky, inefficient and with high harmonics distortion. There are numerous researchers who investigates magnetron power supply design with soft switching converter, in order to reduce weight and improve efficiency [7–10]. However, no investigation currently exists on harmonic distortion of traditional magnetron power supply, and very little research or analysis is done on harmonic distortion of new type of magnetron power supply. This project aims to investigate harmonic distortion of traditional magnetron power supply in the first phase. In the second phase, a novel design of and low harmonic distortion magnetron power supply is targeted.

viii CHAPTER 1: INTRODUCTION

1.1 Traditional Microwave Oven

In 1945, an engineer in Raytheon Percy Spencer discovered that the magnetron built in the war period can be a promising application for heating food [11], and then Raytheon invented the first commercially available microwave oven [12]. The most important component in microwave oven is the magnetron which works as the source of microwave power. The advent of the microwave oven makes the magnetron well-known and popular

1.1.1 Magnetron Characteristics

Figure 1.1 is a picture taken from a 2008 Emerson microwave oven, which shows the structure of the magnetron for microwave oven. The internal construction of the magnetron includes a cylindrical and an on a larger concentric circle, permanent axially produces the magnetic field to accelerate [13]. At start-up stage, the cathode filament is heated until the filament temperature rises up to the critical value, then the filament begins to emit electrons. Within the magnetic fluxes produced by two ring , the accelerated electrons make the anode cavities resonate and radiate [14].

Figure 1.2 represents the voltage vs. current characteristics of the magnetron. The magnetron has very high resistance when operates in non-oscillating range, and low resistance when operating in the oscillating range which is shown in Figure 1.2. When the voltage applied between the anode and the cathode exceeds 3.6 kV, the magnetron anode current starts to increase rapidly. However, when the voltage is lower than 3.6 kV [15], the resistance between anode and cathode is very high which is considered as ’OFF’ state.

1 Figure 1.1: Magnetron Structure

4000

Oscillation Area 3000

2000

Non−oscillation Area Magnetron Voltage [V]

1000

0 0.5 1 1.5 Anode Current [A]

Figure 1.2: Magnetron Voltage and Current

1.1.2 Traditional Power Supply of the Magnetron in Microwave Oven

The mainstream microwave ovens on the market are supplied by a traditional power supply which is shown in Figure 1.3 and Figure 1.4. The picture in Figure 1.3 is a traditional magnetron power supply taken from a 2008 made Galanz microwave oven. The circuit diagram of the traditional power supply is shown in Figure 1.4. 2 As shown in Figure 1.4, the magnetron power supply is fabricated by a line-frequency

transformer, a capacitor and a diode. The 120V-60Hz line voltage is boosted by a line-frequency

transformer. The output voltage of the transformer is rectified by a half-wave rectifier which is

composed of a capacitor and a diode.

5 4 3 2 1

Figure 1.3: The Picture of Traditional Magnetron Power Supply

2 1 D Anode 3 D T

120V AC

Cathode

Filament

C Figure 1.4: A Circuit Diagram of Traditional Magnetron Power Supply C 3

B B

A A

Title </p><p>Size Document Number Rev A <Doc> <RevCod</p><p>Date:Thursday, April 16, 2015 Sheet 11of 5 4 3 2 1 1.1.3 Advantages and Disadvantages of the Traditional Power Supply</p><p>The traditional magnetron power supply has many advantages. The circuit of the power supply is very simple as shown in Figure 1.4, which means the power supply can be cheap and reliable.</p><p>Therefore this kind microwave oven lasts for decades and can keeps its popular.</p><p>However, there are also several significant drawbacks with traditional microwave ovens:</p><p>First, the current distortion is significant [16]. The lab test was performed on a 2008 made</p><p>Emerson microwave oven as shown in the Table 1.1 and Figure 1.5. The total harmonic distortion</p><p>(THD) can be calculated using:</p><p> q 2 2 2 2 I2 I3 I4 I5 K THD + + + + (1.1) = I1 where In is the nth harmonic of the power supply current. K is a sum of all the other higher order harmonics. In this experiment, THD was shown to be 42.92% with K set to zero. In this experiment K was not zero and increased the THD to approximately 45%. That means the MW oven wastes 45% of the consumed energy. This level of THD in current can result in undesired effects in the power grid. At the same time, when the oven is turned on, creating many harmonics, it will make the current through the grid dirty, which will have deleterious effects on other equipment connected within the same power grid.</p><p>Table 1.1: Harmonic Results from Lab Test P PP Order PP PP I1 I2 I3 I4 I5 Value PP Decibels (dBA) 57.5 33.0 50.0 24.0 35.0 Scaled Current (A) 749.0 44.0 316.0 16.0 36.0</p><p>4 Figure 1.5: Input Current of MW (Microwave) Oven and Its Fast Fourier Transform</p><p>Secondly, when the user adjusts the output power, the power supply repeatedly turns on and off to control the total amount of output energy [8]. Continuous adjustment of power is not possible. Since the adjustment is not continuous, there will be numerous current shocks on the magnetron and transformer.</p><p>Thirdly, the traditional power supply system is very bulky. The weight of the transformer and capacitor in the Figure 1.3 is about 3kg.</p><p>Fourthly, the traditional power supply system creats significant audible noise. Since the current has a fundamental frequency of 60 Hz, it produces a physical <a href="/tags/Resonance/" rel="tag">resonance</a> which is in the human-audible sound range.</p><p>1.2 A New Magnetron Power Supply</p><p>To improve the efficiency and reduce the weight and volume of the magnetron power supply, switching mode magnetron power supplies are introduced. The output voltage of the power supply is up to 4kV. For hard-switching converters, the current and voltage spikes cause much switching noise and high switching loss. To solve the problem of noise and reduce the switching 5 loss, soft-switching resonant converters are developed [17].</p><p>1.2.1 LLC (Inductor-Inductor-Capacitor) Resonant Converter</p><p>The LLC resonant converter is a type of series-parallel converter. LLC resonant converters</p><p> combine characteristics from series converters and parallel converters. When the load or input</p><p> voltage have wide variations, it is easy to adjust the output power by changing the switching</p><p>5 frequency. It can achieve zero voltage switching4 (ZVS) across the operational range. Figure3 1.6 2 1</p><p> shows the LLC resonant network. Another advantage of the LLC topology is that the two <a href="/tags/Inductor/" rel="tag">inductors</a></p><p> in the resonant network shown in Figure 1.6 can be integrated into the transformer, including</p><p> the leakage inductance Lr and magnetizing inductance Lm [2].</p><p>Cr L1 D D</p><p>L2</p><p>Figure 1.6: LLC Resonant Network</p><p>1.2.2 A New Magnetron Power Supply Based on LLC Resonant Converter C C Figure 1.7 is the simplified main circuit of the proposed power supply system with resonant</p><p> circuit. This design is a modification from LLC converters which often are used to increase</p><p> power efficiency in many appliances [10,15]. In this study, the LLC network will be used to boost</p><p> the voltage rather than being used as a voltage step-down application. In this figure, a high</p><p> frequency resonant circuit will be applied before the transformer in the power supply system.</p><p>This resonant power supply is composed of an input rectifier bridge, switching bridge, resonant</p><p>6</p><p>B B</p><p>A A</p><p>Title <Title></p><p>Size Document Number Rev A <Doc> <RevCod</p><p>Date:Thursday, April 16, 2015 Sheet 11of 5 4 3 2 1 circuit, transformer and output rectifier.</p><p>Q1 D1 D3 VIN Lr Vsq C1 T Q2 R_Load D2 Lm C2 Cr D4</p><p>Figure 1.7: Simplified Main Circuit</p><p>The power supply system with resonant circuit in this research will have some main advantages as compared to traditional power supply.</p><p>Firstly, the resonant frequency can be up to 150 kHz which is much higher than 60 Hz in the traditional power supply system. Also, the output voltage can be adjusted to keep steady when the input sinusoidal voltage goes down periodically. Therefore the large capacitor can be replaced by a much smaller one. The smaller capacitor will result in a much smaller phase shift between voltage and current.</p><p>Secondly, the output power can be adjusted continuously, as opposed to a pulse output, because the voltage gain of the resonant circuit can be changed by changing the frequency of the switching signal on the IGBT (Insulated-gate Bipolar <a href="/tags/Transistor/" rel="tag">Transistor</a>) device. [18,19]</p><p>Thirdly, the IGBT devices in the switching bridge chop up the input line frequency voltage to be a much higher frequency voltage. Higher frequency voltages require a small-volume transformer if the same power is needed to be transferred. The output voltage filter capacitor can be much smaller too. So, the weight of the power supply system with resonant circuit may be significantly reduced.</p><p>Fourthly, as noted above, the frequency of the current is larger than 20 kHz which is beyond the range of human hearing. The noise of the traditional MW oven should disappear. 7 1.3 Other Studies on LLC Resonant Based Magnetron Power Supplies</p><p>The LLC resonant based magnetron power supply has been studied in one published paper [15].</p><p>The math derivations for the LLC converter with a voltage doubling rectifier is not completely correct in this paper. The IGBTs are adopted as <a href="/tags/Switch/" rel="tag">switches</a> in the LLC resonant converter, therefore the operation frequency range is around 30 kHz. The switching mode power supply with 1000</p><p>Watts output, the total harmonic distortion (THD) is not discussed in this paper or compared with the traditional Microwave oven. No investigations on the power efficiency and closed loop control methods are discussed in this paper.</p><p>In this thesis, switching devices will be replaced by <a href="/tags/MOSFET/" rel="tag">MOSFETs</a> with higher switching frequency which can help LLC resonant converters reach to a higher efficiency [2]. The total harmonic distortion (THD) will be investigated deeply and compared with traditional power supply, as well as the power efficiency and closed loop control methods.</p><p>8 CHAPTER 2: LLC BASED MAIN CIRCUIT ANALYSIS</p><p>2.1 Topology Selection</p><p>As analyzed in the last chapter, to reduce the weight of the transformer, improving the switching frequency decreases the size of passive components. However, a high switching frequency on power devices results in a large switching loss. Therefore the resonant and soft switching technique is a good choice. The soft switching technique improves the power density and efficiency.</p><p>Resonant converters, which have been investigated in-depth in the 1980s [20, 21], can achieve very low loss even when the resonant converter operates at a very high switching fre- quency. There are three typical resonant topologies, Series Resonant Converter (SRC), Parallel</p><p>Resonant Converter (PRC) and Series-Parallel Resonant Converter (SPRC).</p><p>2.1.1 Series Resonant Converter (SRC)</p><p>The circuit diagram of the SRC network is shown in Figure 2.1. The SRC network is a series combination of an inductor and a capacitor. The load is a voltage dividing part connected in series with the SRC network. Changing the input frequency will change the impedance of the</p><p>SRC network, and then consequentially change the load voltage. Since the load is connected in series with the network, the output voltage gain is always less than or equal to 1.</p><p>The AC voltage gain characteristic plot is shown in Figure 2.2. The SRC has three main weaknesses. Firstly, the range of output voltage is limited. The output voltage of the power supply used to power the magnetron needs to have a broad range in order to change the output microwave power. Secondly, it can be seen from the Figure 2.2 that at light load, the switching frequency needs to be very high to keep the output voltage regulated. Theoretically, the switching frequency has to be infinite at zero load. Thirdly, in this topology, the SRC network stores a lot of</p><p>9 5 4 3 2 1</p><p> energy, especially with a light load. The large inrush turn-off current on the <a href="/tags/Switch/" rel="tag">switch</a> is also a big</p><p> challenge. D D</p><p>Cr Lr</p><p>Source R_load</p><p>C Figure 2.1: Series Resonant Converter C</p><p>B B</p><p>Figure 2.2: SRC Voltage Gain [1]</p><p>10</p><p>A A</p><p>Title <Title></p><p>Size Document Number Rev A <Doc> <RevCod</p><p>Date:Friday, September 25, 2015 Sheet 11of 5 4 3 2 1 2.1.2 Parallel Resonant Converter (PRC)</p><p>The circuit diagram of the PRC network is shown in Figure 2.3.For the PRC, the resonant tank is</p><p> in series, similar to the SRC. The difference from the SRC is that the load is in parallel with the</p><p> resonant capacitor. The voltage gain characteristic plot is shown in Figure 2.4. The operation</p><p> area is much smaller comparing with the SRC. Similar to the SRC, the operation area of Zero</p><p>Voltage Switching is also on the right side of the resonant frequency (The ZVS operation area will</p><p> be discussed later).</p><p>The load is in parallel with the capacitor. Since the impedance of the resonant tank is</p><p>5 small [22], a big challenge4 is that the circulating current is very large3 at light load. Due to the 2 1</p><p>PC board trace resistance, the efficiency of the converter is too low to be used on a high power</p><p> application like the Microwave Oven. Similar to the SRC, the turn-off current through the switch</p><p> is also very large at light load. Since the SRC and PRC both only have one resonance, they require</p><p> a wide frequency shift in order to accommodate input and load variations.</p><p>D Lr D</p><p>Source R_load Cr</p><p>Figure 2.3: Parallel Resonant Converter</p><p>C C</p><p>11</p><p>B B</p><p>A A</p><p>Title <Title></p><p>Size Document Number Rev A <Doc> <RevCod</p><p>Date:Friday, September 25, 2015 Sheet 11of 5 4 3 2 1 Figure 2.4: PRC Voltage Gain [1]</p><p>2.1.3 Series-Parallel Resonant Converter (SPRC)</p><p>The typical Series-Parallel Resonant network is shown in Figure 2.5, and is also known as the LCC resonant converter. It combines advantages from both the SRC and PRC. In the normal operation region, the circulating energy is much smaller compared with the SRC and PRC [19]. As shown in</p><p>Figure 2.6, the operation region is still to the right side of the resonant frequency. Similarly to the SRC and PRC, it has a big problem dealing with input voltage variation. The conduction and switching losses will increase at high input voltage, which is fairly similar to PWM converter.</p><p>Changing the LCC resonant network to an LLC resonant network will shift the resonant frequency and will solve the problem of circulating energy [2]. The LLC network is shown in</p><p>Figure 2.7. There are many advantages of the LLC resonant converter. For example, comparing with the LCC topology which needs two independent <a href="/tags/Capacitor/" rel="tag">capacitors</a> that are expensive and increasing the size of the system, the two inductors of the LLC topology can be integrated into a transformer</p><p>12 [2]. This creates a very desirable result in which the ZVS operation can be completed over the entire operating range. As shown in Figure 2.8, the LLC can regulate the output voltage under wide variations of input voltage and load without changing the range of frequency. The LLC converter is a suitable topology for power adapters with high efficiency, providing a high and nearly constant efficiency throughout the complete load and input voltage range [23].</p><p>From the above discussion, the LLC topology will be adopted for this research as the topology of the magnetron power supply, since it can achieve soft-switching, while maintaining great efficiency.</p><p>Figure 2.5: LCC Series-Parallel Resonant Converter</p><p>Figure 2.6: LCC Resonant Converter Voltage Gain [1] 13 5 4 3 2 1</p><p>Cr Lr D D</p><p>Source Lm R_load</p><p>Figure 2.7: LLC Series-Parallel Resonant Converter</p><p>C 2 C</p><p>1.8 Qe=0.15</p><p>1.6</p><p>1.4 Qe=0.60 Qe=0.30</p><p>1.2</p><p>Qe=0.45 1 Mg</p><p>0.8</p><p>0.6 Qe=3.00 Qe=1.00</p><p>0.4 Qe=6.00</p><p>B 0.2 B</p><p>0 −1 0 1 10 10 10 fn ( Ln=6.5 )</p><p>Figure 2.8: LLC Resonant Converter Voltage Gain</p><p>2.2 Mathematical Derivation of Main Circuit Voltage Gain</p><p>The main circuit of the power supply is derived from the normal LLC topology. A voltage doubler</p><p> is adopted as the output network, in order to get a higher output voltage. Normally the LLC</p><p> topology is used on the voltage step-down application, but the power supply needs to boost the</p><p>A voltage in the proposed approach. A 14 Title <Title></p><p>Size Document Number Rev A <Doc> <RevCod</p><p>Date:Friday, September 25, 2015 Sheet 11of 5 4 3 2 1 Q1 D1 D3 VIN Lr Vsq C1 T Q2 R_Load D2 Lm C2 Cr D4</p><p>Figure 2.9: LLC Based Main Circuit</p><p>In the Figure 2.9, the DC (Direct Current) rail voltage Vin is the input voltage applied on the switching bridge. Q1 and Q2 are both high speed MOSFETs. In this application, they conduct alternately on a 50% duty cycle. Lr and Cr are part of the resonant network. In the actual circuit, Lr and Lm are integrated into the transformer as the leakage inductance and magnetizing inductance to reduce space and cost of extra components. A step-up transformer is connected to the resonant network. On the secondary side of the transformer, a rectifier doubles the voltage to satisfy the requirement of 4000V delivered to the magnetron. RLoad represents the magnetron’s impedance. As shown in Figure 2.15, Vsq is the switching node voltage which alternates between zero and Vin. The math derivation of the main circuit model is based on the First Harmonics</p><p>Analysis (FHA) [24]. The following mathmatical analysis does not consider any loss elements.</p><p>The FHA method extracts the fundamental harmonic of the square wave as an approximation.</p><p>D3 Io C1 Io1 T T Vo1 + R_Load Res Vo - C2 D4</p><p>Figure 2.10: Secondary Side Equivalent</p><p>15 The equivalent resistance referred to the transformer secondary side Res is shown in the</p><p>Figure 2.10. Res can be calculated using the Ohm’s law as follows:</p><p>1 Vo Vo1 (2.1) = 2 I 2 I (2.2) o = ∗ o1 Vo Res (2.3) = Io Vo1 RLoad (2.4) = Io1 1 2Vo1 1 Res RLoad (2.5) = 2Io1 = 4</p><p>The LLC resonant network has two resonant frequencies:</p><p>1 fo (2.6) = 2πpLr Cr 1 fp (2.7) = 2πp(L L )C r + m r</p><p>5 From the LLC based main circuit4 which is shown in Figure3 2.9, by replacing the switching2 node 1</p><p> with a square wave voltage source Vge , and referring the secondary side resistance Res to the</p><p> primary side resistance Re , the equivalent main circuit is obtained as Figure 2.11.</p><p>D Cr Lr D</p><p>+ + Lm Re Voe Vge - - + Ioe -</p><p>C C Figure 2.11: Equivalent Main Circuit</p><p>The switching bridge divides the DC input voltage into a square wave voltage, the Fourier</p><p> transform of the periodic square wave is:</p><p>4 1 1 x(t) (cos(ωt) cos(3ωt) cos(5ωt) ... ) (2.8) = π − 3 + 5 − | |</p><p>B 16 B</p><p>A A</p><p>Title <Title></p><p>Size Document Number Rev A <Doc> <RevCod</p><p>Date:Sunday, September 27, 2015 Sheet 11of 5 4 3 2 1 The DC input voltage VIN is applied on the resonant network for each half cycle. Therefore the voltage source Vge is a square wave which can be decomposed as:</p><p>1 4 Vge (t) VIN sin(ωt) (2.9) = 2 π p2 Vge RMS(Vge (t)) VIN (2.10) = = π</p><p>The fundamental harmonic of the output voltage Voe :</p><p>4 Voe (t) nVo sin(ωt φ1) (2.11) = π − 2p2 Voe RMS(Voe (t)) nVo (2.12) = = π</p><p>The equivalent output current Ioe is derived as:</p><p>V I V I (2.13) oe oe = o o π 1 Ioe Io (2.14) = 2p2 n</p><p>The equivalent load resistance Re is derived as:</p><p>2 Voe 8n Re 2 Res (2.15) = Ioe = π 1 Res RLoad (2.16) = 4 2n2 Re Rload (2.17) = π2</p><p>Reactances of Lr , Lm and Cr :</p><p>1 XCr , XLr ωLr , XLm ωLm (2.18) = ωCr = =</p><p>The resonant frequency fo is determined by:</p><p>1 2πfoLr (2.19) = 2πfoCr</p><p>The magnetizing current Im:</p><p>Voe 2p2 nVo Im (2.20) = ωLm = π ωLm 17 The circulating current in the resonant network Ir :</p><p> q I I 2 I 2 (2.21) r = m + oe</p><p>The Voltage gain of this main circuit Mg is calculated by using the voltage division method:</p><p>Voe j XLm Re Mg || (2.22) = V = (j X R ) j(X X ) ge Lm || e + Lr − Cr</p><p>The voltage gain Mg can be normalized as:</p><p> p L L /L , Q L /C /R (2.23) n = m r e = r r e 2 Ln fn Mg (2.24) = [(L 1)f 2 1] j[(f 2 1)f Q L ] n + n − + n − n e n The relationship between the input and output voltage can be expressed as:</p><p>1 VIN Vo Mg (fn,Ln,Qe ) (2.25) = n 2</p><p>2.3 Analysis of Main Circuit</p><p>In this section, the characteristics of the main circuit are discussed, including the utilization of the voltage gain, the resonant converter operation and the zero-voltage switching (ZVS).</p><p>2.3.1 Voltage Gain Analysis</p><p>The expression of voltage gain Mg has been derived. After the normalization, there are three elements involved, Qe ,Ln and fn. As suggested from the a TI handbook [2], the inductance ratio,</p><p>L L /L is normally in the range from 3 to 7. In this application, L is set as 6.5; the reason n = m r n will be explained later. Fixing the parameter Ln makes the voltage gain vs. frequency plot to be much more straightforward. The plot of Mg vs. normalized frequency fn is shown in Figure 2.12.</p><p>18 2</p><p>1.8 Qe=0.15</p><p>1.6</p><p>1.4 Qe=0.60 Qe=0.30</p><p>1.2</p><p>Qe=0.45 1 Mg</p><p>0.8</p><p>0.6 Qe=3.00 Qe=1.00</p><p>0.4 Qe=6.00</p><p>0.2</p><p>0 −1 0 1 10 10 10 fn ( Ln=6.5 )</p><p>Figure 2.12: M vs. L (L 6.5) g n n =</p><p>2</p><p>1.8 Qe=0.15</p><p>1.6 Qe=0.60</p><p>1.4 Qe=0.30</p><p>1.2</p><p>1 Mg Qe=0.45</p><p>0.8</p><p>0.6 Qe=3.00 Qe=1.00</p><p>0.4 Qe=6.00</p><p>0.2</p><p>0 −1 0 1 10 10 10 fn ( Ln=6.5 )</p><p>Figure 2.13: M vs. L (L 3.5) g n n =</p><p>With a given Ln and Qe , Mg presents a convex curve shape, and the operation region is recommended to be in the vicinity of the network’s resonant frequency. As shown in Figure 2.12 19 and Figure 2.13, Ln has been given as 6.5 and 3.5. Qe is a function of the load and the parameters of network. Mg presents a family of curves regarding to the change of Ln and Qe . Every curve goes through a same point (Ln, Mg =1). The voltage drop across Lr and Cr is zero at fn=1, since</p><p>XLr -XCr =0 at the resonant frequency point. Therefore the input voltage is applied directly on the load with a unity voltage gain.</p><p>When the Qe is fixed, such as Qe =0.5 shown in Figure 2.12 and Figure 2.13, decreasing Ln lifts the voltage gain and shrinks the curve. Since the voltage gain is lifted, this results in a better operation frequency band. In other words, it is easier to get an output voltage without shifting the operation frequency too much. For example, in Figure 2.12, the operating frequency range is widest for Mg between 1.1 and 1.4. However, a larger Ln results in a overall higher voltage gain and a higher start-current through the resonant network which might be beyond the current limitation of power devices.</p><p>The quality factor of the resonant network Qe is described in Equation 2.23. In the real design, both Lr and Cr are fixed, and Qe is only decided by the load. Increasing the load Re will increase the effect of Lm, since Re and Lm are parallel, and the distance between the two resonant frequency points will be increased. As observed in Figure 2.12, changing the load Re from 0 to , the corresponding peak voltage gain moves from unity to . ∞ ∞ From the above analysis, there are many considerations during the design process. The combination of fn, Qe and the shifting operation frequency makes the parameter selection full of compromises.</p><p>2.3.2 Operation at the Resonant Point (f 1) n = The typical waveforms on different parts of an LLC resonant converter at the resonant frequency</p><p>(f 1) are illustrated in Figure 2.15. In Figure 2.14, a capacitor C is added to be parallel with n = T</p><p>Q2 comparing to Figure 2.9(There is also a capacitor CT is parallel with Q1). CT is an equivalent capacitor which contains the switch’s output capacitance (Coss) and stray capacitance(Cstray).</p><p>20 CT needs to be considered during the transition between two switches.</p><p>C Coss C str ay (2.26) T = +</p><p>Figure 2.14: Main Circuit with Stray Capacitance</p><p></p><p></p><p> </p><p> </p><p></p><p>         </p><p>Figure 2.15: Operation of LLC Resonant Converter at f0 [2] 21 When the LLC resonant converter operates at the resonant point (f 1), a whole opera- n = tion cycle contains four stages which is shown in Figure 2.15. Vsq is the switching node voltage.</p><p>The analysis of one whole operation cycle is stated as below:</p><p> t t : At t , the switch Q1 turns on. C has been fully charged, and the switch node 0 ∼ 1 0 T voltage is equal to the input voltage. Ir =Im<0 at t=t0. Both Ir and Im increase after t0, from negative to positive. Ir is always larger than Im during this stage, a positive current presents on the transformer’s primary side. The diode D4 is forward biased, and charges C2. At this stage, the voltage on the magnetizing inductor Lm is clamped by the output voltage, thus Lm doesn’t resonate with Lr and Cr .</p><p> t t : At t , the switch Q turns off. C starts to discharge at t1 until the voltage on C 1 ∼ 2 1 1 T T decreases to zero. In other words, the switch node voltage equals to zero. I I 0 at t t . I r = m > = 1 r is still positive after Q1 is turned off. Ir can’t flow back to input voltage source, instead circulating in the resonant network. A positive current flows through the diode D2, the voltage on Q2 is zero and Q is ready for ZVS conduction. At t ,(I I ) is zero which means there is no current 2 1 r − m flowing through the transformer’s primary side. Lm participates into the resonant network. The resonant period becomes much larger, so that I and I decrease very slow during t t . r m 1 ∼ 2 t t : At t , the switch Q is softly turned on. C has been fully discharged, the switch 2 ∼ 3 2 2 T node voltage is zero. I I 0 at t t , and then both I and I begin to decrease from r = m > = 2 r m positive to negative along the resonant sinusoidal current wave. Im is always larger than Ir , thus a negative current presents on the transformer’s primary side. The diode D3 is forward biased, and charges C during this stage. The same as in the first stage t t , the voltage on L is 1 0 ∼ 1 m clamped by the output voltage, and the resonant network only contains Lr and Cr .</p><p> t t : At t , the switch Q turns off. I is negative and starts to charge C . The switch 3 ∼ 4 3 2 r T node voltage rises from zero to input voltage. The negative current Ir can’t circulate in the resonant network, instead flowing back to the input voltage source through the switch Q1. The negative current flows through the diode D1, the voltage on Q1 is zero and Q1 is ready for ZVS conduction. The same as in t t , L resonating with L and C results in a much longer 1 ∼ 2 m r r 22 resonant period.</p><p>2.3.3 Zero-Voltage Switching (ZVS)</p><p>Soft-switching is a major benefit of the LLC converter topology which significantly reduces switching loss. ZVS occurs when a switch device, such as a MOSFET,which turns on only when the drain-source voltage VDS is reduced to zero [25]. In this research, the way to achieve zero</p><p>VDS is to force a reversal current flowing through the MOSFET’s body diode when a positive gate signal is applied.</p><p>As analyzed before, such as in t t stage shown in Figure 2.15, because the switch 1 ∼ 2</p><p>Q1 turns off, the positive current keeps flowing, and makes the diode D2 forward biased and prepares conditions needed for achieving ZVS. After Q1 turns off, the current Ir remains positive for a while and then decreases to be negative. In other words, the current Ir lags the voltage applied on the resonant network which can be observed in Figure 2.15. The condition required to achieve lagging current is to make sure the input impedance, Zin (shown in Figure 2.15) is inductive. Cr L1</p><p>ZIN L2</p><p>Figure 2.16: LLC Network Input Impedance</p><p>23 Zin can be expressed in a polar form:</p><p>Z Z e jθ (2.27) IN = | IN |</p><p>θ is the phase angle between I and the input voltage. When θ 0, the input impedance Z r > IN is inductive. As discussed before, the angle between Ir and VIN is a function of switching frequency. As shown in Figure 2.12, each gain peak point corresponds to θ 0. These peak = points are connected by a red line in the Figure 2.12. A higher frequency results in a larger impedance presented on Lr , but a smaller impedance on Cr . Therefore the right side of the red line represents the inductive region. To achieve ZVS, the operation region has to be in the inductive region.</p><p>The equivalent capacitor CT which is parallel to the switch Q2 cannot be ignored. The energy stored in this capacitor determines the achievement of ZVS. Such as in the stage t t , 3 ∼ 4 after Q2 turns off, the negative Ir starts to charge CT . Only when CT is fully charged, Ir begins to</p><p>flow through the diode D1. Therefore the negative flowing energy in the resonant network needs to be large enough to make sure C can be fully charged during t t . T 3 ∼ 4</p><p>2.4 Design Implementation</p><p>The converter’s electrical specifications in this thesis are given as follows:</p><p>• Input voltage: 97 to 118 VDC</p><p>• Rated output power: 1000 W</p><p>• Output voltage: 4000 VDC</p><p>• Rated output current: 0.25 A</p><p>• Output voltage line regulation: <= 5%</p><p>• Efficiency ( VIN =108 V and I=0.25 A ) >= 90%</p><p>• Switching frequency (normal operation): 60 to 140 kHz 24 The input voltage is a 10% fluctuation from the nominal 108 V rectified grid voltage.</p><p>Design Steps:</p><p>1. Determine the Transformer Turns Ratio (n)</p><p>The theoretical turns ratio is computed as:</p><p> n (VIN/2)/(V /2) (108/2)/(4000/2) 0.027 0.025(1 : 40) (2.28) = o = = ≈ From the reference [26], the industry adjusted turns ratio is computed as:</p><p> p p n1 n L /(L L ) 0.027 6.5/(6.5 1) 0.025 (2.29) = m m + r = + =</p><p>2. Determine the voltage gain from the DC rail to the normalized secondary voltage (Mg _min and Mg _max):</p><p>M _min nV o_min/V in_max n[4000(1 5%)]/[108(1 10%)] 0.80 (2.30) g = = − + = M _max nV o_max/V in_min n[4000(1 5%)]/[108(1 10%)] 1.08 (2.31) g = = + − =</p><p>To implement a 10% safety margin for an overload current capability of 110%, Mg _max is adjusted from 1.08 to 1.08*110% = 1.19.</p><p>3. Calculate the equivalent load resistance (Re )</p><p>R 2 n2/(π2) R 2 0.0272/(π2) 16000 2.36Ω (2.32) e = ∗ ∗ L = ∗ ∗ =</p><p>4. Select the Ln and Qe</p><p>Based on the Spice simulation in Chapter 4, Ln and Qe are selected as 6.5 and 0.4. From Fig- ure 2.12, the corresponding peak of the voltage gain Mg is 1.25, which satifies the required Mg maximum of 1.19.</p><p>5. Calculate Resonant Circuit Parameters</p><p>The resonant parameters, Cr , Lr and Lm, are determined by Equations 2.19 and 2.23. A switching frequency of 80 kHz is selected as the series resonant frequency fo. 1 1 Cr 2.1µF (2.33) = 2 2π Q f R = 2 2π 0.4 80kHz 2.36 = ∗ ∗ e ∗ o ∗ e ∗ ∗ ∗ ∗ 1 1 Lr 1.88µH (2.34) = (2π f )2 C = (2π 80kHz)2 2.1µF = ∗ o ∗ r ∗ ∗ L L L 1.88µH 6.5 12.27µH (2.35) m = n ∗ r = ∗ = 25 CHAPTER 3: HARDWARE DESIGN</p><p>In this Chapter, transformer design, component selection, MOSFET driver IC and protec- tion circuit will be discussed in detail. The signal <a href="/tags/Processor_(computing)/" rel="tag">processor</a> is selected as TI 2000 DSP controller.</p><p>3.1 Integration Transformer Design</p><p>As discussed in Chapter 2.3, the LLC resonant topology has many advantages. One of these advantages is that the LLC contains two inductors which can be integrated into the transformer.</p><p>Therefore this study will use the existing inductors in the transformer as part of LLC implemen- tation. Thus the leakage inductance and magnetizing inductance of the transformer can be effectively utilized.</p><p>The transformer is a device which can provide energy storage and delivery, current filter- ing and electrical isolation. To achieve high power density of the power supply, the transformer design is one of the most key elements. There are many ways to reduce the loss and improve the power density. Magnetic integration is one of the methods that has been studied recently, and applied into real products [27]. The transformer design will be shown as following step by step.</p><p>3.1.1 The List of Transformer Parameters</p><p>Input : 54V,20A</p><p>Output1 : 2000V,0.5A</p><p>Output2 : 7V,0.5A</p><p>Topolog y : Hal f Br idge − Switching Freq : 80kHz</p><p>MaxCore Loss(Pclim) : 2.0W 26 (22/24) FERRITES</p><p>Mn-Zn Large Size <a href="/tags/Ferrite_(magnet)/" rel="tag">Ferrite</a> for High Power Material List of PC40</p><p>3.1.2 Core Selection</p><p>FerriteCore cores loss are the vs. most temperature often used in switched characteristics mode power supply design. The relative permeability µr of ferrite is between 1500-3000. Ferrite materials are popular because of their 10000 10000 lower cost andTemp.23°C lower loss as compared with powdered metal materials; Ferrite materials have the Temp.40°C disadvantage of a lower saturation flux, however in high frequency applications, the required 1000 1000 saturation) flux density is usually very low. In this thesis, Mn-Zn ferrites are chosen as the(21/24) core ) 3 3</p><p> material.m FERRITES TDK Corporation provides a list of large size Mn-Zn ferrites for high power [3]. Ferrite m 100 100 PC40Mn-Zn from TDK Large is selected Size Ferrite as the core for material. High Power Figure 3.1Material gives the keyList characteristics of PC40 of PC40, (kW/ (kW/ and corecv loss vs. temperature characteristics is shown Figure 3.1. 300mT cv 300mT MATERIALP CHARACTERISTICS 250mT P 250mT Initial 10Curie Saturation Remanent Coercive Core loss Electrical Approximate Thermal Thermal Specific Bending200mT Young’s Magnetos 10 200mT permeability temperature magnetic flux flux density force resistivity density expansion conductivity heat strength modulus triction density dapp coefficient i Tc Bs Br Hc Pcv  (kg/m3)  Cp b3 150mTE s 150mT (°C) (mT) (mT) (A/m) (kW/m3) ( • m) 103 (1/K) (W/mK) (J/kg • K) (N/m2) (N/m2) H=1194A/m H=1194A/m H=1194A/m B=200mT 10–6 107100mT1011 10–6 100mT 25kHz 100kHz 50mT 50mT 23°C 1 23°C 100°C 23°C 23°C 90°C 100°C 100°C 1 10 100 1000 10000 10 100 1000 10000 2300 >200 500 380 125 15 64 70 420 6.5 4.8 12 5 600 9 1.2 –0.6 Frequency (kHz) Frequency (kHz) Figure 3.1: PC40 Material Characteristics [3]. Core loss vs. temperature characteristics(Typ.) Saturation magnetic flux density vs. temperature characteristics(Typ.)</p><p>900 700 800 600 10000700 10000 500</p><p>) 600</p><p>3 Temp.60°C Temp.40°C 100kHz-200mT 500 ) 400 kW/m mT ( 400 ( s cv</p><p>B 300 P 300 200 200 1000 25kHz-200mT 1000 100 100 ) ) 0 3 0 20 40 60 80 100 120 0 3 0 50 100 150 Temperature(°C) Temperature(°C) m m 100 100 Initial magnetic permeability vs. temperature Magnetic permeability vs. frequency characteristics(Typ.) (kW/ (kW/ characteristics(Typ.) cv 300mT cv 300mT 5000 4000 P Temp.: 23°C P Hm=0.4A/m 250mT 250mT 4000 10 10 3000 200mT 200mT 3000 150mT 150mT ” i</p><p>μ μ , μ 2000 ’ ’ 100mT 100mT 2000 μ</p><p>50mTμ” 50mT 1000 1 1000 1 f=1kHz Hm=0.4A/m10 100 1000 10000 10 100 1000 10000 0 0 100 200 300 0 10 100 1000 10000 Temperature(°C) Frequency (kHz) Frequency(kHz) Frequency (kHz)</p><p>Figure 3.2: PC40 Core Loss vs. Freq at 60 Hz [3].</p><p>27 10000 10000 Temp.90°C Temp.100°C</p><p>1000 1000 ) ) 3 3 m m 100 100</p><p>(kW/ Please be sure to request delivery specifications that provide further details on the features and specifications of the products for proper and safe use. (kW/ Please note that the contents may change without any prior notice due to reasons such as upgrading. cv 300mT cv 300mT P P 20141203 / ferrite_mn-zn_material_characteristics_en.fm250mT 250mT 10 200mT 10 200mT 150mT 150mT 100mT 100mT 50mT 50mT 1 1 10 100 1000 10000 10 100 1000 10000 Frequency (kHz) Frequency (kHz)</p><p>10000 Temp.120°C</p><p>1000 ) 3 m 100 (kW/</p><p> cv 300mT P 250mT 10 200mT 150mT 100mT 50mT 1 10 100 1000 10000 Frequency (kHz)</p><p>Please be sure to request delivery specifications that provide further details on the features and specifications of the products for proper and safe use. Please note that the contents may change without any prior notice due to reasons such as upgrading.</p><p>20141203 / ferrite_mn-zn_material_characteristics_en.fm There are many ways to estimate the size of the core. The Area Product (’AP’) method is</p><p> adopted in this transformer design [26]. The following formula gives an estimation of the area</p><p> product required: PO AP AW AE (3.1) = = K B f 4 0 where:</p><p>Po Power Output inWatts = ∆B Flux Density Swing (Per C ycle),Tesl a 90 Product Specifications= (Mn-Zn Ferrite) f MainOperating Frequency in Hz 0 = K 0.014(Forward converter ) = 0.017(Br idge, Hal f Br idge) = Type : EE/EEL Cores</p><p>A diagram of the EE core is shown below in Figure 3.3. EE cores are less expensive, and Ordering Code:have Shape: the advantage of a simple bobbin winding. In this thesis, the EE shape will be adopted as the core shape.</p><p>P4 EE8.8 G□</p><p>Material Core Size Gapped AL Value 材質 品名</p><p>Figure 3.3: EE Core Diagram [4] 28</p><p>■ DIMENSIONS AND EFFECTIVE PARAMETERS</p><p>DIMENSIONS (mm) EFFECTIVE PARAMETERS</p><p>-1 2 3 CORES ABCDEFC1(mm ) Le(mm) Ae(mm )Ve(mm ) Wt(g/set) EE4.2 4.35 ± 0.10 1.35 ± 0.05 1.35 ± 0.10 1.20 ± 0.10 3.15 ± 0.10 0.85 ± 0.05 4.71 7.04 1.49 10.49 0.11 EE5.0 5.25 ± 0.10 2.66 ± 0.07 1.95 ± 0.05 1.35 ± 0.05 3.80min 1.98 ± 0.07 4.70 12.50 2.66 33.30 0.24</p><p>+ 0.08 + 0.08 + 0.20 + 0.08 EE6.3 6.30 ± 0.25 2.82 - 0.07. 2.00 ± 0.15 1.32 - 0.07. 3.60 - 0.00. 1.92 - 0.07. 3.64 12.13 3.33 40.39 0.28 EE8.0/5.0 8.00 ± 0.15 5.00 ± 0.08 5.00 ± 0.15 2.90 ± 0.10 5.31 ± 0.15 3.50 ± 0.08 1.48 20.93 14.16 296.37 1.50 EE8.1 8.10 ± 0.20 7.00 ± 0.15 3.70 ± 0.15 1.85 ± 0.15 6.10 ± 0.20 5.75 ± 0.15 4.12 30.45 7.39 225.03 1.16 EE8.3A 8.30 ± 0.20 4.00 ± 0.10 3.90 ± 0.10 2.15 ± 0.15 6.30 ± 0.20 3.00 ± 0.10 2.41 19.33 7.98 154.42 0.76 EE8.3A-1 8.30 ± 0.20 4.00 ± 0.10 3.90 ± 0.10 2.15 ± 0.15 6.30 ± 0.20 3.00 ± 0.10 2.41 19.33 7.98 154.42 0.76 EE8.3B 8.30 ± 0.30 4.15 ± 0.10 1.85 ± 0.15 1.85 ± 0.15 6.00min 3.13 ± 0.10 4.53 19.95 3.67 73.22 0.36 EE8.3B-1 8.30 ± 0.30 4.00 ± 0.10 1.85 ± 0.15 1.85 ± 0.15 6.00min 3.00 ± 0.10 5.32 19.42 3.65 70.89 0.35 EE8.3D 8.30 ± 0.20 4.00 ± 0.10 3.90 ± 0.10 1.85 ± 0.15 6.15 ± 0.20 3.00 ± 0.10 2.50 19.37 7.74 149.92 0.76 EE8.6 8.60 ± 0.30 4.65 ± 0.10 3.65 ± 0.15 1.85 ± 0.20 6.30min 3.55min 2.99 22.02 7.37 162.29 0.87 EE8.8 8.80 ± 0.20 6.00 ± 0.20 2.80 ± 0.10 2.80 ± 0.10 6.00 ± 0.15 4.50 ± 0.10 3.23 25.74 7.95 204.60 1.32 EE8.8A 9.00 ± 0.40 4.00 ± 0.10 1.90 ± 0.10 1.90 ± 0.10 5.20 ± 0.15 2.19 ± 0.16 3.13 15.58 4.98 77.65 0.52 EEL8.8 8.80 ± 0.20 8.50 ± 0.10 2.80 ± 0.10 2.80 ± 0.10 6.00 ± 0.15 7.20 ± 0.10 4.67 36.22 7.75 280.70 1.41 EE9.0 9.00 ± 0.20 6.15 ± 0.20 2.80 ± 0.10 2.80 ± 0.10 6.30 ± 0.15 4.65 ± 0.10 3.39 26.58 7.83 208.23 1.06 + 0.15 + 0.15 EE9.3 9.30 ± 0.20 6.20 - 0.10. 2.80 ± 0.10 2.80 ± 0.10 6.60 ± 0.10 4.70 - 0.10. 3.47 27.16 7.84 212.87 1.04 EE10 10.20 ± 0.20 5.70 ± 0.10 4.75 ± 0.15 2.45 ± 0.15 7.70min 4.20 ± 0.15 2.13 26.00 12.00 323.00 1.60 EE10/10 10.20 ± 0.20 5.50 ± 0.10 9.85 ± 0.15 2.40 ± 0.15 7.80 ± 0.20 4.30 ± 0.10 1.11 26.36 23.64 623.10 3.32 EE10A 10.00 ± 0.20 6.60 ± 0.20 2.70 ± 0.10 2.80 ± 0.10 7.30 ± 0.15 5.00 ± 0.15 3.80 29.08 7.66 222.75 1.12 EE12 12.00 ± 0.15 3.20 ± 0.10 6.50 ± 0.10 3.10 ± 0.10 8.90 ± 0.15 1.80 ± 0.10 0.92 17.60 19.18 337.57 1.70 EE12.8-1 12.80 ± 0.25 12.00 ± 0.15 3.50 ± 0.13 3.65 ± 0.10 8.80 ± 0.25 10.00 ± 0.15 3.81 51.20 13.43 687.80 3.38 + 0.00 + 0.30 EE12.9/10 12.95 ± 0.30 6.50 - 0.15. 9.80 ± 0.20 3.55 ± 0.15 9.15 ± 0.25 4.50 - 0.00. 0.80 29.57 36.80 1088.00 5.34 EE12.9A 12.90 ± 0.30 6.85 ± 0.15 1.80 ± 0.20 6.00 ± 0.10 9.40 ± 0.25 4.50 ± 0.30 3.54 27.43 7.75 212.58 1.28 + 0.00 EE13 13.00 ± 0.30 6.00 ± 0.20 6.15 ± 0.15 2.95 - 0.35. 10.50 ± 0.30 4.65 ± 0.15 1.64 28.00 17.00 480.00 2.38 EEL14 14.05 ± 0.25 15.75 ± 0.15 3.50 ± 0.15 4.55 ± 0.15 9.25 ± 0.20 12.25 ± 0.15 3.64 62.06 17.06 1058.68 5.42 According to the Equation 3.1, the minimum required area product can be calculated by specifying the required output power:</p><p>1000 AP 39,993.0 cm4 (3.2) = 0.017 0.26 80 = ∗ ∗ The core size is selected as EE42/21/15, which has an area product as 49484 cm4 and satisfies the area product requirement [4].</p><p>3.1.3 Loss Limited Flux Swing</p><p>The core loss is mainly determined by the frequency and the flux swing. The operation frequency is 80 kHz. The core loss per cm3 is required to find the maximum flux swing. The core loss per cm3 is calculated as: Pclim 2 W 115.6 mw/cm3 (3.3) V e = 17.3 cm3 = At the operating frequency, the peak flux density is found in the core loss curve. Doubling the peak to obtain the peak flux density swing B(At 115.6 mw/cm3 and 80 kHz): 4</p><p>B 2 130 mT 0.26 Tesl a (3.4) 4 = ∗ =</p><p>3.1.4 Primary and Secondary Turns Calculation</p><p>Using Faraday’s Law, the number of primary turns N1 is calculated as:</p><p>Z N1 Edt/ φ V in Ts (3.5) = 4 = ∗ naV 0 0.025 2000 N1 o ∗ 6.75 (3.6) = f s B Ae = 80k 0.26 178 10 6 = 4 ∗ ∗ ∗ − Rounding N1 to an integer, thus N1 7. Recalculate the flux swing and core loss at 7 turns: = 6.75 B(7tur ns) 0.26T 0.25 Tesl a (3.7) 4 = ∗ 7 =</p><p>From the core loss curve, the core loss at the amplitude of 0.25T/2 is 110mW /cm3 V e: ∗</p><p>Core Loss(real) 110 17.3 mW 1.9 W atts (3.8) = ∗ = 29 The numbers of secondary turns N2 and N3:</p><p>N1 7 N2 280 (3.9) = na = 0.025 = N3 1 (3.10) =</p><p>3.1.5 Define the Winding Structure</p><p>The skin depth, Dpen, is the distance from the conductor surface to where the current density is</p><p>37% of the surface current density. The nominal depth of penetration for a conductor can be calculated using page 58 of [28]: s ρ 7.6 Dpen 0.269mm (3.11) = πµ0µr f = p80k =</p><p>Where:</p><p>ρ is the resistivity at 100◦C in Ω m − 8 ρ 2.3 10− Ω m f or copper = ∗ − f isthe frequencyinHz</p><p>µ is the absolute magnetic permeability of the conductor</p><p>The absolute magnetic permeability µ µ µ = 0 ∗ r 7 µ 4πx10− H/m 0 =</p><p>According to US <a href="/tags/Wire/" rel="tag">wire</a> gauge table, a radius of 0.21mm is selected as Dpen, In order to reduce the</p><p>AC resistance, the wire radius must be less than the calculated skin depth Dpen. According to US wire size table, a value of 0.21 mm is selected as the wire radius. The cross-sectional area Aw of the conductor is:</p><p>A π Dpen2 π 0.212 0.138 mm2 (3.12) w = ∗ = ∗ = The cross-sectional area of AWG 26 wire is 0.138 mm2 which satisfies the penetration require- ment. Therefore AWG 26 wire is selected as the winding wire on both sides of the transformer.</p><p>2 The recommendation of the maximum RMS current operated in copper wire Idc is 450A/cm 30 limited by heat dissipation. The RMS current flows in the primary side Ip and in the secondary side Is are:</p><p>Ip 1000W 110%/54V 20.4A (3.13) = ∗ = Is 1000W 110%/2000V 0.55A (3.14) = ∗ =</p><p>For the primary side and secondary side, the required total cross-sectional areas Ap _Total and</p><p>As_Total are calculated as:</p><p>Ip 2 Ap _Total 4.8 mm (3.15) = Idc = Is 2 As_Total 0.129 mm (3.16) = Idc =</p><p>To avoid the high AC resistance while handling large currents, many <a href="/tags/Wire/" rel="tag">wires</a> will be twisted in parallel for each turn. The required parallel numbers in each turn of N1,N2,N3 are calculated by dividing the total cross-sectional area by the cross-sectional area of AWG 26 wire. Therefore the N1,N2 and N3 windings will have 40,1 and 6 individually wires, respectively within each winding. The resulting winding structure is shown in Figure 3.4:</p><p>N2 N1 1 turn 7 turns 280 turns 4+3 20*14</p><p>Gap</p><p>Figure 3.4: The Transformer Winding Structure.</p><p>31 3.1.6 The Real Designed Transformer</p><p>The transformer is custom made in Xingchuangli,Ltd in GuangDong, China. The pictures are followed as in Figure 3.5:</p><p>Figure 3.5: The Real Transformer.</p><p>The leakage inductance Lr and the magnetizing inductance Lm of the transformer is tested on a bench LCR meter. By applying signals with different frequencies, the following table is obtained:</p><p>Table 3.1: Lr and Lm Test Results</p><p>Freq(kHz) 0.1 1 10 100 200 Lr (µH) 28.6 3.2 2.7 2.6 2.7 Lm (µH) 9,400 5,700 99.5 14.7 -24.3</p><p>As seen from Table 3.1, the Lr and Lm at 100 kHz are 2.6µH and 14.7µH,respectively. The ratio Ln Lm/Lr 5.65 = =</p><p>3.2 EMI Filter, Input Rectifier and Output Rectifier Design</p><p>In this section, the input and output configurations will be discussed in detail.</p><p>32 3.2.1 EMI Filter</p><p>The function of the EMI (Electromagnetic Interference) filter that will be installed at the AC input is to reduce high frequency noise that may cause interference with other devices. There are two main sources of noise that need to be eliminated. These are common mode noise and differential mode noise. An EMI filter normally consists of capacitors and inductors, therefore the EMI filter is bi-directional and passive. The EMI filter is shown in Figure 3.6. The EMI filter includes a protection <a href="/tags/Fuse_(electrical)/" rel="tag">fuse</a>, common mode choke, and filtering capacitor.</p><p>Figure 3.6: EMI Filter</p><p>Since the circuit must accommodate a 10 ampere line current, a 20 ampere fuse is selected to provide short circuit protection. Two inductors with the same number of turns and the opposite direction are wound on the same <a href="/tags/Ferrite_core/" rel="tag">ferrite core</a>. These two inductors and the core form a common mode choke. The common mode choke can reduce the common mode noise.</p><p>Because the common mode signal has the same direction, this builds two identical magnetic</p><p>fields in the ferrite core that will be added together to form a large magnetic field. The magnetic</p><p>field increases the impedance in the path of common mode noise. For the normal line current</p><p>flow through the common mode choke, there is no effect because two magnetic fields with the opposite direction cancel each other.</p><p>The capacitors including Cx , CY 1 and CY 2 can provide a low impedance path to divert the high frequency input noise, either into the ground, or into the power source. The capacitor</p><p>Cx installed between two input lines can absorb the noise between two lines which is known as</p><p>33 differential mode noise. CY 1 and CY 2, which are both connected to the ground, can be used to eliminate the noise between line and the ground.</p><p>3.2.2 Input Rectifier</p><p>The power source of the resonant converter is the general-purpose alternating-current (AC) power supply, which is 120 volts AC in United States. The 120 volts will be rectified by a four- diode bridge, and followed by an L-C filter in order to smooth the sinusoidal waves especially at the case of a light load. As shown in the Figure 3.7, the inductor L and the capacitor C form a low pass filter which sets a cut-off frequency point, and only allows low frequencies to pass. The values of the inductor and the capacitor are selected as 2 mH and 5uF . The cut-off frequency fc can be calculated as:</p><p>1 1 fc p 1591.5Hz (3.17) = 2πpLC = 2 π 2mH 5µF = ∗ ∗ ∗</p><p>Figure 3.7: Input Filter</p><p>3.2.3 Output Rectifier</p><p>The circuit is designed to provide an output voltage as high as 4000 Volts. The high voltage is a big challenge for designing the transformer with the concern of electricity isolation. A voltage doubler is adopted as the output rectifier which is shown in Figure 3.8, in order to reduce the output voltage of the secondary side of the transformer. A high voltage, fast recovery diode is required as the rectifier diode. In this design, the low loss diode UX-F5B with a peak reverse 34 voltage of 8 kV is chosen. The value of the output filter capacitor can be estimated assuming a</p><p>10% voltage drop is allowed. The average output voltage is 4000 V, and the current is equal to</p><p>P/Vout =0.25 A. The equation of the capacitor charging balance is:</p><p>V C I t (3.18) 4 ∗ = ∗</p><p>V 4000/2 10% 200V . t is the half switching cycle(fo 80kHz),t 6.25µs. Then the 5 4 4 3= ∗ = 2 = 1 = capacitance is calculated as:</p><p>6.25µs 0.25A C ∗ 7.8nF (3.19) = 200V =</p><p>D A 10nF film capacitor with a 3000 volt rating is selected as the output filter capacitor.D Q1 D1 D3 VIN Lr C1 T Q2 R_Load D2 Lm C2 C Cr D4 C</p><p>Figure 3.8: Output Rectifier</p><p>3.3 Main Circuit Design</p><p>The main circuit design includes the design of MOSFET bridge, resonant network and their</p><p>B B component selection.</p><p>3.3.1 MOSFET Bridge Selection, Loss Calculation, Heat Sink Selection</p><p> a).MOSFET Bridge selection:</p><p>The most important parameters for MOSFET selection include Drain-Source Breakdown Voltage</p><p>(VDS), Continuous Drain Current (ID ), Drain-Source On-State Resistance (RDS(on)), Total Gate</p><p>A A Charge (Qg ) and Rise time (tr ). The MOSFET bridge and LLC network is shown in Figure 3.9. Title <Title> 35</p><p>Size Document Number Rev A <Doc> <RevCod</p><p>Date:Friday, September 25, 2015 Sheet 11of 5 4 3 2 1 The maximum voltage applied across Q1 is Vrec when Q2 is on. Vrec is the RMS value</p><p> of the rectified grid voltage which is around 108 V. The current, IDS(on), flowing through the</p><p>MOSFET (Q1 or Q2) is equal to the circulating current, Ir , in the resonant network. Ir is derived</p><p> as the Equation 2.21. Referring back to the equivalent main circuit in Figure 2.11, based upon the</p><p> calculation of Lm, Lr in Equations 2.35 and 2.34. Im and Ioe can be calculated using Equations</p><p>3.21 and 3.22:</p><p>2p2 n Vo 2p2 0.025 2000V Im ∗ ∗ ∗ ∗ 7.3A (3.20) = π ω L = π 2π 80kHz 12.27µF = ∗ ∗ m ∗ ∗ ∗ π Io π 0.25A Ioe ∗ ∗ 22.2A (3.21) = (2p2 n) = (2p2 0.025) = ∗ ∗</p><p>Thus,</p><p> q p I I I 2 I 2 7.3A2 22.2A2 23.4A (3.22) r = DS(on) = m + oe = + =</p><p>5 The peak value of Ir is: 4 3 2 1</p><p>I I p2 33.0A (3.23) r _peak = r ∗ =</p><p>D D Q1 D1 D3 Vrec Lr C1</p><p>Q2 R_Load D2 Lm T C2 C Cr D4 C</p><p>Figure 3.9: MOSFET Bridge and LLC network 36</p><p>B B</p><p>A A</p><p>Title <Title></p><p>Size Document Number Rev A <Doc> <RevCod</p><p>Date:Monday, May 23, 2016 Sheet 11of 5 4 3 2 1 Table [ref from datasheet]. Key Performance Parameters of IPW60R041P6 Parameter Value Unit </p><p>VDS @ Tj,max(Drain-Source voltage) 650 V </p><p>RDS(on)@ Tj,125OC (Drain-Source on-state resistance) 85 mΩ Qg(Gate charge total) 170 nC </p><p>VDF(Diode forward voltage) 0.9 V ID (Continuous drain current)@150 49.0 A IDSS(Zero gate voltage drain current) 10 μA Eoss@100V (Coss stored energy) 7.2 μJ Ptot (Maximum power dissipation) 481 W tr(Switching rise time) 27 ns tf(Switching fall time) 5 ns td(off)( Turn-off delay time) 90 ns </p><p>3.1.2 MOSFETTable loss 3.2:calculation Key Performance Parameters of the IPW60R041P6</p><p>The calculation of power loss in the MOSFET is critical for choosing or designing a heat sink, and also TM Thefor evaluating model the IPW60R041P6 power efficiencyMOSFET of the power which supply. There is from are many Infineon factors Coolcontributing MOS to theP 6 series is selected.power Table loss 3.2 on MOSFET. lists some The key power performance loss can be categorized parameters into three of thistypes MOSFETof loss, quiescent model. loss, b).MOSFET switching loss, diode loss. loss calculation: Quiescent loss includes the conduction loss (Pon) during the on-state and the cut-off loss (Poff) during The calculation of power loss in the MOSFET is critical for choosing or designing a heat sink, and the off-state. Pon is dissipated by the resistive element RDS(on). The conduction loss Pon at 125 Celsius also for evaluatingjunction temperature the power is calculated efficiency as: of the power supply. There are many factors contributing</p><p>Pon = IDS(on)^2* (RDS(on) )@ Tj,125^(o)) /2 = 23.4^2*(0.085)/2=23.27 Watts to the power loss in the MOSFET. The power loss can be categorized into three types of loss, The reason for dividing 2 in the formula of Pon is the two MOSFETs conduct alternatively with a 50% quiescentduty loss, cycle. switching The cut-off loss,loss Poff diode is caused loss. by the leakage current when the MOSFET is off. Poff=VDS(off)*IDSS*/2=108*10*10-6/2=0.00 Watts QuiescentVds(off) is the loss voltage includes applied the to the conduction MOSFET when loss it (isPon off. V) duringDS(off) is theequals on-state to Vrec shown and the in cut-off loss</p><p>Fig.[ MOSFET Bridge and LLC network]. Poff is negligible comparing to Pon. (Po f f ) during the off-state. Pon is dissipated by the resistive element RDS(on). The conduction The contributions to switching loss include the energy lost during turn-on transition Poff_on, the loss Pon at 125◦C junction temperature is calculated as: energy lost during turn-off transition Pon_off, and the energy PDS used to charge drain-source capacitance (also referred2 to as output capacitance, Coss).2 As discussed in Chapter 2.3, the body diode Pon IDS(on) RDS(on)/2 23.4 (0.085Ω)/2 23.27 W atts (3.24) is forward biased when= the switch∗ is turning on.= Therefore∗ there is no crossover= loss due to the fact that the voltage drop between source and drain is 0 during the turn-on transition. The reason for dividing by 2 in the formula for Pon is that the two MOSFETs conduct alternatively Poff_on=0 with a 50%Turn-off duty transition cycle. Pon_off The cut-off is still lossexisting.Po fThe f is turn caused-off transition by the waveform leakage in current the worst whencase is shown the MOSFET is off. as Fig.[] The lost energy is the total crossover product area which can is calculated as: Pon_off=1/2* VDS* IDS(on) *(td(off)+tf)*fs = 1/2*108*23.4*(90+5)*10-9*80000 = 9.606 Watts Po f f VDS(o f f ) IDSS/2 108 10 10− /2 0.00 W atts (3.25) = ∗ = ∗ ∗ =</p><p>VDS(o f f ) is the voltage applied to the MOSFET when it is off. VDS(o f f ) is equals to Vrec shown in Figure 3.9. Po f f is negligible comparing to Pon. 37 The contributions to switching loss include the energy lost during turn-on transition</p><p>Po f f _on, the energy lost during turn-off transition Pon_o f f , and the energy PDS used to charge drain-source capacitance (also referred to as output capacitance, Coss). As discussed in</p><p>Chapter 2.3.2, the body diode is forward biased when the switch is turning on. Therefore there is no crossover loss due to the fact that the voltage drop between source and drain is 0V during the turn-on transition. Thus,</p><p>Po f f _on 0 (3.26) =</p><p>VDS</p><p>IDS</p><p> td(off) tf</p><p>Figure 3.10: Turn-off Transition Waveform</p><p>Turn-off transition Pono f f is still existing. The turn-off transition waveform in the worst case is shown as Figure 3.10 The lost energy is the total crossover product area which can be calculated as:</p><p>Pon_o f f 1/2 V I [td(o f f ) t f ] f s (3.27) = ∗ DS ∗ DS(on) ∗ + ∗ 1/2 108V 23.4A (90 5)ns 80kHz 9.60 W atts (3.28) = ∗ ∗ ∗ + ∗ =</p><p>The energy for one charging of Coss under a specific VDS (400V) value is given in IPW60R041P6 datasheet as Eoss, and is shown in Table 3.2. PDS is calculated as:</p><p>6 P Eoss f s 7.2 10− j 80kHz/s 0.58 W atts (3.29) DS = ∗ = ∗ ∗ =</p><p>38 Diode loss includes the forward conduction loss Pd_f and the reverse recovery loss Pd_re. Pd_f is calculated as:</p><p>Pd_f 1/2 I V t f s 1/2 23.4 0.9 0.01 0.11 W atts (3.30) = ∗ F ∗ DF ∗ x ∗ = ∗ ∗ ∗ =</p><p>As discussed in Chapter 2.3.2, the diode conducts only during the transition between two MOSFETS. IF is the resonant current flowing through the diode during the transition time.</p><p>The transition time (deadband time) is less than 1% of the switching cycle. In the transition</p><p>1 period, the resonant current is approximately set as 2 Ir . The conduction time tx in one duty cycle multiplied with the frequency fs is the total conduction time in one switching cycle. Pd_re is zero. As discussed in Chapter 3.2, the body diode D2 of MOSFET Q2 starts to conduct after Q1 is off at t1, then Q2 turns on at t2, the current flowing through D2 diverts into Q2 because of the low on-resistance in Q2. Since Q2 already conducted before D2 is reversed, the reversed voltage applied on D2 is zero. Therefore there is no reverse recovery loss on D2. The analysis is the same on the body diode D1.</p><p>The summation of losses analyzed above will give the total dissipation, PD , in the MOS-</p><p>FET:</p><p>P Pon Po f f Po f f _on Pon f f P Pd_f Pd_re (3.31) D = + + + o + DS + + 23.27 0.00 0 9.60 0.58 0.11 0.00 33.56 W atts = + + + + + + = c).MOSFET Heating Sink Selection:</p><p>The typical equation used for calculation of the MOSFET dissipation is shown as below:</p><p>θ (T T )/P (3.32) JA = J − A D</p><p>Where:</p><p>θJA=thermal resistance</p><p>TJ = junction temperature</p><p>TA = ambient temperature</p><p>39 PD = power dissipation</p><p>θJA consists of three separate thermal resistances in series. One is the thermal resistance inside the device, between the junction and the its case, called θJC . Another is the resistance of the silicon grease used between the MOSFET case and the heat sink, called θCS. The last one is the thermal resistance of the heat sink, called θSA [29]. The total thermal resistance is:</p><p>θ θ θ θ (3.33) JA = JC + CS + SA</p><p>Rearranging two Equations 3.32 and 3.33:</p><p>θ (T T )/P θ θ (3.34) SA = J − A D − JC − CS</p><p>Based on the datasheet specifications of the device and the actual operation conditions,</p><p> o o the maximum junction temperature TJ = 150 C. The ambient temperature TA is set as 50 C. PD has been already calculated as 33.56 Watts. From the datasheet, the thermal resistance of silicon</p><p> o o grease θCS is 0.1 C/Watt, and the junction-case thermal resistance is 0.26 C/Watt. Thus the thermal resistance θSA should be at most:</p><p>θ (150oC 50oC)/33.56W 0.1oC/W 0.26oC/W 2.62oC/W (3.35) SA = − − − =</p><p>The heat sink is selected as 52980X model provided by Aavid Thermalloy. The dissipation features are shown in Figure 3.11 [30]. Based on the Figure 3.11, to acquire a low enough thermal resistance, a cooling fan will be added in the practical design. Because a high air velocity results in a lower thermal resistance.</p><p>40 TO-220 & TO-218 & TO-247 Heat Sinks</p><p>Grease Mounting & SW25, SW38, SW50, SW63 Extruded heat sink with unequal channel widths Epoxy Kits page112 page 99</p><p>Air Velocity—Feet Per Minute 34.50 0 200400 600 800 1000 6.25 (1.358) 100 10 (0.246)</p><p>C 2.00</p><p>80 8 C/Watt —° (0.079) 12.50 —° 60 6 (0.492) 40 4 SEE NOTE 1 20 2 Mounting SurfaceMounting Temp Rise Above Ambient Rise Above Thermal Resistance From MTG From Resistance Thermal 0 0 Surface Ambient to 024 6 810 Extruded heat sink with unequal SW25 Heat Dissipated—Watts channel widths front and back SW38 Air Velocity—Feet Per Minute can accommodate a TO-220,TO-218, "A" or TO-247 devices. Includes two solder- 0 200400 600 800 1000 100 10 25.00</p><p> able mounting pins which permit verti- C (0.984) 19.90</p><p>80 8 C/Watt 15.00 cal mounting and eliminate stress on —° (0.783)</p><p>—° (0.591) device leads. Available in three heights. 60 6 Version without hole uses clip 5901 40 4 ø3.20 (sold separately) to attach device. 4.00 (0.126)TYP (0.157) 20 2 2.50 See page 97 for clip information. SurfaceMounting Temp Rise Above Ambient Rise Above (0.098) Thermal Resistance From MTG From Resistance Thermal 0 0 Surface Ambient to 25.40 024 6 810 (1.000) SW50 Heat Dissipated—Watts SW63 ORDERING INFORMATION Dia of PCB Plated Thru Part Number Description “A” Dim Holes Hole for Pins SW25-2G Extruded heat sink with unequal channel widths front and back 25.00 (0.984) No 3.00 (0.118)</p><p>SW25-4G With device mounting holes 25.00 (0.984) Yes 3.00 (0.118) NOTE 1:This hole not present in SW25 model</p><p>THRU HOLE DISCRETE SEMICONDUCTOR PACKAGES SW38-2G Extruded heat sink with unequal channel widths front and back 38.00 (1.496) No 3.00 (0.118)</p><p>SW38-4G With device mounting holes 38.00 (1.496) Yes 3.00 (0.118) Material: Aluminum SW50-2G Extruded heat sink with unequal channel widths front and back 50.00 (1.968) No 3.00 (0.118) Finish: Black Anodize SW50-4G With device mounting holes 50.00 (1.968) Yes 3.00 (0.118) SW63-2G Extruded heat sink with unequal channel widths front and back 63.00 (2.480) No 3.00 (0.118) SW63-4G With device mounting holes 63.00 (2.480) Yes 3.00 (0.118)</p><p>Grease Mounting & 5297, 5298, 5299, 5300 Extruded heat sink with large radial fins Epoxy Kits page112 page 99 Air Velocity—Feet Per Minute 0 200400 600 800 1000 20.96 100 5 (0.825) 80 4</p><p>60 3 "C" 40 2</p><p>20 1 Mounting SurfaceMounting Temp Rise Above Ambient—°C Rise Above Thermal Resistance From MTG From Resistance Thermal 0 0 Surface Ambient—°C/Watt to "A" 0 4 8 12 16 20 52970X Heat Dissipated—Watts Extruded heat sink with large radial 52980X Figure 3.11: Heating Sink Dissipation Features fins features equal channel widths on Air Velocity—Feet Per Minute "B" 3.96 both sides for single or dual device 0 200400 600 800 1000 (0.156) 100 5 2x mounting. Includes two solderable 3.4 Resonant Network mounting pins which permit vertical 80 4 3.18 The resonant network contains three components as shown in Figure 3.12. The leakage inductor (0.125) 13.72 mounting and eliminate stress on 60 3 14.22 (0.540) ø 2.36 Lr and the magnetizing inductor Lm are both discussed in Chapter 2.4. Lr and Lm are integrated device leads. Available in four heights (0.560) (0.093) 2x into the transformer40 when it’s designed. As shown in the Table 3.1, the2 values of Lr and Lm for TO-220,TO-218, and TO-247 devices. 25.40 produced favorable20 test results. 1 (1.000) Mounting SurfaceMounting Temp Rise Above Ambient—°C Rise Above Thermal Resistance From MTG From Resistance Thermal 0 0 Surface Ambient—°C/Watt to 0 4 8 12 16 20 52990X Heat Dissipated—Watts 53000X 1.57 (0.062) Dia of PCB ORDERING INFORMATION 25.40 Plated Thru (1.000) Part Number Device “A” Dim “B” Dim “C” Dim Hole for Pins 529701B02500G TO-218,TO-247 25.40 (1.000) 21.59 (0.850) 3.66 (0.144) 2.67 (0.105) 17.02 529702B02500G TO-220 25.40 (1.000) 18.29 (0.720) 3.17 (0.125) 2.67 (0.105) Figure 3.12: Resonant Network (0.670) 529801B02500G TO-218,TO-247 38.10 (1.500) 21.59 (0.850) 3.66 (0.144) 2.67 (0.105) 41 41.91 529802B02500G TO-220 38.10 (1.500) 18.29 (0.720) 3.17 (0.125) 2.67 (0.105) (1.650) 529901B02500G TO-218,TO-247 50.80 (2.000) 21.59 (0.850) 3.66 (0.144) 2.67 (0.105) Material: Aluminum 529902B02500G TO-220 50.80 (2.000) 18.29 (0.720) 3.17 (0.125) 2.67 (0.105) Finish: Black Anodize 530001B02500G TO-218,TO-247 63.50 (2.500) 21.59 (0.850) 3.66 (0.144) 2.67 (0.105) 530002B02500G TO-220 63.50 (2.500) 18.29 (0.720) 3.17 (0.125) 2.67 (0.105) For additional options see page 83</p><p>AMERICA USA Tel: +1 (603) 224-9988 email: info@aavid.com ASIA Singapore Tel: +65 6362 8388 email: sales@aavid.com.sg EUROPE Italy Tel: +39 051 764011 email: sales.it@aavid.com Taiwan Tel: +886(2) 2698-9888 email: sales@aavid.com.tw 56 www.aavidthermalloy.com United Kingdom Tel: +44 1793 401400 email: sales.uk@aavid.com The selection of the resonant capacitor (2.2µF ) consists of determining the voltage applied across the capacitor and the capacitance value. A power film capacitor is selected, since it has a high power rating. The voltage on the resonant capacitor is obtained from the</p><p>PSpice simulation, which is shown in Figure 3.13. The voltage is a DC voltage with sinusoidal ** Profile: "SCHEMATIC1-correct3fo06" [ C:\Cadence\Practice\... Date/Time run: 05/30/16 15:42:40 Temperature: 27.0 fluctuations. The RMS value of the voltage(A) is correct3fo06 around 55 (active) V. B32523 Model from EPCOS is designed 128.17V for automotive industry use. B32523 Model has a permissible 250 V DC voltage which satisfies the requirement.</p><p>100.00V</p><p>50.00V</p><p>0V</p><p>Figure 3.13: Voltage on the Resonant Capacitor Cr -15.25V 19.14ms 19.18ms 19.22ms 19.26ms V(CR1:2,CR1:1) Time Date: May 30, 2016 Page 1 Time: 15:49:18 3.5 Driver Circuit Design</p><p>The driver circuit for the MOSFET is critical for the success of the circuit design. In this section, the driver IC selection and the detailed turning on and off process will be discussed.</p><p>3.5.1 Driver IC Selection</p><p>The goal of the driver circuit design is to turn on and turn off the MOSFET fast and accurately.</p><p>The equivalent circuit of the MOSFET is shown in Figure 3.14. The MOSFET contains a body diode and three parasitic capacitors, Cgs, Cgd and Cds.</p><p>42 Where:</p><p>Cgs = capacitance between gate and source</p><p>Cgd = capacitance between drain and gate</p><p>Cds = capacitance between drain and source</p><p>Figure 3.14: Parasite Capacitance in the MOSFET</p><p>During the turn on process, the capacitance Cgs first begins to charge until arriving at the plateau of the curve shown in Figure 3.15. The MOSFET starts to turns on at the gate plateau voltage which is around 6.1 V. Technically the rise time tr of the turn-on process is the period from the starting point to the plateau voltage (Miller Plateau). However, to turn on the MOSFET completely, the gate current has to fill the total charge Qg shown in Table 3.1.</p><p>43 600VCoolMOS™P6PowerTransistor</p><p>IPW60R041P6</p><p>Diagram9:Typ.transfercharacteristics Diagram10:Typ.gatecharge 300 10</p><p>9 250 25 °C 8 120 V 480 V</p><p>7 200 6</p><p>150 [V] 5 [A] D GS I</p><p>150 °C V 4 100 3</p><p>2 50 1</p><p>0 0 0 2 4 6 8 10 12 14 0 50 100 150 200 VGS[V] Qgate[nC]</p><p>ID=f(VGS);VDS=20V;parameter:Tj VGS=f(Qgate);ID=44.4Apulsed;parameter:VDD</p><p>Figure 3.15: Typical Gate Charge Diagram [5]</p><p>Diagram11:Forwardcharacteristicsofreversediode Diagram12:Avalancheenergy 102 2000 The rise time tr of the turn on transition is 27 ns. From the datasheet, tr is tested under a 1800 very large gate charging current which is around 7.6 A. During the rise time, the total gate charge 1600</p><p> equals to 27*7.6 = 205 nC. The1400 total charge given in Table 3.1 is 170 nC. It is hard to get a driver IC 101 with a 7.6 A charging current.1200 Finally the model 2EDL23N06PJ from Infineon is selected, which 125 °C 25 °C 1000 [A] [mJ] F I AS</p><p> has a maximum charging currentE of 2.3 A,is selected as the driver IC. The charging time tr (rise 800 100 time) can be approximately calculated600 as:</p><p>400 tr Qg/2.3A 170nc/2.3A 74ns (3.36) 200 = = =</p><p>10-1 0 0.0 0.5 1.0 1.5 2.0 25 50 75 100 125 150 3.5.2VSD[V] Charging and Discharging Path Tj[°C] IF=f(VSD);parameter:Tj EAS=f(Tj);ID=13.4A;VDD=50V The charging and discharging paths for both MOSFETs are the same, and are highlighted in the</p><p> red box as shown in Figure 3.16 below. The internal gate resistance of the MOSFET is 1 Ω. The Final Data Sheet 10 Rev.2.0,2014-03-07 resistance RLIN1 for the charging path is calculated as:</p><p>RLIN1 V g/2.3A 1Ω 5.5Ω. (3.37) = − =</p><p>Where Vg is the voltage supply for the driver IC which is equal to 15 V, and Vg is applied directly</p><p> on the gate charging path. RLIN1 is selected as a 6 Ω <a href="/tags/Resistor/" rel="tag">resistor</a>. 44 15V Bootstrap Capacitor RHIN1K VHIN 1 2 2EDL23N06PJ 1 14 2 13 4U7_1206 DC_HV VLIN 1 2 3 12 4.7uf FAULT 4 11 RLIN 1K 5 10 C102_1 C102_2 + PGND 6 9 LO 78 RHIN1 1 2 1nf 1nf CAP4U7_1 SO14 10BQ100PBF_1 6R RHIN2 1 2 GND Charge and 0R RLIN1 Discharge Path 2 PWM Filter 1 10BQ100PBF_2 6R RLIN2 LO 1 2 0R</p><p>Figure 3.16: MOSFET Driver Circuit</p><p>As for the discharging path, the resistance along the path should be as small as possible to reduce the turn-off loss. Therefore a zero resistance will be ideal. Because of the 1 Ω internal gate resistance, the total discharging resistance is 1 Ω. Vgs is fully charged to be Vg here. The peak discharging current will be Vgs/1 Ω =15 A. A 15 A repetitive surge current is a huge challenge for the discharging diode. A high performance Schottky rectifier diode 10BQ100PBF from VISHAY is selected. 10BQ100PBF is compatible with the high frequency operation. It can take a continuous current of 1A, and a 38 A surge current.</p><p>3.5.3 Bootstrap Capacitor Calculation</p><p>The driver for the low side MOSFET (Q2) is fairly straightforward, only a 15 V voltage applied on the gate charge path is required. However the high side MOSFET (Q1) needs some special techniques to guarantee a +15 V difference. The bootstrap circuit is utilized in the high side <a href="/tags/Gate_driver/" rel="tag">gate driver</a> to provide the +15 V difference. The MOSFET driver with bootstrap circuit is shown in</p><p>Figure 3.17 [6]. When the low side MOSFET is turned on and the high side MOSFET is turned off, the Vs is pulled down to the ground. The bootstrap capacitor, CBOOT , is charged through the bootstrap resistor, RBOOT , and bootstrap diode, DBOOT . When the low side MOSFET is turned off, the VBS floats and the bootstrap diode is reversely biased.</p><p>45</p><p> www.fairchildsemi.com</p><p>AN-6076 Design and Application Guide of Bootstrap Circuit for High-Voltage Gate-Drive IC</p><p>1. Introduction unique level-shift design. To maintain high efficiency and manageable power dissipation, the level-shifters should not The purpose of this paper is to demonstrate a systematic draw any current during the on-time of the main switch. approach to design high-performance bootstrap gate drive A widely used technique for these applications is called circuits for high-frequency, high-power, and high-efficiency pulsed latch level translators, shown in Figure 1. switching applications using a power MOSFET and IGBT. It should be of interest to power <a href="/tags/Electronics/" rel="tag">electronics</a> engineers at all levels of experience. In the most of switching applications, efficiency focuses on switching losses that are mainly depen- VB dent on switching speed. Therefore, the switching character- UVLO istics are very important in most of the high-power switching PULSE GENERATOR HO applications presented in this paper. One of the most widely IN R NOISE R used methods to supply power to the high-side gate drive cir- CANCELLER S Q Shoot-through current compensated gate driver gate compensated cuitry of the high-voltage gate-drive IC is the bootstrap VS power supply. This bootstrap power supply technique has the advantage of being simple and low cost. However, it has some limitations, on time of duty-cycle is limited by the Figure 1. Level-Shifter in High-Side Drive IC requirement to refresh the charge in the bootstrap capacitor and serious problems occur when the negative voltage is pre- 2.2 Bootstrap Drive Circuit Operation sented at the source of the switching device. The most popu- The bootstrap circuit is useful in a high-voltage gate driver lar bootstrap circuit solutions are analyzed; including the and operates as follows. When the V goes below the IC effects of parasitic elements, the bootstrap resistor, and S supply voltage VDD or is pulled down to ground (the low- capacitor; on the charge of the floating supply application. side switch is turned on and the high-side switch is turned off), the bootstrap capacitor, CBOOT, charges through the 2. High-Speed Gate-Driver Circuitry bootstrap resistor, RBOOT, and bootstrap diode, DBOOT, from the VDD power supply, as shown in Figure 2. This is pro- 2.1 Bootstrap Gate-Drive Technique vided by VBS when VS is pulled to a higher voltage by the high-side switch, the V supply floats and the bootstrap The focus of this topic is the bootstrap gate-drive circuit BS diode reverses bias and blocks the rail voltage (the low-side requirements of the power MOSFET and IGBT in various switch is turned off and high-side switch is turned on) from switching-mode power-conversion applications. Where the IC supply voltage, V . input voltage levels prohibit the use of direct-gate drive cir- DD cuits for high-side N-channel power MOSFET or IGBT, the RBOOT DBOOT DC SUPPLY principle of bootstrap gate-drive technique can be consid- Bootstrap charge current path ered. This method is utilized as a gate drive and accompany- Bootstrap discharge current path VB ing bias circuit, both referenced to the source of the main RG1 switching device. Both the driver and bias circuit swing VDD HO Q1</p><p>ILOAD between the two input voltage rails together with the source CBOOT VDD of the device. However, the driver and its floating bias can VS LOAD be implemented by low-voltage circuit elements since the RG2 Q2 input voltage is never applied across their components. The COM LO driver and the ground referenced control signal are linked by a level shift circuit that must tolerate the high-voltage differ- ence and considerable capacitive switching currents between FigureFigure 2. 3.17:Bootstrap Bootstrap Power Power Supply Supply Circuit Circuit [6] the floating high-side and ground-referenced low-side cir- cuits. The high-voltage gate-drive ICs are differentiated by The bootstrap capacitor is charged during each switching cycle. Theoretically the voltage</p><p>© 2008 Fairchild Semiconductor Corporation VBS across the bootstrap capacitor, CBOOT , can be charged to: www.fairchildsemi.com Rev. 1.4 • 12/18/14 V V VD VDS 15V 1.2V 0.2V 13.6V (3.38) BS = DD − BOOT − = − − =</p><p>The voltage drop on RBOOT can be ignored because it is very small. The value of the</p><p> bootstrap capacitance is determined by the maximum allowable voltage drop on VBS. Assuming</p><p> the permissible maximum bootstrap voltage fluctuation, V , is 0.5 V. The maximum tolerance 4 BS of the bootstrap voltage fluctuation is about 1.5 V. Therefore a 0.5 V design specification provides</p><p> a 1V margin. The bootstrap capacitance is calculated as [5]:</p><p>C (i tp Qg s)/( V ) 1.5 (3.39) BOOT = QBS ∗ + 4 BS ∗</p><p> where iQBS is the quiescent current of the high side section, tp is the switching period. Comparing</p><p> with the total charge Qg for the super junction capacitance in this MOSFET model, i tp can QBS ∗ be ignored. Therefore the bootstrap capacitance is:</p><p>C Qg s/ V 1.5 170nC/(0.5V ) 1.5 127.5nF (3.40) BOOT = 4 BS ∗ = ∗ =</p><p>In the practical design, there are two special considerations on the bootstrap capacitor.</p><p>The current drawn from the bootstrap capacitor is a large pulse current. Therefore the ESR 46 (Equivalent Series Resistance) of the capacitance has to be very small. Otherwise the losses can result in a lower capacitor lifetime. The layout rule of the bootstrap capacitor is that it must be placed as close as possible to the driver IC. Otherwise, the voltage spikes caused by parasitic <a href="/tags/Resistor/" rel="tag">resistors</a> and inductors may trigger the undervoltage lockout threshold of the driver IC. a).Investigation of the Voltage Drop along the Bootstrap Charging Path</p><p>As shown in the Equation 3.38, the value of VBS is supposed to be around 13.6 V with a small periodical fluctuation. This voltage drop along the bootstrap charging path was measured in the lab. The VBS shown in Figure 3.18 demonstrates the Equation 3.38 for a switching frequency of 100 kHz. However when the switching frequency is raised to 500 kHz from 100 kHz, the VBS becomes 10.0 V which is shown in Figure 3.19.</p><p>Figure 3.18: VBS under 100 kHz Switching Frequency</p><p>47 Figure 3.19: VBS under 500 kHz Switching Frequency</p><p>There are two possible explanations. One is a small switching period results in a non- saturation on-state of the MOSFET. According to the Equation 3.38, a non-saturation on-state means a higher VDS value, thus the VBS is lower than 13.6 V.However the voltage drop on MOSFET was also measured in the lab, and the resulting VDS was almost zero during the on-state. Thus this explanation is not valid.</p><p>The other reason is the high switching frequency causes a big recovery loss on the boot- strap diode, DBOOT . The bootstrap diode, DBOOT , is integrated into the driver IC. The perfor- mance of the bootstrap diode under a high frequency is doubtable. Therefore paralleling a high performance diode with the existing diode might be a good solution.</p><p>3.5.4 PWM (Pulse Width Modulation) Signal Filtering</p><p>The PWM signal block is shown in Figure 3.16, which consists of a resistor and a capacitor (RC</p><p>filter) for each PWM signal. VHIN and VLIN are two PWM signals from DSP controller. The IO 48 ports of this controller can provide 3.3V PWM signals with a maximum current of 4mA. The RC</p><p>filter resistances, RHIN and RLIN, can be calculated as:</p><p>RHIN RLIN 3.3V /4m A 825Ω (3.41) = = =</p><p>In the real design, the value of RHIN and RLIN are chosen as 1 kΩ. The RC filter and its magnitude bode plot are shown in Figure 3.20. The 3dB cut off frequency needs to be higher − than the frequency of PWM signal. The 500 kHz PWM signal is the highest frequency that will be used during the soft-start period. Therefore the cut off frequency fc can be set as 600 kHz. Based on the voltage division rule, the expression of a 3dB output magnitude decrease can be written − as:</p><p>1/(2π f c C) 3dB 20 log( ∗ ∗ ) (3.42) − = ∗ (R 1/(2π f c C)) + ∗ ∗ C 0.11nF (3.43) =</p><p>Figure 3.20: RC Low Pass Filter</p><p>3.6 Protection and Feedback</p><p>There are four parts of design in this section, MOSFET current sensing, input current sensing, input voltage sensing and fault management. The first two parts are design to protect the short circuit and restart. The other two are design to acquire the parameters used in the feedback control.</p><p>49 3.6.1 Detect the Short Circuit Condition</p><p>There is a mechanism in the driver IC model 2EDL23N06PJ to prevent overcurrent (short circuit).</p><p>The voltage drop between the pins, PGND and GND, can be sent to a comparator with a threshold of 0.46 V. If the voltage drop is larger than 0.46 V, then the comparator will be triggered and the protection is activated to stop all the PWMs signals for a 230µs period. During the protection period, a 230µs fault signal will be shown on the pin of /FLT.</p><p>The voltage drop between PGND and GND needs to be created when the short circuit is happened. As shown in Figure 3.9, the circulating resonant current flows through MOSFET during the whole switching cycle. Therefore the overcurrent sensor can be connected in series with the source terminal of the MOSFET. The overcurrent sensor is shown in the red box in</p><p>Figure 3.16.</p><p>As calculated in the Equation 3.23, the peak circulating current is 33.0 A. The definition of the overcurrent value under the short circuit condition is critical. It can’t be too large, thus some large currents caused by short circuit might be omitted. It also can’t be too small, that the protection can be triggered by the start currents or the noises. Therefore a three times of the peak circulating current is selected as the overcurrent limitation. The resistance of the current sensor can be calculated as:</p><p>0.46V /(3 33.0A) 4.6mΩ (3.44) ∗ =</p><p>This resistor has to be a special made resistor for power electronics current sensing. The LRMA series resistors from TT Electronics is selected. The LRMA series resistors have precise resistance, a high power rating, and a low thermal EMF (Electromotive Force).</p><p>50 DC_HV</p><p>RHIN1 IPW 2</p><p>1 6R RHIN2 1 2 0R RLIN1 2 IPW</p><p>2 6R RLIN2 1 2 0R</p><p>PGND 2 5mOh RSEN 1</p><p>GND_</p><p>Figure 3.21: Over Current Sensor</p><p>3.6.2 Fault Indication and Restart</p><p>The /FLT pin will activate under the occurring of the under-voltage protection or the overcurrent protection. The fault indication signal from /FLT lasts only 230µs. The driver IC will restart to work after the 230µs activation. If the problems in the circuit are not properly solved, the driver IC will keep going into the fault condition and restart. Finally the repetitive overcurrent or</p><p>51 �</p><p>�</p><p>� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �</p><p>� � � � � � �</p><p>� � � � � � � � � � � � � � � � � � � � �</p><p>� � �</p><p>� � � � � � � � � � � � � � � � � � � � � � � � � � � � � �</p><p>� �</p><p>� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �</p><p>� � � �</p><p>� � � �</p><p>� � � � �</p><p>� � � �</p><p>� � � � � � � � � � � � � �</p><p>� � � � � �</p><p>� � � � � � � � � � �</p><p>� � � � �</p><p>� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �</p><p>� � � � � � � � � � � � � � � � � �</p><p>�</p><p>� � � �</p><p>+5VA DC_HV 6 5 +5VA 4 3 2 1 +5VA INDUCTOR_5UF +5VA INDUCTOR REVISION RECORD</p><p>15V DC_HV GBPC35 1 2</p><p>2 LTR ECO NO: APPROVED: DATE: 2 LM7805CT 2 4 2 CAPFIL_5UF 10K 1 3 R20 3 BRIDGEDIO 1 IN OUT 120VAC R18 ACPLUG 160K 1</p><p>GND 1 C104_1+ 220UF + CAPFIL_47UFC104_2 1 15VIN 15VPIN 1 2 +5VA D ZEROCROSS_DET GND_SEN D 2 3 2 2 BC849_3 CAP1206 ZENER2 RD 6.8nf CURSEN R27 1 2 1 2 4.7K 1 8 1 2 7 CURR_TOL_OUT</p><p>1K 1 D_15V 3 6 4 5 GND C104_3 CF 47nf</p><p> under-voltage conditions probably will damage the MOSFETs or driver IC itself. GND 15V</p><p>RHIN1K The faultVHIN signal has1 to be2 detected and sent to the DSP controller.2EDL23N06PJ Then the DSP controller 1 14 2 13 4U7_1206 DC_HV TRANS_PLUG2 1 C VLIN 1 2 3 12 4.7uf GND_SEN C can prohibit all the PWM signals until the circuit problemsFAULT are4 found and11 solved. A flip-flop ACPLUG RLIN 1K 5 10 C102_1 C102_2 + PGND 6 9 circuit is shown as below. When the /FLT pin is activated,LO the zero7 fault voltage8 will be locked RHIN1 IPW60R041P6_1 CAP4U7_1 1 2 1nf 1nf CR2U1 SO14 10BQ100PBF_1 6R RHIN2 and a red LED will be lighted. At the same time, the DSP captures the falling edge of the fault 1 2 GND 0R RLIN1 signal and stops all PWM outputs. A reset signal will be sent to the flip-flop to circuit to clear the 1 2 IPW60R041P6_2 10BQ100PBF_2 6R RLIN2 fault condition. LO 1 2 0R</p><p>PGND 2 2 2 R9 R5 B 10K 10K 15VIN1 B 2mOh RSEN VLIN 1 6 GND 15V 2 1 1 1 1 2 7 RST CURR_TOL_OUT 3 8 FAULT CURR_TOL_OUT 4 9 ZEROCROSS_DET 1 1 R3 R4 22K 22K 5 10 VHIN GND 1</p><p>2 DIP10_100 D_FAULT D_READY 2 2</p><p>RST FAULT COMPANY: 3 3 47K R8 BC849_1 2 2 1 1 2 2 BC849_5 47K R6 TITLE: 1 3 1 3 BC849_4 2 47K 47K 2 1 2 1 2 BC849_2 DRAWN: DATED:</p><p>1 R7 1 R2 A 1 A CHECKED: DATED: CODE: SIZE: DRAWING NO: REV: R10 47K</p><p>2 QUALITY CONTROL: DATED:</p><p>GND</p><p>RELEASED: DATED: SCALE: SHEET: OF Figure 3.22: Flip-Flop Circuit for Fault Indication and Restart</p><p>3.6.3 Input Current and Zero-crossing Point of Input Voltage</p><p>As analyzed in the Chapter 2.3.1, the output voltage of the resonant power supply can be adjusted</p><p> by changing the switching frequency. The LC filter after the rectified bridge is far away from</p><p>filtering the sinusoidal voltage into a DC voltage. Therefore the DC rectified voltage is actually an</p><p> approximate positive semi-sine.</p><p>52 �</p><p>� �</p><p>� � � � � � � � � � � � � � � � � �</p><p>� �</p><p>� � � � � �</p><p>� � � � � � � � � � � � � � � � � � � �</p><p>� �</p><p>� � � � � � � � � � � � � � � � � � � � �</p><p>� � � � � � � �</p><p>�</p><p>�</p><p>� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �</p><p>� � � � � � � �</p><p>� �</p><p>� � � � � � � � � � � � � �</p><p>� � � � � �</p><p>� � � � � � � � � � � � � � � �</p><p>� � � � � � � � � � � � � � � � � � � � � � � � � � � � � �</p><p>� � � � � � � �</p><p>� DC_HV +5VA +5VA INDUCTOR_5UF +5VA +5VA BRIDGE_DIODE INDUCTOR 15V GBPC35 1 2 DC_HV 2 LM7805CT 2 4 2 2 CAPFIL_5UF 1 3 3 1 IN OUT 120VAC 10K R20 ACPLUG 1</p><p>GND R18 C104_1+ 220UF + CAPFIL_47UFC104_2 160K 1 15VIN 15VPIN 1 2 1 ZEROCROSS_DET +5VA GND_SEN 2 3 2 2 CURRENT_SENSOR RD CAP1206 ZENER2 1 2 1 2 6.8nf 1 8</p><p>4.7K BC849_3 2 7 CURR_TOL_OUT 1K D_15V 1 3 6 1</p><p>R27 4 5 GND C104_3 CF 47nf</p><p>15V</p><p>GND</p><p>RHIN VHIN 1 2 2EDL23N06PJ 1 14 DC_HV TRANS_PLUG2 1 1K Figure 3.23:4U7_1206 Input Voltage Zero Cross Detection and Input Current Sensor RLIN 2 13 4.7uf GND_SEN VLIN 1 2 3 12 ACPLUG FAULT 4 11 1K 5 10 6 9 C102_1 C102_2+ CAP4U7_1 PGND RHIN1 IPW60R041P6_1 LO 7 8 1 2 1nf 1nf CR2U1 1N4148_1 10R SO14 RHIN2 To acquire a more flat output1 voltage2 applied on the magnetron, the voltage gain of the 7R GND RLIN1 IPW60R041P6_2 resonant converter needs to be1 adjusted2 along with the positive semi-sine input voltage. The 1N4148_2 10R RLIN2 LO 1 2 2 synchronous control point for every7R cycle of the positive semi-sine wave can be selected as 5mOh</p><p>PGND RSEN 2 2 the zero-crossing point of the positive semi-sine1 wave. The zero-crossing detection circuit is R9 R5</p><p>10K 10K 15VIN1 VLIN 1 6 GND 15V shown in Figure 3.23. A voltage divider is used to obtain the rectified voltage. When the voltage is 2 1 1 1 2 7 RST GND_SEN CURR_TOL_OUT 3 8 FAULT CURR_TOL_OUT 4 9 ZEROCROSS_DET 1 1 R3 R4 22K 22K approaching the bottom of the positive semi-sine wave, the output of the amplifier will5 be flipped.10 VHIN 1</p><p>2 DIP10_100 D_FAULT D_READY 2 A small capacitor2 is installed for filtering the possible noises, in case of the false triggering. The RST FAULT 3 3 47K passingR8 frequency band of this filtering capacitor needs to include the frequency of the semi-sine BC849_1 2 2 1 1 2 2 BC849_5 R6 47K 1 3 1 wave.3 BC849_4 2 47K 47K 2 1 2 1 2 BC849_2</p><p>1 R7 1 R2 1 The RMS current also need to be acquired to be used in the calculation of the input R10 47K</p><p>2 power. There are two ways to detect the input current. One is to insert a small precision resistor.</p><p>GND The other method is to adopt a hall effect linear current sensor. A small precision resistor is</p><p> cheap, but it needs a amplifying circuit to enlarge the signal. The input current is large, thus a</p><p> considerable power will be dissipated in the resistor. Finally the hall effect chip ACS711 model</p><p> from Allegro is adopted as the current sensor.</p><p>53 3.7 Layout of PCB (Printed Circuit Board)</p><p>The considerations of designing the high power PCB and electromagnetic interference (EMI) are discussed in this section.</p><p>3.7.1 PCB Copper Calculations</p><p>Due to the high current in the resonant tank and the MOSFET bridge, the PCB thickness and the trace width need to be calculated in case of over temperature or even damage. According to the standard IPC-2221 (Generic Standard on the Printed Circuit Board Design) [31], the trace width is calculated as following. First, the Area is calculated:</p><p>³ Cur rent(A) ´(1/c) Area(mil s2) (3.45) b = k ¡Temp_Ri se(oC)¢ ∗ Then, the width is calculated:</p><p>Area(mil s2) W idth(mil s) (3.46) = (T hickness(oz) 1.378(mil s/oz) ∗ For IPC-2221 external layers: k = 0.048, b = 0.44, c = 0.725. where k, b, and c are constants obtained from IPC-2221 curves. To reduce the trace width as much as possible, a PCB copper plate with 3 oz thickness is selected. Bringing the 3 oz thickness into the formula above, and set the allowable temperature rise as 10oC. The width trace is calculated as 305 mils.</p><p>3.7.2 EMI Suppression</p><p>The PCB layout of the transformer primary side is shown in Figure 3.24. The left area of the primary side is the mixed signal processing part (the low power area), and the right area is the high power side. The switching MOSFET can generate a high electromagnetic noise which might be interfered with the low voltage side. The PWM signal in the low voltage area is very sensitive, any pollutions can results in the wrong conduction on the MOSFETs which might burn the</p><p>MOSFETs. The low voltage side also has communication with the DSP controller, any noises might hurt the DSP controller as well.</p><p>54 Figure 3.24: PCB Layout</p><p>As shown in the Figure 3.24, the low power and the high power side are separated on the</p><p>PCB. There is only one connection point at the border between these two areas. Also to protect the low power side from the electromagnetic noise, the ground flooding on the both side of the low power area is implemented.</p><p>55 CHAPTER 4: SIMULATION AND EXPERIMENT</p><p>4.1 Simulation Results Discussion</p><p>The LLC based main circuit in Figure 2.9 is simulated in Pspice environment. A transient analysis</p><p> based circuit is built in Pspice as shown in Figure 4.1. The DC input voltage of the MOSFET</p><p> bridge is set as 108 V which is equal to the filtered rectified voltage of the AC main in United</p><p>States. In the simulation diagram, TR1 is a transformer model with two secondary outputs. The</p><p> secondary output between pin 3 and pin 4 is for delivering the energy to the rectifier diode. The</p><p>5 4 3 2 1 other output between oins 10 and 11 is for driving the filament of the Microwave Oven.</p><p>D D1 1N4148 D HS_DRI</p><p>RA1 M1 IRF840</p><p>20 R1 Re=8*RL/(pi^2*n^2) fs=80kHZ Vf_pp=2/piVdc VDC1 10k CR1 LR1 D8 108 D2 1N4148 LS_DRI 2.1uf 1.88uH M2 TR1 40eps16 RB1 IRF840 C3 1 4 0 LM1 0.5uf R2 20 12.27uH 3 R4 16k 10k 10 C R3 2 11 C Rlamp C4 XFMR2 20 0.5uf 5m RATIO1 = 0.027 D7 0 Np=Vdc/(8*fs*Bmax*Ae) D3 RATIO2 = 18 Vcc Vcc 40eps16 1N4007 R7 Vcc Q1 Q2</p><p>1k Q2N3904 CBOOT1 Q2N3904 VCC1 HS_DRI LS_DRI 14Vdc 0.1u V1 Q3 V2 Q4 S Q2N3906 S Q2N3906 B B 0 Implementation = V1 Implementation = V2 OUT</p><p>0</p><p>MOSFET Driver PART</p><p>Figure 4.1: Simulation Diagram of the Main Circuit in Pspice</p><p>A A</p><p>Title LLC RESONANT CONVERTER SIMULATION</p><p>Size Document Number Rev A <Doc> 0.1</p><p>Date:Sunday, June 05, 2016 Sheet 11of 5 4 3 2 1 56 4.1.1 The Simulation of the Operation of the Resonant Network</p><p>The operation of the resonant network has been discussed in detail in subsection 2.3.2. As shown in the Figure 2.15. The simulation results of currents Ir , Im and Is are all shown in Figure 4.3.</p><p>The resonant current Ir is a sinusoidal wave, the magnetizing current Im is a linear increasing or decreasing current and doesn’t resonate with Lr and Cr . Because the voltage on Lm is clamped by the secondary output voltage (constant voltage). The current Is which is delivered to the secondary side is the difference between Ir and Im.</p><p>40A</p><p>0A</p><p>-40A I(CR1) -I(LM1) 40A</p><p>20A</p><p>0A</p><p>-20A</p><p>SEL>> -40A 5.00ms 5.01ms 5.02ms 5.03ms 5.04ms 5.05ms 5.06ms I(TR1:1) Time</p><p>Figure 4.2: Simulation of the Operation of the Resonant Network</p><p>57 4.1.2 The Simulation of the Operation of the Resonant Network</p><p>The operation of the resonant network has been discussed in detail in Chapter 2.3.2. As shown in the Figure 2.15. The simulation results of currents Ir , Im and Is are all shown in Figure 4.3.</p><p>The resonant current Ir is a sinusoidal wave, the magnetizing current Im is a linear increasing or decreasing current and doesn’t resonate with Lr and Cr . Because the voltage on Lm is clamped by the secondary output voltage (constant voltage). The current Is which is delivered to the secondary side is the difference between Ir and Im.</p><p>40A</p><p>0A</p><p>-40A I(CR1) -I(LM1) 40A</p><p>20A</p><p>0A</p><p>-20A</p><p>SEL>> -40A 5.00ms 5.01ms 5.02ms 5.03ms 5.04ms 5.05ms 5.06ms I(TR1:1) Time</p><p>Figure 4.3: Simulation of the Operation of the Resonant Network</p><p>58 4.1.3 The Output Voltages at Different Switching Frequencies</p><p>As analyzed in the Chapter 2.3.1, the voltage gain Mg changes as a function of switching frequency as shown in Figure 2.12. The curves of Mg under different Qe all have a peak value. In Section</p><p>2.4, Qe of 0.4 is selected for this design. The maximum voltage gain Mg =1.25 is produced when the switching frequency is approximately 0.6 f . ∗ o When the switching frequency increases beyond 0.6 f , the voltage gain M decreases ∗ o g and the power delivered also decreases. Therefore adjusting the power level of the microwave oven can be achieved by adjusting the switching frequency beyond 0.6 f . Three switching ∗ o frequencies ( 0.625 f , f and 1.667 f ) are simulated in Pspice. The simulated output voltage as ∗ o o ∗ o a function of time is shown in Figure 4.4 for each of the three selected switching frequencies. One will notice that the steady state output voltage decreases with increasing switching frequency:</p><p>4700 V at 0.625 fo, 3980 V at fo, and 2950 V at 1.667 fo.</p><p>59 5.0KV</p><p>4.0KV</p><p>3.0KV</p><p>2.0KV</p><p>1.0KV</p><p>0V 0s 2ms 4ms 6ms 8ms 10ms V(R4:1) Time A1:(5.0000m,4.6333K) A2:(100.000p,2.1102p) DIFF(A):(5.0000m,...</p><p>(a) f 0.625f n = o</p><p>4.0KV</p><p>3.0KV</p><p>2.0KV</p><p>1.0KV</p><p>0V 0s 2ms 4ms 6ms 8ms 10ms V(C4:1) Time A1:(5.0000m,3.7793K) A2:(100.000p,2.1102p) DIFF(A):(5.0000m,...</p><p>(b) f f n = o</p><p>4.0KV</p><p>3.0KV</p><p>2.0KV</p><p>1.0KV</p><p>0V 0s 2ms 4ms 6ms 8ms 10ms V(C4:1) Time A1:(5.0000m,3.0516K) A2:(100.000p,2.1102p) DIFF(A):(5.0000m,...</p><p>(c) f 1.667f n = o Figure 4.4: Output Voltages under Different Switching Frequencies</p><p>60 50A</p><p>25A</p><p>0A</p><p>-25A</p><p>-50A 5.00ms 5.01ms 5.02ms 5.03ms 5.04ms 5.05ms 5.06ms I(LM1) I(CR1) Time A1:(5.0480m,36.443) A2:(5.0000m,27.227) DIFF(A):(48.010u,9.2...</p><p>(a) L 3 n =</p><p>50A</p><p>25A</p><p>0A</p><p>-25A</p><p>-50A 5.00ms 5.01ms 5.02ms 5.03ms 5.04ms 5.05ms 5.06ms -I(LM1) I(CR1) Time A1:(5.0100m,29.893) A2:(5.0000m,13.741) DIFF(A):(10.002u,16....</p><p>(b) L 6 n =</p><p>50A</p><p>25A</p><p>0A</p><p>-25A</p><p>-50A 5.00ms 5.01ms 5.02ms 5.03ms 5.04ms 5.05ms 5.06ms -I(LM1) I(CR1) Time A1:(5.0597m,28.633) A2:(5.0000m,9.2382) DIFF(A):(59.742u,19....</p><p>(c) L 9 n =</p><p>Figure 4.5: Resonant Current Ir and Magnetizing Current Im under Different Ln 61 4.1.4 The Resonant Currents Under Different Inductor Ratio Ln (Lm/Lr )</p><p>Ln is defined as the ratio between Lm and Lr in Equation 2.23. Ln is a critical parameter to determine the operation of the resonant converter. During the exploration using the simulation, a problem emerged. The peak of the current Im is too large and almost equals to the peak of the current Ir when Ln is small. That means a substantial current flows through the magnetizing inductor which will cause a lot of loss.</p><p>Increasing the magnetizing inductance can reduce the current Im. Because the slope of the Im vs. time is inversely proportional to the magnetizing inductance Lm. Therefore a larger</p><p>Lm (also means a larger Ln) will reduce the peak of the current Im substantially. The resonant current Ir and the magnetizing current Im are simulated under three different Ln. They are shown in Figure 4.5.</p><p>4.1.5 Soft Switching Realization</p><p>As discussed in subsection 2.3.3, the zero-voltage switching (ZVS) during the MOSFET turn-on transition is one of the benefit of using the LLC resonant topology. The ZVS MOSFET turn-on transition is shown in Figure 4.6. Before the MOSFET Q2 is turned on, the voltage drop of Q2 has already reduced to 0 (closely) because of the conduction of the MOSFET body diode.</p><p>Soft switching is also realized on the secondary rectifier <a href="/tags/Diode/" rel="tag">diodes</a>. The current flowing in the rectifier diodes is the current difference between Ir and Im. As observed in Figure 2.15, Ir and Im has an intersection period. This intersection period is the transition between two PWM signals. The diode current Id is zero during the intersection period. As shown in Figure 4.7, the diode current is reduced to zero before it turns off. This is called zero-current switching (ZCS) which reduces the switching loss substantially.</p><p>62 20.00</p><p>10.00</p><p>0</p><p>-10.00</p><p>-16.79 6.656100ms 6.656200ms 6.656300ms 6.656400ms V(HS_DRI,OUT) V(LS_DRI) V(0,OUT) Time</p><p>Figure 4.6: MOSFET(Q2) Turn on at Zero Voltage</p><p>1.0A 4.0KV 1 2</p><p>0.8A</p><p>3.0KV</p><p>0.6A</p><p>2.0KV</p><p>0.4A</p><p>1.0KV</p><p>0.2A</p><p>>> 0A 0V 6.152ms 6.156ms 6.160ms 6.164ms 6.168ms 1 I(D8) 2 -V(D8:A,D8:C) Time</p><p>Figure 4.7: Rectifier Diode(D3) Turn off at Zero Current</p><p>63 4.1.6 Soft Start</p><p>Due to the large resonant capacitance, filtering capacitance and parasitic capacitance, the start- up current can be huge. The huge start-up current of the resonant converter can damage the devices and produce a large scale EMI.</p><p>As analyzed in Chapter 2, the voltage gain Mg has a much smaller value under a high switching frequency which is shown in Figure 2.12. Based on this characteristic, the start-up current can be controlled by using a high frequency PWM to obtain a low output voltage. Thus the start-up current can be smaller. A DSP can be used to produce a high switching frequency during startup and the design switching frequency during steady state operation. The simulations of the start-up current under different frequencies are shown in Figure 4.8.</p><p>64 300A</p><p>200A</p><p>100A</p><p>0A</p><p>-100A</p><p>-200A</p><p>-300A 0s 0.5ms 1.0ms 1.5ms 2.0ms I(CR1) Time A1:(46.678u,240.565) A2:(100.000p,-2.8476m) DIFF(A):(46.678u...</p><p>(a) f 80kHz s =</p><p>300A</p><p>200A</p><p>100A</p><p>0A</p><p>-100A</p><p>-200A</p><p>-300A 0s 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms I(CR1) Time A1:(7.9729u,54.655) A2:(112.500p,-3.2042m) DIFF(A):(7.9728u,...</p><p>(b) f 250kHz s =</p><p>300A</p><p>200A</p><p>100A</p><p>0A</p><p>-100A</p><p>-200A</p><p>-300A 0s 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms I(CR1) Time A1:(9.974u,37.666) A2:(100.000p,-2.8476m) DIFF(A):(9.974u,37...</p><p>(c) f 500kHz s = Figure 4.8: Start Resonant Current under Different Frequencies</p><p>65 4.2 Experiment Results Discussion</p><p>The experiment tested is implemented based on the designed Prototype which is shown in the</p><p>Figure 4.9. The complete circuit was tested using a low voltage power supply and a resistive load.</p><p>A 6 V DC voltage was adopted as the input of the MOSFET bridge. The circuit was not tested at full voltage(and full load) due to a failure in the input full wave rectifier. The two complementary</p><p>PWM signals from the DSP are shown in the Figure 4.10. There is a 100 ns dead time between the turn-on statuses of two MOSFETs.</p><p>Figure 4.9: Picture of the System Prototype</p><p>66 Figure 4.10: Two Complementary PWM Signals from DSP</p><p>The two complementary PWM signals are amplified by the driver IC, and the voltage of the turn-on stage is increased to 13.6 V which is shown in Figure 4.11 in order to drive the gates of the MOSFETs. The MOSFET switching waveform (channel 1) is shown in Figure 4.12,.</p><p>Figure 4.11: Two Complementary PWM Signals from Driver IC</p><p>67 Figure 4.12: MOSFET Switching Waveform</p><p>The two MOSFETs alternatively conducts. The DC voltage applied on the MOSFET bridge is chopped into a square wave which has a frequency the same as the switching frequency. As shown in the Figure 2.11, the voltage of the primary side of the transformer is close to the square</p><p>Vge, because the voltage drop on the Cr and Lr is close to 0V around the switching frequency fo.</p><p>The voltage on the secondary side of the transformer is also a square wave due to the clamping of the output capacitors. The voltage on the secondary side of the transformer is measured as in</p><p>Figure 4.13. The peak to peak secondary voltage is about 150 volts as shown in Figure 4.13. The input voltage from the MOSFETs is about 6 volts, which gives a voltage gain of about 25 for this low voltage test.</p><p>68 Figure 4.13: The Voltage on the Secondary Side of the Transformer(yellow);PWM signal (blue)</p><p>Finally the square wave output voltage of the secondary side of the transformer is doubled by the half-wave voltage doubler and filtered by the capacitor. The output voltage is a DC voltage which will be applied on the testing load. The output voltage on the load is shown in</p><p>Figure 4.14.The volts per division in Figure 4.14 is 50 V.</p><p>Figure 4.14: DC Output Voltage</p><p>The design specify a voltage gain of 40 from the input to the load. However the voltage 69 gain from the input to the load is around 25. The voltage gain is much lower than expectation because of the voltage drop on the MOSFETs and the transformer core. When the input voltage is improved to the 108 V nominal rectified grid voltage, the effects of the the voltage drop on the</p><p>MOSFETs and the transformer core can be ignored.</p><p>70 CHAPTER 5: CONCLUSION AND FUTURE WORK</p><p>This thesis designed a soft switching power supply forg magnetrons. The design includes the theoretical analysis, math derivation, simulation and hardware implementation.The soft switching power supply adopted a LLC based main circuit. The main circuit is analyzed step by step to show how the resonant network works. The mathematical derivation of the voltage gain gave a good guidance on analysis. The open-loop main circuit was simulated by Pspice.All the analyses are verified by the simulation results.</p><p>The main part of this thesis is the hardware design and implementation. The hardward design includes the integrated transformer design, inductor design, driver circuit, mixed-signal circuit,and firmware debugging. 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