Testing of an Optimised Data Bus for Pico- and Nanosatellites Making Cubesats Future-Proof
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Testing of an Optimised Data Bus for Pico- and Nanosatellites Making CubeSats Future-Proof by Stefan van der Linden to obtain the degree of Master of Science at the Delft University of Technology, to be defended publicly on Thursday January 26, 2017 at 14:00. Student Number: 4082346 Project Duration: April 12, 2016 – January 26, 2017 Thesis Committee: Ir. B.T.C. Zandbergen, TU Delft, SSE (Head of Committee) Ir. J. Bouwmeester, TU Delft, SSE (Supervisor) Ir. C. De Wagter, TU Delft, C&S J. Carvajal Godinez, TU Delft, SSE An electronic version of this thesis is available at http://repository.tudelft.nl/. Abstract The definition of the CubeSat is already nearly two decades old. This results in the trend that a large fraction of CubeSat missions are leaving the domain of (educational) technology demon- stration and entering that of commercial applications. Therefore a larger focus is put on the reliability and compatibility of commercial of the shelf systems and the spacecraft containing them. One subsystem that is more or less fixed since the first CubeSat missions is the serial data bus. This internal network is essential for interconnecting subsystems. However, recent investiga- tions have shown that the industry standard I2C must be re-evaluated due to performance and reliability restrictions. The research contained in this thesis sets off to evaluate these charac- teristics of other data bus standards to propose a possible future-proof data bus architecture. By splitting up the analysis cases into two parts, the choice and design of both parts can be optimised. The Telemetry and Command (TC) bus carries essential commands and house- keeping data between systems, while the Payload (PL) bus is dedicated to high speed bulk data transfers. An initial requirement-based selection of bus standards reduced the selection of standards to several options for both bus cases; for the TC bus, I2C, CAN and RS485 were selected. For the PL bus, CAN, RS485, SPI and USB were selected. The selected standards were all implemented in a data bus testing suite, comprising of up to nine simulated subsystems providing pseudo data to be communicated over the bus. Mea- surements were conducted of the buses’ power consumption and data rates in several realistic test cases. Furthermore, the complexity and ability to withstand noise and voltage transients were evaluated. Ultimately, this resulted in a recommendation of using RS485 in future TC bus configurations and SPI in the PL bus configurations. However, this conclusion must be regarded a recommended direction of future research for several reasons. Firstly, more in- vestigations are needed in the ability of these buses to work when subjected to large amounts of noise and other extreme environments. Secondly, the performed trade-off does not ap- ply weighting to its criteria, as these can and will vary wildly for different missions. Finally, the test setup was limited in terms of processor ability for the PL bus case. These specific tests should therefore be redeveloped with more powerful equipment, allowing an even more realistic simulation of future CubeSat subsystems. iii Acknowledgements This thesis, and hence my educational career, would never have been completed without the help and support from a large number of people. First of all, I am extremely thankful to my daily supervisor Jasper Bouwmeester for the con- tinuous help and support during the entire thesis project. Many thanks also go out to Stefano Speretta, Tatiana Pérez Soriano, Aleš Povalač and Johan Carvajal Godinez for their help, pa- tience and the many fruitful discussions we had while I was finding my way into the diverse world of the many electrical and electronics engineering concepts. The people at two different companies have also played large roles in the development and steering of my interests into space system engineering in general and specifically in CubeSat engineering. Firstly, David Gerhardt, Jesper Abildgaard Larsen and the rest of the great team while I was at GomSpace provided an incredible amount of motivation and guidance during and after my internship. Secondly, the many people at S[&]T also provided vast amounts of inspiration and largely introduced me to the art of space and data engineering. Finally, the countless other people I want to thank, of which there are way too many to list here, are all my family and friends. My entire studies at the TU Delft would have especially been impossible without the huge amount of support from my parents, my younger brother Tristan and of course Annemiek. Thank you. Stefan van der Linden Delft, January 2017 v Contents List of Figures xi List of Tables xiii List of Symbols xv List of Abbreviations xvii 1 Introduction 1 1.1 The Data Bus. 2 1.2 Thesis Objective . 4 1.3 Thesis Outline . 5 2 Data Bus Design 7 2.1 Digital Information . 7 2.2 Open System Interconnect (OSI) Layers. 8 2.3 Bus Topologies. 10 3 Data Bus Selection 13 3.1 General Data Bus Requirements . 14 3.2 TC Bus Requirements . 16 3.3 TC Bus Selection . 18 3.4 PL Bus Requirements. 21 3.5 PL Bus Selection . 22 3.6 Conclusion . 24 4 Experimental Comparison 25 4.1 Tests and Metrics . 26 4.2 Bit Error Ratio . 26 4.3 Packet Error Ratio . 29 4.4 Data Throughput. 30 4.5 Power Consumption. 31 4.6 Noise Immunity . 31 4.7 Complexity . 32 4.8 Conclusion . 32 5 Generalised CubeSat Data Bus Simulator 33 5.1 Bus Node Hardware. 33 5.2 Physical Configuration . 35 5.3 Central Controlling Computer . 37 5.4 Simulated Subsystems . 37 5.5 OBC Software Architecture (TC Bus). 39 5.6 Subsystem Software Architecture (TC Bus) . 43 5.7 OBC Software Architecture (PL Bus) . 44 5.8 Subsystem Software Architecture (PL Bus) . 45 5.9 Conclusion . 45 vii viii Contents 6 Inter-Integrated Circuit (I2C) 47 6.1 Introduction . 47 6.2 I2C Daughterboard . 49 6.3 Differential I2C . 50 6.4 Bus Schematics . 51 6.5 Bus Software: DWire . 52 6.6 DWire in the Test Suite . 54 6.7 Results . 55 6.8 Conclusion . 60 7 Controller Area Network (CAN) 61 7.1 Introduction . 61 7.2 Error Handling . 63 7.3 CAN Controller and Transceiver. 64 7.4 Bus Schematics . 65 7.5 Software Driver Architecture . 65 7.6 Results . 70 7.7 Conclusion . 71 8 RS422 / RS485 73 8.1 Introduction . 73 8.2 Physical Layer Design . 74 8.3 Data Link Layer . 76 8.4 Results . 79 8.5 Conclusion . 84 9 Serial Peripheral Interface (SPI) 87 9.1 Introduction . 87 9.2 Physical Layer . 87 9.3 Data Link Layer . 88 9.4 Results . 90 9.5 Conclusion . 92 10 Universal Serial Bus (USB) 93 10.1 Introduction . 93 10.2 Physical Layer . 94 10.3 Data Link Layer . 95 10.4 MAX3421E Driver . 97 10.5 Results . 98 10.6 Conclusion . 99 11 Data Bus Comparison 101 11.1 Overview . 101 11.2 Data Throughput. 102 11.3 Power Consumption. 103 11.4 Complexity . 105 11.5 Noise and Transient Effects . 106 11.6 Discussion of Results . 107 12 Conclusions and Recommendations 111 12.1 TC Buses . 111 12.2 PL Buses . ..