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Asynchronous Dynamic Single-Flux Quantum Majority Gates Gleb Krylov , Student Member, IEEE, and Eby G

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Asynchronous Dynamic Single-Flux Quantum Majority Gates Gleb Krylov , Student Member, IEEE, and Eby G IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 30, NO. 5, AUGUST 2020 1300907 Asynchronous Dynamic Single-Flux Quantum Majority Gates Gleb Krylov , Student Member, IEEE, and Eby G. Friedman , Fellow, IEEE Abstract—Among the major issues in modern large-scale rapid of an SFQ pulse within a clock period. In logic gates, the single-flux quantum (RSFQ) circuits are the complexity of the input pulses are processed by switching Josephson junctions clock network, tight timing tolerances, poor applicability of (JJs), and an output pulse is produced based on the target existing CMOS-based design algorithms, and extremely deep pipelines, which reduce the effective clock frequency. In this logic function. Most RSFQ logic gates require a clock signal article, asynchronous dynamic single-flux quantum majority gates either to release the output pulse or to reinitialize the state are proposed to solve some of these problems. The proposed logic of the gate to process the next datum. A large scale circuit gates exhibit high bias margins and do not require significant area utilizing these gates requires a complex clock network. RSFQ or a large number of Josephson junctions as compared to existing circuits are capable of operating at extremely high clock fre- RSFQ logic gates. These gates exhibit a tradeoff among the input skew tolerance, clock frequency, and bias margins. Asynchronous quencies (up to hundreds of gigahertz [8]), resulting in narrow logic gates greatly reduce the complexity of the clock network timing tolerances. in large-scale RSFQ circuits, thereby alleviating certain timing Multiple synchronization approaches exist for reducing the issues and reducing the required bias currents. Furthermore, effects of timing on circuit operation. These approaches asynchronous logic allows existing design algorithms to utilize range from globally asynchronous locally synchronous tech- CMOS approaches for synthesis, verification, and testability. The adoption of majority logic in complex RSFQ circuits also reduces niques [9], [10] to fully asynchronous structures [11], [12] and the pipeline depth, enabling higher clock speeds in very large scale dual rail logic families [13]. These approaches, however, intro- integration RSFQ circuits. duce significant performance and area overhead as compared to Index Terms—Single-flux quantum (SFQ), superconductive conventional synchronous RSFQ circuits, partially negating the digital electronics, superconductive integrated circuits. primary incentives of RSFQ technology. Another distinctive feature that adversely affects the increas- I. INTRODUCTION ing integration of RSFQ circuits is limited fanout. Typical RSFQ logic gates and flip flops exhibit a fanout of one. A splitter HE slowdown in scaling of CMOS technology has led gate is used to deliver a signal to multiple inputs. This property T to increasing interest in beyond CMOS computing tech- necessitates large splitter trees that can dominate the area of nologies, including cryogenic and superconductive electronics. a complex circuit. Insertion of these splitter trees into a logic Rapid single-flux quantum (RSFQ) [1] is a well established and path increases the delay of the path, significantly reducing the widely used logic family in superconductive electronics [2]. The effective clock frequency of the overall system—degrading a increased interest [3] combined with recent advances in fabri- primary advantage of RSFQ circuits. RSFQ clock networks cation technology for single-flux quantum (SFQ) circuits [4] consist mostly of splitters, decreasing the area available for logic. provides enhanced complexity while requiring novel design Novel solutions are, therefore, necessary to either support larger algorithms, methodologies, and tools specifically targeting large fanout or to reduce the number of splitters. scale RSFQ circuits [5], [6]. Existing RSFQ circuits typically utilize AND/OR/NOT logic Distribution of the clock signals in very large scale integration with clocked AND and OR gates and, therefore, exhibit these (VLSI) RSFQ circuits is an important issue [7]. A distinctive aforementioned issues. An alternative functionally complete feature of RSFQ circuits is clocked logic gates. In SFQ tech- logic set is the MAJ/INV set, consisting of majority gates and nology, the data are represented by the presence or absence inverters. Logic synthesis utilizing MAJ/INV logic has been shown to reduce logic depth, power, and delay in both CMOS Manuscript received August 7, 2019; revised November 8, 2019; accepted benchmarks [14] and beyond CMOS technologies [15]. January 14, 2020. Date of publication March 4, 2020; date of current ver- No efficient RSFQ majority gate has currently been described sion May 5, 2020. This work was supported by the Department of Defense Agency—Intelligence Advanced Research Projects Activity through the U.S. in the literature. A majority gate is typically composed of a Army Research Office under Contract W911NF-17-9-0001. This paper was combination of AND/OR/NOT gates and requires a clock signal recommended by Associate Editor H. Rogalla. (Corresponding author: Gleb with a network of multiple splitters. This topology, therefore, Krylov.) The authors are with the Department of Electrical and Computer En- exhibits a large overhead both in area and delay and is, therefore, gineering, University of Rochester, Rochester, NY 14627 USA (e-mail: infeasible in complex circuits. In other SFQ logic families, such [email protected]; [email protected]). as quantum flux parametron (QFP) [16] and reciprocal quantum Color versions of one or more of the figures in this article are available online at http://ieeexplore.ieee.org. logic [17], majority gates exist and are widely used [18], [19]. Digital Object Identifier 10.1109/TASC.2020.2978428 1051-8223 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See https://www.ieee.org/publications/rights/index.html for more information. Authorized licensed use limited to: UNIVERSITY OF ROCHESTER. Downloaded on November 13,2020 at 23:35:30 UTC from IEEE Xplore. Restrictions apply. 1300907 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 30, NO. 5, AUGUST 2020 Fig. 1. DSFQ storage loops. (a) Traditional dynamic loop. (b) Novel dynamic loop introduced in [20]. Fig. 2. Loop current (a) within a loop with a single time constant (dashed line) and (b) within a loop with dual time constants (solid line). In this article, novel asynchronous RSFQ majority gates are proposed based on a recently introduced dynamic SFQ (DSFQ) Self-resetting storage loops have been used for many years logic family [20]. In Section II, a discussion of DSFQ is pro- and utilize either resistors or overdamped JJs inserted within the vided, and the benefits of DSFQ storage loops are discussed. loops for flux leakage [21]–[23]. These loops exhibit a narrow In Section III, circuit design issues and related parameters for timing tolerance due to a nearly constant rate of flux leakage, DSFQ loops are discussed. In Section IV, majority gates are controlled by a single time constant. An example of this type of introduced, the operation of these gates is described, and margin dynamic loop is shown in Fig. 1(a). A recently introduced DSFQ characteristics are presented. In Section V, the application of storage loop [20], shown in Fig. 1(b), utilizes a critically damped majority gates to VLSI RSFQ circuits is discussed. Finally, JJ in parallel with a JJ in series with a resistor to reset the state. Section VI concludes this article. This topology produces two different time constants, for hold and reset, combining the slow leakage process during the hold period with fast relaxation to the initial state. A comparison of II. DSFQ STORAGE LOOPS the current stored within a dynamic loop with single and double A novel family of asynchronous RSFQ logic gates—DSFQ time constants, exhibiting a twofold increase in hold time, is gates—is discussed in this section. DSFQ [20] is a recently shown in Fig. 2. introduced type of RSFQ logic, where the state of a gate is Novel DSFQ logic gates [20] combine the self-resetting stor- temporarily stored, and the gate self-resets to the initial state age loops with existing RSFQ circuits to achieve AND and OR after a period of time. This capability enables asynchronous logic functions. As the inversion operations can be propagated operation, significantly reducing the size and energy require- to the boundary of the combinatorial logic clouds [24] and ments of complex clock networks in large scale RSFQ circuits. integrated into registers with complementary outputs, these gates DSFQ circuits are more similar to CMOS than regular RSFQ produce a functionally complete set. circuits and can be separated into sequential and combinatorial In the following section, operation of DSFQ storage loops is logic [20], enabling the use of relevant CMOS design techniques described. The effects of different circuit parameters are also and algorithms. discussed. The primary features of DSFQ are self-resetting storage loops, as shown in Fig. 1. In conventional RSFQ, logic gates contain III. CIRCUIT DESIGN OF DYNAMIC LOOPS storage loops, which temporarily store a state based upon the input pulses received by the gate. The state of these storage In this section, the operation and circuit components of DSFQ loops is typically reset by either the clock pulse (e.g., DFF) or loops are described. The effects of these components on the by another input pulse (e.g., Muller C element). In the absence operation of the logic gate are discussed, and guidelines for of a reset pulse, logic gates can store a state indefinitely. This these parameters are provided. capability greatly complicates the application of certain CMOS DSFQ storage loops require a leakage mechanism for the techniques to RSFQ circuits and exacerbates flux trapping ef- magnetic flux to escape a superconductive loop. In the DSFQ fects, while increasing the complexity of the clock network. loop shown in Fig. 1(b), a combination of JJs and resistors is Authorized licensed use limited to: UNIVERSITY OF ROCHESTER. Downloaded on November 13,2020 at 23:35:30 UTC from IEEE Xplore.
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