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Superconducting Microelectronics for Next-Generation Computing

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Superconducting Microelectronics for Next-Generation Computing Superconducting Microelectronics for Next-Generation Computing Leonard M. Johnson 2018 MIT Research and Development Conference 14 November 2018 DISTRIBUTION STATEMENT A. Approved for public release. © 2018 Massachusetts Institute of Technology. Distribution is unlimited. Delivered to the U.S. Government with Unlimited Rights, as defined in This research was funded by the Office of the Director of National Intelligence DFARS Part 252.227-7013 or 7014 (Feb 2014). Notwithstanding any (ODNI), Intelligence Advanced Research Projects Activity (IARPA) under Air copyright notice, U.S. Government rights in this work are defined by DFARS Force Contract No. FA8721-05-C-0002. The views and conclusions contained 252.227-7013 or DFARS 252.227-7014 as detailed above. Use of this work herein are those of the authors and should not be interpreted as necessarily other than as specifically authorized by the U.S. Government may violate representing the official policies or endorsements, either expressed or implied, any copyrights that exist in this work. of ODNI, IARPA, or the US Government. Computing Development Timeline Triode vacuum Transistor First fully transistor- 30k transistors: 4.5M transistors: 19.2B transistors: ENIAC tube invented invented based computer: TX-0 i8088 Pentium 32-core Epyc GPU 1907 1946 2017 1971 Vacuum tubes Discrete Bipolar transistor CMOS transistors integrated circuits integrated circuits Superconducting Elec - 2 *RSFQ: Rapid Single Flux Quantum L. M. Johnson 11/14/2018 **AQFP: Adiabatic Quantum Flux Parametron Computing Development Timeline Triode vacuum Transistor First fully transistor- 30k transistors: 4.5M transistors: 19.2B transistors: ENIAC tube invented invented based computer: TX-0 i8088 Pentium 32-core Epyc CPU 1907 1946 2017 1971 Vacuum tubes Cryotron IBM Latching Logic RSFQ* Circuits AC-Clocking AQFP** Circuits Superconducting Elec - 3 *RSFQ: Rapid Single Flux Quantum L. M. Johnson 11/14/2018 **AQFP: Adiabatic Quantum Flux Parametron Computing Application Space Wearables / Implants Personal Computing Centralized Computing Titan Supercomputer at ORNL Facebook Data Center Low Power, Limited Processing High Power, Massive Processing Superconducting Elec - 4 L. M. Johnson 11/14/2018 High Performance Computing (HPC) Energy Consumption Limitations • Exascale computer projected to consume ~100 MW HPC Energy Consumption Trends with existing approaches 1000 – ~1 B kW-h / year 10 best supercomputers – ~$50M / year for electricity (without cooling) • DOE and IARPA charged with realizing aggressive exascale computing power consumption goals 100 2 GFLOPS/Watt Tianhe-2 DOE Target GFLOPS/Watt K-Computer 14 Sunway Summit 10 Titan/Sequoia Tiahu Light Mirra IARPA Target Power consumption (MW) 1 1 10 100 1000 Supercomputer performance (Peta FLOPS) Superconducting Elec - 5 L. M. Johnson 11/14/2018 Outline • Introduction to Superconducting Electronics • Technology Development for Digital Computing • Additional Applications Superconducting Elec - 6 L. M. Johnson 11/14/2018 First Superconducting Device - Cryotron I-V Curve for Superconducting Wire V T >T • Superconductivity c – Zero dc electric resistance at T < Tc ‘1’ • Cryotron S→N – Developed at MIT Lincoln Laboratory by Dudley Allen ‘0’ Ic I Buck in 1950s – Information encoded in the superconducting and normal states of a wire – Tantalum wire with wound copper heater Vacuum – Achieved 5-ms switching tube – Spawned research efforts at IBM, RCA, and GE – Speed and power never outperformed transistors Cryotron and efforts were abandoned Transistor Superconducting Elec - 7 L. M. Johnson 11/14/2018 Computing with Superconductivity - Josephson Tunneling Logic Josephson Junction (JJ) I S2 • Josephson tunneling and Josephson junction – Superconductor-Insulator-Superconductor ~ 1-nm-thick JJ - a “weak link” between insulator two superconductors • Josephson Tunneling Logic – Information encoded in the normal and superconducting states of the JJ S1 – Ultrafast, ~ 1 ps S → N switching by current I > Ic – Slow, ~ 1 ns N → S switching back I-V Characteristics of Josephson junction – ~100 person effort at IBM from 1970 to 1982 – No path identified to outperform transistors V ‘1’ ~2.5 mV S→N ‘0’ Ic I Superconducting Elec - 8 L. M. Johnson 11/14/2018 Computing with Superconductivity Single Flux Quantum, 1985 - Present • Flux in a superconducting loop is quantized Josephson Junction in Superconducting Loop – Φ = nΦ0, Φ0 - magnetic flux quantum Φ = nΦ0 B Φe • Addition of Josephson junction (JJ) in Is superconducting loop allows switching JJ Persistent current Φ – Generates a quantized Single Flux Quantum (SFQ) voltage pulse S • Ultrafast switch is made from shunted JJ – Voltage waveform at I > Ic: periodic ~ 1-ps pulses Resistively Shunted Josephson Junction (JJ) • Ultralow switching energy of ~10-19 J V • Single Flux Quantum (SFQ) logic/memory Ib Rsh – Proposed in 1985; thousands of circuits demonstrated JJ N time – DC bias (early versions), synchronous / asynchronous I clocking S I – Recent SFQ logic families nearly eliminate DC bias c power Superconducting Elec - 9 L. M. Johnson 11/14/2018 SCE as Candidate for a Beyond CMOS Technology Ultralow Logic Energy and High Speed Lossless Data Transmission Speed of light 10-15 CMOS TFETs STOlogic GpnJ STT/DW -16 High PowerSpinFET Spin-based ~ 1 ps 10 STT/ SpinFET NML CMOS LP DW CMOS HP -17 HJ TFET CMOS0.3 V InA s 10 Low Power (J) IIIvTFET STTtriad E (J) E 0.3V InAs STM G D -18 gnrTFET 10 SWDSWD ERSFQ RQL -19 10 Switching AQFP • Superconductive transmission -20 10 Qu antu m 'limit', Superconducting Adiabatic lines provide lossless on-chip Superconducting -21 nSQUID data transmission 10 D Et = h Switching Energy – Preserves ~1 ps SFQ pulses (no -22 Landauer’s Switching energy, energy, Switching 10 k T ln2 @ 4.2 K B thermodynamic dispersion) 10-23 limit, !"#$%& 0.1 1 10 100 1000 • Solution to high energy overhead Delay, t (ps) of data movement in conventional processors Superconducting Elec - 10 L. M. Johnson 11/14/2018 The Fastest Digital Technology 1/2 • Clock speed of SFQ circuits increases as (Jc/Cs) • Early SFQ development emphasized high-speed 1000 AB limit demonstration of small-scale circuits 800 Pair breaking in Nb wiring f • 770 GHz maximum frequency of operation of SFQ 2D 600 static frequency dividers (T Flip-Flop) was demonstrated at Stony Brook University ~ 20 years ago 400 MIT LL HYPRES 200 HYPRES+SUNY SB NGST SUNY SB plasma frequency f p Maximum TFF Divider Frequency (GHz) Frequency Divider TFF Maximum 1 10 100 Josephson Junction Critical Current Density (kA/cm2) SUNY Stony Brook 0.3-µm, 140 kA/cm2, CMP Nb Josephson fabrication process Superconducting Elec - 11 L. M. Johnson 11/14/2018 Outline • Introduction to Superconducting Electronics • Technology Development for Digital Computing • Additional Applications Superconducting Elec - 12 L. M. Johnson 11/14/2018 Superconducting Electronic (SCE) Circuit Trends (pre 2011) SFQ Circuit Level of Integration pre 2011 Issues Contributing to 20,000 JJ limit 10 7 • Primary focus on high-clock-speed circuit HYPRES NEC-ISTEC demonstrations, not larger-scale circuits 10 6 ISTEC-AIST D-Wave Systems • RSFQ circuit design limitations 5 – Parallel current biasing: Ib ∝ number of JJs 10 – Required dc bias current of over 2 A into small chips 4 – Relatively large bias currents cause spurious 10 doublingDoubling every every 4.5 years 4.5 years magnetic fields that interfere with the SFQ pulse propagation 10 3 • Unsophisticated circuit design tools • Outdated fabrication equipment 10 2 1990 1995 2000 2005 2010 2015 2020 Number JJs in operational SCE circuits Year Superconducting Elec - 13 L. M. Johnson 11/14/2018 SFQ Logic Families Adiabatic Quantum Flux Parametron (AQFP) Energy-Efficient RSFQ (ERSFQ) • Developed by Hypres, Inc. • Eliminates resistor-based bias network Reciprocal Quantum Logic Q (4) (RQL) (2) I • Developed by Northrop Grumman (1) (3) • Based on AC biasing I+ Superconducting Elec - 14 L. M. Johnson 11/14/2018 Nominal Energy per Operation for Beyond-CMOS Technologies Computation Nominal Device Interconnect Cooling Device Type Energy per Energy (aJ) Factor Factor Operation (aJ) Commercial State-of-the-Art HP CMOS 18 100x 1.5x 2700 Today LP CMOS Advanced 3.3 100x 1.5x 500 Semiconductor 0.3-V InAs Technologies ~10x Tunneling FETs 1.5 100x 1.5x 220 improvement Switching SFQ 0.1 1x 500x 50 @ 4 K Superconducting ~500x AQFP @ 4 K 0.01 1x 500x 5 Technologies improvement Nearly reversible 0.001 1x 500x 0.5 @ 4 K Superconducting electronics offers orders of magnitude reduction in energy consumption, even with requirement to cool to 4 K temperature Superconducting Elec - 15 L. M. Johnson 11/14/2018 State-of-the-Art Superconducting Circuit Fabrication HYPRES 4-Layer Process (USA) AIST 10-Nb-Layer (Japan) D-Wave Systems 6-Nb-Layer MIT LL 8-Nb-Layer Process 1 μm Wafer size 150 mm 75 mm 200 mm 200 mm Number of Nb layers 4 9 and 10 6 8 and 9 Planarization No planarization Partial planarization Full planarization Full planarization Min wiring feature size ~ 1 μm ~ 1 μm 250 nm 350 nm Min JJ size ~ 1.5 μm ~ 1.2 μm 600 nm 700 nm Integration scale 11k JJs 80k JJs 128k JJs 810k JJs Superconducting Elec - 16 L. M. Johnson 11/14/2018 *AIST: National Institute of Advanced Industrial Science and Technology, Japan Contrast to 90nm FDSOI CMOS Fabrication Process 90-nm FDSOI CMOS Cross Section Superconducting Electronics Cross Section Passive Active Layers Wiring Layers JJs, resistors Interconnect, vias, inductors Passive Wiring Layers interconnect, Active Layers vias, inductors Transistors, capacitors, resistors
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