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L02-Architecture 1/15/2019 Overview of Architecture Spring 2019 EE3954: Microprocessors and Microcontrollers Avinash Karanth Professor, Electrical Engineering and Computer Science Ohio University E-mail: [email protected] Acknowledgment: Harsha Chenji, Jim Goble, Maarten Uijt de Haag 1 1 Course Administration • Course website up and working at http://ace.cs.ohio.edu/~avinashk/classes/ee3954/ee3954.htm • Jan 14 and today’s lecture posted • Forming Laboratory Teams (passed the sheet) • Lab 1 will be posted by Friday Jan 18 • Pre-lab work is required to work in the lab! 2 2 1 1/15/2019 Topics to be covered • Types of Architecture • Instruction Sets • Pipelining (example) • Microcontroller Architecture 3 3 Information in Computing Systems Instructions Fixed-point Information Numbers Data Floating-point Non-numerical data : (text, graphics, music, etc) Stored in Memory and Registers Instruction: operation or control words Data: operands 4 4 2 1/15/2019 Processor Organization • Control needs to • Input instructions from memory CPU Memory Devices • Issue signals to control the control input information flow between datapath components and to control what operations they Datapath output perform • Control instruction sequencing • Datapath needs to have the Fetch • Components – the functional units and storage needed to execute instructions Exec Decode • Interconnects – components connected so that instructions can be routed, and data loaded from and stored into memory 5 5 Types of Architectures Advantages/disadvantages? 6 6 3 1/15/2019 Perspective! 1. Memory was expensive! 2. AND/OR gates, diodes, vacuum tubes 7 7 Harvard vs. Von Neumann • Program memory and Data memory are separate physical memories. • Program memory fetches and Data memory fetches can occur simultaneously. • Program & Data memory have separate address bus/data bus – therefore separate address registers for program and data fetching. 8 8 4 1/15/2019 Where do ISA fit in a computing system? Application Software Compiler Architecture – (Instruction Set Architecture) - Platform Specific - a limited number of assembly language commands understood by the hardware (ADD, LOAD, etc) Software Hardware Microarchitecture (Hardware Implementation of ISA) - Pentium IV implements x86 ISA - Motorola G4 implements the Power PC ISA Circuits Devices 9 Instruction Set Design (1/2) • What instructions should be included? • Add, Multiply, Divide, Srqt [functions] • Branch [flow control] • Load/store [storage management] • What storage locations? • How many registers? • How much memory? • How should instructions be formatted? • 0, 1, 2 or more operands • Immediate operands 10 5 1/15/2019 Instruction Set Design (2/2) • How to encode instructions? • RISC (Reduced Instruction Set Computer) • All instructions are the same length (Eg: MIPS, PowerPC, Sun UltraSparc, XAP Processor, ARM processor) • CISC (Complex Instruction Set Computer) • Instructions can vary in size (Eg. VAX, Intel x86) • What instructions can access memory? • For RISC, only load/store can access memory (load- store architecture) • For CISC, memory manipulation instructions are possible 11 Software Program to Machine Code Compile Assemble main() .text { .global main 0x7456 int a, *b, c; lw $s1, 100($0) 0xA16B c = a + b; add $s1, $s2, } $s3 C Program Assembly code Machine code 12 6 1/15/2019 Manuals and Data Sheets: PIC16(L)F18875 • C Compiler Optimized RISC Architecture • Only 49 Instructions • Operating Speed: • DC – 32 MHz clock input • 125 ns minimum instruction cycle • Interrupt Capability • 16-Level Deep Hardware Stack • Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT) Extensions • Four 16-Bit Timers (TMR0/1/3/5) • Memory • Up to 14 KB Flash Program Memory (8K for us.) • Up to 1 KB Data SRAM • 256B of EEPROM 13 13 PROGRAM HARVARD ARCHITECTURE MEMORY PROGRAM BUS 14 14 7 1/15/2019 HARVARD ARCHITECTURE DATA MEMORY DATA BUS 15 15 Clocks and Timing • Clocks are the “heartbeat” • For every tick, something gets done • Purchase performance using hardware • Chip area, power, gates, silicon • Today’s processors: nano/pico seconds 16 16 8 1/15/2019 Clock Cycles and Instruction Cycles Instruction Cycle Clock Cycles f f = OSC T = 4T CY 4 CY OSC Example! 17 17 Q-cycle Activity- Inst. Fetch Q1 Q3 Increment Program Counter Nothing done Q4 Instruction Written to Instruction Register Q2 Nothing done 18 18 9 1/15/2019 Q-cycle Activity- Execute Q1 Q3 Instruction Decode Cycle Process the Data (or Forced No Operation) (ALU) Q4 Instruction Write Q2 Data Cycle Instruction Read (or Forced No Operation) Data Cycle (or Forced No Operation) 19 19 Pipelining • Doing the laundry 20 20 10 1/15/2019 Pipelining • Do it faster (but with more workers/people) 21 21 Pipeline Example (Example 4-1) TCY0 TCY1 TCY2 TCY3 TCY4 1. MOVLW 55H Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 Fetch 3 Execute 3 3. CALL SUB_1 Fetch 4 Flush 4 4. BSF PORTA,3 Fetch SUB_1 . … … X. SUB_1: . … … 22 22 11 1/15/2019 Instruction ADDWF 0x34,F – FETCH: Q1,Q2,Q3,Q4 23 23 Instruction ADDWF 0x34,F – EXECUTE: Q1 (Instruction Decode) 24 24 12 1/15/2019 Instruction ADDWF 0x34,F – EXECUTE: Q2 (fetch data) 25 25 Instruction ADDWF 0x34,F – EXECUTE: Q3 (ALU performs operation) 26 26 13 1/15/2019 Instruction ADDWF 0x34,F – EXECUTE: Q4 ( data written to destination) 27 27 Peripherals 28 28 14.
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