The Computer Organization and Design Underneath the Execution of C Programming Language Mingkai Li1 1University of Science and Technology of China
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Second-Generation Stack Computer Architecture
Second-Generation Stack Computer Architecture Charles Eric LaForest A thesis presented to the Independent Studies Program of the University of Waterloo in fulfilment of the thesis requirements for the degree Bachelor of Independent Studies (BIS) Independent Studies University of Waterloo Canada April 2007 ii Declaration I hereby declare that I am the sole author of this research paper. I authorize the University of Waterloo to lend this thesis to other institutions or individuals for the purpose of scholarly research. Signature: I further authorize the University of Waterloo to reproduce this research paper by photocopy- ing or other means, in total or in part, at the request of other institutions or individuals for the purpose of scholarly research. Signature: The work in this research paper is based on research carried out in the Independent Studies Program at the University of Waterloo, Canada. No part of this thesis has been submitted else- where for any other degree or qualification and is all my own work unless referenced to the contrary in the text. Copyright c 2007 by Charles Eric LaForest. The copyright of this thesis rests with the author. Quotations and information derived from it must be acknowledged. iii Second-Generation Stack Computer Architecture Charles Eric LaForest Submitted for the degree of Bachelor of Independent Studies April 2007 Abstract It is commonly held in current computer architecture literature that stack-based computers were entirely superseded by the combination of pipelined, integrated microprocessors and improved compilers. While correct, the literature omits a second, new generation of stack computers that emerged at the same time. -
Second-Generation Stack Computer Architecture
Second-Generation Stack Computer Architecture Charles Eric LaForest A thesis presented to the Independent Studies Program of the University of Waterloo in fulfilment of the thesis requirements for the degree Bachelor of Independent Studies (BIS) Independent Studies University of Waterloo Canada April 2007 ii Declaration I hereby declare that I am the sole author of this research paper. I authorize the University of Waterloo to lend this thesis to other institutions or individuals for the purpose of scholarly research. Signature: [:.,,,u..c ;(~ I further authorize the University of Waterloo to reproduce this research paper by photocopy ing or other means, in total or in part, at the request of other institutions or individuals for the pUipose of scholarly research. SignatUI·e: 6 ~ >{!. The work in this research paper is based on research carried out in the Independent Studies Program at the University of Waterloo, Canada. No part of this thesis has been submitted else where for any other degree or qualification and is all my own work unless referenced to the contrary in the text. Copyright© 2007 by Charles Eric La Forest. The copyright of this thesis rests with the author. Quotations and infonnation derived from it must be acknowledged. Ill Second-Generation Stack Computer Architecture Charles Eric LaForest Submitted for the degree of Bachelor of Independent Studies April 2007 Abstract It is commonly held in current computer architecture literature that stack-based computers were entirely superseded by the combination of pipelined, integrated microprocessors and improved compilers. While correct, the literature omits a second, new generation of stack computers that emerged at the same time. -
LC-3B Simulator
CENG3420 Lab 2-1: LC-3b Simulator Bei Yu Department of Computer Science and Engineering The Chinese University of Hong Kong [email protected] Spring 2018 1 / 29 Overview LC-3b Basis LC-3b Assembly Examples LC-3b Simulator Task 2 / 29 Overview LC-3b Basis LC-3b Assembly Examples LC-3b Simulator Task 3 / 29 Assembler & Simulator I Assembly language – symbolic (MIPS, LC-3b, ...) I Machine language – binary I Assembler is a program that I turns symbols into machine instructions. I EX: lc3b_asm, SPIM, ... I Simulator is a program that I mimics the behavior of a processor I usually in high-level language I EX: lc3b_sim, SPIM, ... 3 / 29 LC-3b I LC-3b: Little Computer 3, b version. I Relatively simple instruction set I Most used in teaching for CS & CE I Developed by Yale Patt@UT & Sanjay J. Patel@UIUC 4 / 29 LC-3 Architecture I RISC – only 15 instructions I 16-bit data and address I 8 general-purpose registers (GPR) Plus 4 special-purpose registers: I Program Counter (PC) I Instruction Register (IR) I Condition Code Register (CC) I Process Status Register (PSR) 5 / 29 Memory 2k × m array of stored bits: Address I unique (k-bit) identifier of location I LC-3: k = 16 Contents I m-bit value stored in location I LC-3: m = 16 Basic Operations: I READ (Load): value in a memory location ! the Processor I WRITE (Store): value in the Processor ! a memory location 6 / 29 Interface to Memory How does the processing unit get data to/from memory? I MAR: Memory Address Register I MDR: Memory Data Register To LOAD from a location (A): 1. -
Computer Architecture (TT 2011) the MIPS/DLX/RISC Architecture
Computer Architecture (TT 2011) The MIPS/DLX/RISC Architecture Daniel Kroening Oxford University, Computer Science Department Version 1.0, 2011 Outline ISAs Overview MIPS/DLX Instruction Formats D. Kroening: Computer Architecture (TT 2011) 2 Roadmap for today I We will discuss Instruction Set Architectures (ISAs) I These summarise the behavior of a CPU from the point of view of the programmer I An ISA describes “what the CPU does” I Ideally as little as possible about “how the CPU does it” D. Kroening: Computer Architecture (TT 2011) 3 I We will study two ISAs: 1. RISC: specifically the DLX (academic variant of the MIPS R3000) 2. CISC: specifically the Y86 (academic variant of Intel’s x86) I One of the goals of this course is to understand the difference D. Kroening: Computer Architecture (TT 2011) 4 History MIPS/DLX I 1981: John L. Hennessy, Stanford University I 1984: MIPS Computer Systems I 1985: R2000 released I 1988: R3000 released (used e.g., by SGI) I 1991: R4000 released (64 bits) I Now primarily licensed as IP, built by numerous vendors, with focus on low-end embedded systems D. Kroening: Computer Architecture (TT 2011) 5 Overview MIPS/DLX memory memory I/O module module (USB, ...) MIPS Processor data PC R0 R1 address R2 R3 control R4 ... I Programs and data are held in the same memory I I/O is also done via “memory” (memory-mapped I/O) D. Kroening: Computer Architecture (TT 2011) 6 Visible Registers I RAM, organised in 32-bit words I Registers I R0 to R31 I R0 is a special case: value is hardwired to 0 I Usual MIPS notation: $0 .