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Computer Architecture (TT 2011) the MIPS/DLX/RISC Architecture

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Computer Architecture (TT 2011) The MIPS/DLX/RISC Architecture Daniel Kroening Oxford University, Computer Science Department Version 1.0, 2011 Outline ISAs Overview MIPS/DLX Instruction Formats D. Kroening: Computer Architecture (TT 2011) 2 Roadmap for today I We will discuss Instruction Set Architectures (ISAs) I These summarise the behavior of a CPU from the point of view of the programmer I An ISA describes “what the CPU does” I Ideally as little as possible about “how the CPU does it” D. Kroening: Computer Architecture (TT 2011) 3 I We will study two ISAs: 1. RISC: specifically the DLX (academic variant of the MIPS R3000) 2. CISC: specifically the Y86 (academic variant of Intel’s x86) I One of the goals of this course is to understand the difference D. Kroening: Computer Architecture (TT 2011) 4 History MIPS/DLX I 1981: John L. Hennessy, Stanford University I 1984: MIPS Computer Systems I 1985: R2000 released I 1988: R3000 released (used e.g., by SGI) I 1991: R4000 released (64 bits) I Now primarily licensed as IP, built by numerous vendors, with focus on low-end embedded systems D. Kroening: Computer Architecture (TT 2011) 5 Overview MIPS/DLX memory memory I/O module module (USB, ...) MIPS Processor data PC R0 R1 address R2 R3 control R4 ... I Programs and data are held in the same memory I I/O is also done via “memory” (memory-mapped I/O) D. Kroening: Computer Architecture (TT 2011) 6 Visible Registers I RAM, organised in 32-bit words I Registers I R0 to R31 I R0 is a special case: value is hardwired to 0 I Usual MIPS notation: $0 . $31 I “Special purpose” registers: EDATA, ESR, . I The program counter (PC) D. Kroening: Computer Architecture (TT 2011) 7 Basic Instructions (by Example) I Memory I LW: loads a data word from the RAM into a register I SW: stores a data word from a register into the RAM I ALU/FPU I ADD: adds the values of two registers, stores in third I SUB: same with subtraction I Control I J: jump to given address (absolute value) I BNEZ: branches to given address (relative offset) if a register is not zero D. Kroening: Computer Architecture (TT 2011) 8 MIPS Register Usage Conventions R# Name Purpose 0 zero Always equal to zero 1 at Assembler temporary 2–3 v0–v1 Return value from a function call 4–7 a0–a3 First four parameters for a function call 8–15 t0–t7 Temporary variables; need not be preserved 16–23 s0–s7 Function variables; must be preserved 24–25 t8–t9 Two more temporary variables 26–27 k0–k1 Kernel use; may change unexpectedly 28 gp Global pointer (global variables) 29 sp Stack pointer 30 fp/s8 Stack frame pointer or subroutine variable 31 ra Return address of the last subroutine call D. Kroening: Computer Architecture (TT 2011) 9 Machine Code and Assembler I The program is given as machine code I In the case of the MIPS/DLX, these are sequences of 32-bit words I One word = one instruction I We usually show a textual representation, called assembly language I An assembler turns the assembly language into machine code D. Kroening: Computer Architecture (TT 2011) 10 Instruction Formats 6 5 5 16 I-type Opcode RS1 RD Immediate 5 56 5 5 6 R-type Opcode RS1 RS2 RD SA Function 6 26 J-type Opcode PC Offset D. Kroening: Computer Architecture (TT 2011) 11 I-Type Load/Store IR[31 : 26] Mnem. d Effect 100000 0x20 lb 1 RD=Sext(mem) 100001 0x21 lh 2 RD=Sext(mem) 100011 0x23 lw 4 RD=mem 100100 0x24 lbu 1 RD=024mem 100101 0x25 lhu 2 RD=016mem 101000 0x28 sb 1 mem=RD[7:0] 101001 0x29 sh 2 mem=RD[15:0] 101011 0x2b sw 4 mem=RD mem = M[RS1 + imm], with d bytes D. Kroening: Computer Architecture (TT 2011) 12 I-Type Test/Set IR[31 : 26] Mnem. d Effect 011000 0x18 clri RD=(false ? 1 : 0) 011001 0x19 sgri RD=(RS1 > imm ? 1 : 0) 011010 0x1a seqi RD=(RS1 = imm ? 1 : 0) 011011 0x1b sgei RD=(RS1 ≥ imm ? 1 : 0) 011100 0x1c slsi RD=(RS1 < imm ? 1 : 0) 011101 0x1d snei RD=(RS1 6= imm ? 1 : 0) 011110 0x1e slei RD=(RS1 ≤ imm ? 1 : 0) 011111 0x1f seti RD=( true ? 1 : 0) D. Kroening: Computer Architecture (TT 2011) 13 I-Type Control Operations IR[31 : 26] Mnem. d Effect 000100 0x04 beqz PC=PC+4+(RS1 = 0 ? imm : 0) 000101 0x05 bnez PC=PC+4+(RS1 6= 0 ? imm : 0) 000110 0x16 jr PC=RS1 000111 0x17 jalr R31=PC+4; PC=RS1 D. Kroening: Computer Architecture (TT 2011) 14 R-Type Shifts IR[31 : 26] IR[5 : 0] Mnem. Effect Shift Operation 000000 0x00 000000 0x00 slli RD=RS1<<SA 000000 0x00 000001 0x01 slai RD=RS1<<SA (arith.) 000000 0x00 000010 0x02 srli RD=RS1>>SA 000000 0x00 000011 0x03 srai RD=RS1>>SA (arith.) 000000 0x00 000100 0x04 sll RD=RS1<<RS2[4:0] 000000 0x00 000101 0x05 sla RD=RS1<<RS2[4:0] (ar.) 000000 0x00 000110 0x06 srl RD=RS1>>RS2[4:0] 000000 0x00 000111 0x07 sra RD=RS1>>RS2[4:0] (ar.) D. Kroening: Computer Architecture (TT 2011) 15 R-Type ALU Operations IR[31 : 26] IR[5 : 0] Mnem. Effect 000000 0x00 100000 0x20 add RD=RS1+RS2 000000 0x00 100001 0x21 addu RD=RS1+RS2 (no overfl.) 000000 0x00 100010 0x22 sub RD=RS1-RS2 000000 0x00 100011 0x23 subu RD=RS1-RS2 (no overfl.) 000000 0x00 100100 0x24 and RD=RS1 ^ RS2 000000 0x00 100101 0x25 or RD=RS1 _ RS2 000000 0x00 100110 0x26 xor RD=RS1 ⊕ RS2 000000 0x00 100111 0x27 lhg RD=RS2[15:0] 016 D. Kroening: Computer Architecture (TT 2011) 16 R-Type Test/Set IR[31 : 26] IR[5 : 0] Mnem. Effect 000000 0x00 101000 0x28 clr RD=( false ? 1 : 0) 000000 0x00 101001 0x29 sgr RD=(RS1 > RS2 ? 1 : 0) 000000 0x00 101010 0x2a seq RD=(RS1 = RS2 ? 1 : 0) 000000 0x00 101011 0x2b sge RD=(RS1 ≥ RS2 ? 1 : 0) 000000 0x00 101100 0x2c sls RD=(RS1 < RS2 ? 1 : 0) 000000 0x00 101101 0x2d sne RD=(RS1 6= RS2 ? 1 : 0) 000000 0x00 101110 0x2e sle RD=(RS1 ≤ RS2 ? 1 : 0) 000000 0x00 101111 0x2f set RD=( true ? 1 : 0) D. Kroening: Computer Architecture (TT 2011) 17 J-Type Jumps IR[31 : 26] Mnem. Effect 000010 0x02 j PC = PC + 4 + imm 000011 0x03 jal R31 = PC + 4; PC = PC + 4 + imm 111110 0x3e trap trap = 1; EDATA = imm; 111111 0x3f rfe SR = ESR; PC’ = EPC; DPC = EDPC D. Kroening: Computer Architecture (TT 2011) 18 Assembler Example (1) Assembler Program Machine Code L1: LW 1, 0(SUM) 00: 8c 01 00 0b LW 2, 0(INC) 01: 8c 02 00 0a ADD 3, 1, 2 02: 00 22 18 20 SW 0(SUM), 3 03: ac 30 00 0b BNEZ 3, L1 04: 14 60 ff fb LW 1, 0(INC) 05: 8c 01 00 0a L2: BNEZ 1, L2 06: 14 20 ff ff INC: WORD 1 10: 00 00 00 01 SUM: WORD 0 11: 00 00 00 00 D. Kroening: Computer Architecture (TT 2011) 19 Assembler Example (2) 8c 01 00 0b = 1000 1100 0000 0001 0000 0000 0000 1011 opcode RS 1 RD immediate 100011 00000 00001 0000 0000 0000 1011 | {z } | {z } 0x23 11 = SUM LW 1, 0(SUM) D. Kroening: Computer Architecture (TT 2011) 20 ISA in C++ (1st Part) #define opcode(I) ((I&0xfc000000)>>26) #define RS1(I) ((I&0x03e00000)>>21) #define RD I(I) ((I&0x001f0000)>>16) #define immediate(I) ((I&0xffff ) j (( I&0x8000)?0xffff0000 :0)) #define RS2(I) ((I&0x001f0000)>>16) #define RD R(I) ((I&0x0000f800)>>11) #define SA(I) ((I&0x00000780)>>6) #define function(I) (I&0x0000003f) D. Kroening: Computer Architecture (TT 2011) 21 ISA in C++ (2nd Part) class c p u d l x t f public : // constructor: zero−initialise everything c p u dlxt ():PC(0) f for ( unsigned i =0; i <100; i++) MEM[ i ]=0; for ( unsigned j =0; j <32; j++) R[j]=0; g unsigned PC; // the program counter unsigned MEM[ 1 0 0 ] ; / / the main memory unsigned R[ 3 2 ] ; // the registers void show ( ) ; // show the state void step ( ) ; // perform one step void run ( ) ; // execute the program g ; D. Kroening: Computer Architecture (TT 2011) 22 ISA in C++ (3rd Part) void c p u dlxt ::step() f / / f e t c h unsigned I =MEM[PC ] ; unsigned op=opcode( I ); PC=PC+1; switch ( op ) f case LW: / / load word R[ RD I( I )]=MEM[R[RS1( I )]+immediate( I )]; break ; case SW: // store word MEM[R[ RD I(I )]+immediate(I )]=R[RS1(I )]; break ; D. Kroening: Computer Architecture (TT 2011) 23 ISA in C++ (4th Part) case 0: / / add / sub i f (function( I)==fADD) R[ RD R(I )]=R[RS1(I )]+R[RS2(I )]; else i f (function( I)==fSUB) R[ RD R( I )]=R[RS1( I)] −R[RS2( I ) ] ; break ; case BNEZ: // branch not equal to zero i f (R[RS1( I )]!=0) PC=PC+immediate( I ); break ; D. Kroening: Computer Architecture (TT 2011) 24 ISA in C++: Example Output PC = 4 R: 0 14 1 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM: 8c01000b 8c02000a 221820 ac60000b 1460fffb 8c01000a 1420ffff 0 0 0 1 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D.
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