Abstract Implementation of Low-Bit Rate Audio Codec

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ABSTRACT

IMPLEMENTATION OF LOW-BIT RATE AUDIO CODEC, CODEC2, IN VERILOG ON MODERN FPGAS

by Santhiya Sampath Kumar

Audio compression codecs are an important application in the Internet of Things (IoT) where small sensing devices will gather voice signals, but then need to transmit the information to aggregating servers at low cost. In this work, we implement and evaluate a hardware implementation of the Codec2, a lossy speech compression codec in Verilog and map it to an Intel CycloneIV FPGA. We describe the details of our implementation approach, including how we converted the C code of Codec2, how we represent data inside the hardware implementation and the associated cost of this implementation on a real FPGA. We then analyze our implementation compared to a microprocessor implementation to observe what performance we get on an FPGA versus a microprocessor. Our hardware implementation of Codec2 is qualitatively the same in terms of hearing the spoken transmission and has an error rate of 6.55 bits per frame (48 bits) and is 1.73 times faster than the microprocessor implementation.

IMPLEMENTATION OF LOW-BIT RATE AUDIO CODEC, CODEC2, IN VERILOG ON MODERN FPGAS

A Thesis

Submitted to the

Faculty of Miami University

in partial fulfillment of

the requirements for the degree of

Master of Science

Santhiya Sampath Kumar

Miami University

Oxford, Ohio

2020

Advisor: Dr. Peter Jamieson

Reader: Dr. Chi-Hao Cheng

Reader: Dr. Sahin Gokhan

IMPLEMENTATION OF LOW-BIT RATE AUDIO CODEC, CODEC2, IN VERILOG ON MODERN FPGAS

Santhiya Sampath Kumar

has been approved for publication by

The College of Engineering and Computing

and

Department of Electrical and Computer Engineering

______Dr. Peter Jamieson

______Dr. Chi-Hao Cheng

______Dr. Sahin Gokhan Table of Contents

List of Tables v

List of Figures vi

Acknowledgements vii

1 Chapter 1 : Introduction 1

2 Chapter 2 : Background 3 2.1 Audio Compression ...... 3 2.2 Codec2 ...... 3 2.3 Hardware Implementations of Lossy Audio Compression Codec ...... 5

3 Chapter 3 : Implementation Details 7 3.1 Number Representation ...... 7 3.2 C code to FSM ...... 8 3.3 External and Internal IP Cores for Base Operations ...... 9 3.4 Memory model implementation of the C code in Verilog...... 10 3.5 Codec2 Modules ...... 12

4 Chapter 4 : Results 16 4.1 FPGA Utilization ...... 16 4.2 Quality of Implementation ...... 17 4.3 Performance Results ...... 20

5 Chapter 5 : Discussion on Converting Other Codec2 Configurations 23

6 Chapter 6 : Conclusion 24

References 25

A Finite State Machines of the Top Verilog Modules 27 A.1 codec2 encoder mode2400.v ...... 27 A.2 codec2 encoder one frame mode2400.v ...... 28 A.3 analyse one frame.v ...... 30 A.4 speech to uq lsps.v ...... 31 A.5 encode lsp scalar.v ...... 33 A.6 encode WoE.v...... 34

B Verilog Implementation 35 B.1 codec2 encoder mode2400.v ...... 35 B.2 CODEC2 encoder one frame mode2400.v ...... 77

iii B.3 analyse one frame.v...... 116 B.4 speech to uq lsps.v ...... 172 B.5 encode lsp scalar.v ...... 200 B.6 encode WoE.v...... 212

iv List of Tables 2.1 Allocation of bits per FRAME ...... 6

3.1 Cyclone IV EP4CE115F29C7 resource utilization of 32-bit multipliers ...... 7 3.2 Encoder blocks and states...... 9 3.3 List of IP cores for Base Operations in our 32-bit representation used in the implementation...... 9 3.4 Verilog modules implemented for Codec2 Encoder ...... 12 3.5 Resource utilization of the encoder blocks ...... 14

4.1 Cyclone IV EP4CE115F29C7 resource utilization of Codec2 encoder to process one FRAME ...... 17 4.2 Cyclone IV EP4CE115F29C7 resource utilization of Codec2 encoder to process 150 FRAMES ...... 17 4.3 Cyclone IV EP4CGX150DF31I7AD resource utilization of Codec2 encoder to process one FRAME ...... 17 4.4 Cyclone IV EP4CGX150DF31I7AD resource utilization of Codec2 encoder to process 150 FRAMES...... 18 4.5 Timing Analysis of FPGA C2 Vs RaspberryPi’s ARM processor ...... 21

v List of Figures 2.1 Digital Voice Radio System ...... 4 2.2 Codec2 Encoder Block Diagram ...... 5

3.1 32-bit Fixed-point representation ...... 7 3.2 FSM model of the Codec2 encoder for one FRAME (20 ms) ...... 8 3.3 FSM model with parallel states ...... 10 3.4 An example of RAM implementation ...... 11 3.5 C to FSM conversion ...... 13 3.6 Codec2 Verilog module names overlaid in the block diagram ...... 15

4.1 Codec2 output of the hts1a.raw processed in C ...... 18 4.2 Codec2 output of the hts1a.raw processed in Verilog ...... 19 4.3 Codec2 output of the hts2a.raw processed in C ...... 19 4.4 Codec2 output of the hts2a.raw processed in Verilog ...... 20

A.1 FSM of codec2 encoder mode2400.v...... 27 A.2 FSM of codec2 encoder one frame mode2400.v ...... 28 A.3 FSM of CODEC2 encoder one frame mode2400.v (continued)...... 29 A.4 FSM of analyse one frame.v ...... 30 A.5 FSM of speech to uq lsps.v ...... 31 A.6 FSM of speech to uq lsps.v (continued) ...... 32 A.7 FSM of encode lsp scalar.v ...... 33 A.8 FSM of encode WoE.v ...... 34

Acknowledgements

This thesis is a major milestone in my journey of research and therefore, I am feeling very happy to thank all who have supported me for reaching it. In the first place, I would like to express my heartfelt gratitude to my thesis advisor, Dr. Peter Jamieson for his supervision, advice, guidance from the very early stage of this research and for providing me with an excellent atmosphere for doing the research. His continuous encouragement and support in various ways inspired me and enriched my growth as a research student. It is his guidance and timely help that took me towards the completion of this thesis. His guidance and support not only aided me in completing the thesis but also inspired me to explore my career in the semiconductor industry. It is indeed a great pleasure to work under the guidance of Dr. Peter Jamieson.

I am very thankful to the thesis committee members Dr. Chi-Hao Cheng and Dr. Gokhan Sahin for their constructive criticism and feedback that helped to improve my thesis. I am very grateful to the School of Electrical and Computer Engineering, Miami University for providing me with a conducive and comfortable environment to study and conduct my research. My time at Miami was made enjoyable in large part due to my fellow graduate students and friends in the Electrical and Computer Engineering Department, Miami University who have now become a part of my life.

I would like to express my profound gratitude to my beloved mother Amudha and my lovely sister Adhithya for their unwavering faith in me and their support in my decision to pursue the Masters program.

A special thanks to my friends Rajasekar, Nahlah, Nithin, Dhivya and Ankitha for always being there for me in just a ping away and for being a major source of support in helping me through challenging times and to shape my research in a better way.

I would like to convey my warmest thanks to a very special person, my best half, Boopathy for his continuous support, love and understanding during my pursuit of the Masters program and without whom the completion of this thesis would not have been possible.

Lastly, I would like to thank the Almighty for giving me wonderful parents, partner, teachers and friends. They all made my life very pleasant and enjoyable.

vii Chapter 1 : Introduction

Human speech is a common signal that is transmitted in a variety of applications in radio commu- nications. Depending on the compression of the speech signal, there are trade-offs for quality of speech versus the associated communication signal size. For example, signal size can be quanti- fied in terms such as bits per sample and sampling rate in a digital communication sense. Larger signals require higher capacity communication links, more time for transmission, more power consumption to transmit the signal, and more memory capacity at both the transmission and receiving nodes. Compressing a signal reduces many of these factors but comes with a computational cost to perform the signal processing, and in this work, we will focus on Digital Signal Processing (DSP). For a number of applications, such as Internet of Things (IoT), one potential goal is to transmit information contained in speech with minimal power and computation resources at the expense of a low-quality speech signal [1]. A number of audio compression codecs (COder and DECoder) have been created for this purpose, and the focus of this work is on Codec2 [2]. Codec2 is an open-source and patent-free audio codec that operates at a compressed lowest bit rate at the publication date of this work. The current implementation is in C and can be run on microprocessors. The key benefit of this core is that it has been developed without any existing commercial ties, and researchers and developers can use this codec for any application without restriction. This thesis implements a Register Transfer Level (RTL) version of Codec2 on a Field Pro- grammable Gate Array (FPGA) using Verilog HDL. The questions for this exercise are to see what trade-offs in terms of computation speed and quality a hardware implementation of the Codec2 encoder on FPGA results in compared to a software implementation running on a microprocessor. We hypothesize that a hardware implementation can be faster than a software implementation on a microprocessor due to custom parallel implementation capabilities possible on FPGA. Also, the creation of this hardware core will allow future chip designers to test and implement Codec2 on other FPGAs and even ASIC versions of this core (if the market demand ever is high enough to jus- tify the high cost of manufacturing ASICs). To verify our hypothesis, we implemented and tested a Codec2 encoder in Verilog and mapped it to Terasic’s DE2-115 [3] prototyping board with an Intel Cyclone IV FPGA [4]. We observe and report the speed and area consumption of this implementation and compare it to the Codec2 running on a RaspberryPi, including its ARM processor. From this experiment, we are not conclusively determining that the hardware core is faster than a software implementation, but provide insight for future designers on the capabilities and costs of a hardware implementation of the Codec2. Through various experiments, we perform a detailed analysis of the hardware implementation of Codec2 in terms of quality and speed. We quantitatively measure the hardware utilization of the proposed implementation in the FPGA hardware. We report the average bit error rate per frame, and we see whether the decoded files of the male and female speech samples from the hardware Codec2 are intelligible as compared to the same samples running on the software version of the Codec2. We also do a time profile analysis between the two implementations with respect to both time and clock cycles. From the experimental results, it can be seen that our FPGA implementation

1 of the encoder gives a qualitative result of speech as compared to the original speech sample. In terms of speed, the FPGA consumes more time to process the input samples as compared to the software version running on RaspberryPi. We analyzed the timing results to convey what are the modules to be modiﬁed in the future for better processing time. Our approach is to map the Codec2 design to Verilog HDL and target any FPGA or ASIC implementation. Alternatively, we might choose to use a High-level synthesis (HLS) tool, such as Legup [5] or those provided by Intel and Xilinx, with their associated tools and chip structure. This HLS approach is viable, but those tools tend to be tightly coupled with the FPGAs that those com- panies target. Instead, by creating a low-level Verilog implementation, our core is more portable and open along similar lines to the main thrust of the Codec2 principles. The remainder of this thesis is organized as follows: Chapter2 provides background information on the audio compression techniques, Codec2, and the previous work on the hardware implementation of Audio Codecs. Chapter3 describes the details of our hardware implementation of the Codec2 encoder in Verilog, targeting an FPGA. Chapter4 discusses the experiments, results, and analysis of the performance of this work. Chapter5 discusses possible improvements and future work. Chapter6 presents the conclusion of this thesis. Finally, the Appendix contains the Finite State Machine (FSM) diagrams and the Verilog code of the modules.

2 Chapter 2 : Background

In this chapter, we present background information on audio compression, details of Codec2, and describe existing hardware implementations of hardware Codecs.

2.1 Audio Compression

Audio compression techniques attempt to shrink the signal size via lossy or lossless compression techniques. Lossless compression techniques ﬁnd redundant data in the encoding of the signal at the transmission side and are completely recoverable at the receiver side. A well-known algorithm in this domain that can be applied to digital data is the Lempel-Ziv algorithm [6]. Lossy compression, on the other hand, attempts to remove data that is less useful, and thus makes the signal less like the original signal, but the signal contains most of the relevant information. For example, an original speech signal includes characteristics that would allow a listener to identify who the speaker is based on the acoustics, but lossy compression can remove these qualities to only transmit the information, also known as the words spoken. A well-known algorithm for lossy compression is MP3 encoding for music [7]. The areas of audio compression and data compression are vast areas of research and development and cannot be captured in this work. We suggest that unfamiliar readers start with Kavitha’s recent survey on lossy and lossless compression techniques [8] and Uthayakumar et. al. survey on data compression techniques [9].

2.2 Codec2

Our focus in this work is on lossy compression for speech. In particular, we focus on the Codec2 [2] implementation. Codec2 is a patent-free and open-source speech codec software developed by Dr. David Rowe, who has implemented a number of low bit rate speech compression and High-Frequency (HF) modems, with a focus on combining these technologies for digital voice over radio applications [2]. Codec2 is designed for lossy speech compression and operates at different rates, including 3200, 2400, 1600, 1400, 1300, 1200, 700, and 450 bit/s. There exist several competing codecs in this domain, such as MELP (a licensed codec) [10] and Speex (another open-source codec) [11] that operate in the range of 5000 bits/s. Figure 2.1 shows the Digital Voice Radio System [2], which is an HF modem, and Codec2 was originally designed to be incorporated in this application. Digital voice radio system uses a microphone to capture the input speech, which is then fed into Analog to Digital converter (ADC), and the ADC converts the inputs and converts the analog speech into 8000 samples per second. The Codec2 encoder compresses the input samples from 8000 samples/s to a compressed form (for example, 2400 bits/s depending on the mode of the Codec2 software chosen). A Forward Error Correction (FEC) encoder takes 2400 bits/s from the Codec2 encoder, and after modulation,

3 Figure 2.1: Digital Voice Radio System

the data is transmitted over the radio channel. The decoding reverses the procedure and generates an analog audio signal that can be heard over a speaker.

Codec2 Encoder Our work focuses on developing the hardware implementation of the Codec2 encoder. We choose one compression mode to implement in hardware, which is 2400 bits/s (called MODE2400 from now on in this thesis), and other modes could be implemented from our example hardware codec, but the process of conversion is not trivial (in Chapter5 we provide discussion on how this conversion might be done). Similarly, Dr. Rowe’s new implementations of Codec2 modes at lower bit rates take time to design as new techniques and algorithms are implemented in the software. Speech data are processed in terms of FRAMEs, and the time interval of each FRAME is 20ms with 160 samples in 16-bit signed short data format. In MODE2400, the Codec2 encoder encodes a FRAME to 48 bits. Codec2 is implemented with a number of DSP algorithms such as sinusoidal coding, pitch estimation, Linear Predictive Coding (LPC), and so on. The Codec2 encoder uses extracted speech parameters to compress the speech data. The computational process of encoding a single speech FRAME is shown in Figure 2.2, and Table 2.1 shows the output parameters of each of the system components in column 1, the encoder block that produces that output in column 2, and the total number of output bits where the sum of these is 48.

4 Figure 2.2: Codec2 Encoder Block Diagram

2.3 Hardware Implementations of Lossy Audio Compression Codec

Lossy compression codecs can be implemented on a number of computational system substrates. Examples include an MP3 codec on a microprocessor [12], an MP3 codec on a DSP processor [13], and image compression on a GPU [14]. Our focus is on FPGA implementations, and we brieﬂy survey existing implementations in the research literature. The work on MELP encoder which operates at 2400 bits/s, has been implemented using Vivado HLS on a Zync-7 FPGA [15]. The algorithm is coded in C and is converted to Verilog by the HLS tool. This work then compares the area utilization and latency of the C-synthesis with the post- synthesis of the design to the Verilog RTL model. This work shows that the Verilog model utilizes fewer resources when compared to a C-Synthesis model. The Advanced Multi-Band Excitation (AMBE) work is a Codec module that uses Quartus II to synthesize a VHDL design targeting a Cyclone II FPGA [16]. This work demonstrates that an FPGA can replace the DSPs or microcontrollers in traditional voice communication systems.

5 Table 2.1: Allocation of bits per FRAME

Output Parameter Block Bits/FRAME Harmonic Magnitudes LSP Quantization 36 (LSPs) Wo and Joint Energy and Wo 8 Energy Quantization Pitch Quantization and Voicing 2 MBE voicing test Spare 2 Total 48

Here, the FPGA acts as a codec and AMBE chip controller. It also acts as interface support for the Subscriber Line Interface Card (SLIC) and handles the Dual Tone Multi-Frequency (DTMF) decoding. They demonstrated that an FPGA could be used to implement a complete speech system on a single chip. The work on ‘An Efﬁcient Hardware Architecture of Codec2’ implemented Codec2 decoder to process 1200 bits/s using Verilog and synthesized on Xilinx’s Artix-7 XC7A100T FPGA [17]. This implementation followed ‘Very Long Instruction Word(VLIW)’ architecture to enhance the parallelism and pipelining of the DSP algorithms. For FFT and IFFT blocks, to reduce the computation time of 512-point FFT for every frame, the butterﬂy operation was executed using a pipeline scheme. This work showed that this decoder implementation reduced the processing time up to 20 times when compared to the Cortex-M4 CPU.

6 Chapter 3 : Implementation Details

The open-source Codec2 is written in the C language[18] and can be executed on a Linux system with a microprocessor such as the RaspberryPi. In order to synthesize this design to an FPGA, all the variables, constants, and functions in the code-base should be implemented in fixed-point representation as opposed to floating-point to achieve results with a reasonable number of resources. For example, multiplication and division in floating-point representation involve operations that consume considerable amounts of the logic resources available on the FPGA. Table 3.1 shows the comparison of the resource utilization of the 32-bit fixed-point and floating-point multipliers when synthesized on Cyclone IV FPGA. The Fixed-point multiplier is from “Opencores” Fixed point Math Library [19], and the floating-point multiplier is generated with the help of Quartus “IP Catalog” tool.

Table 3.1: Cyclone IV EP4CE115F29C7 resource utilization of 32-bit multipliers

32 -bit Multiplier Logic Elements Registers Memory bits 9-bit Multipliers Floating-point 318 281 173 7 Fixed-point 57 0 0 8

In this chapter, we will describe our internal number representation, how we convert C code to a Finite State Machine (FSM) implementation, which IP modules we have used from elsewhere, and how we use memory blocks to implement C arrays.

3.1 Number Representation

One of the first challenges is to write all the basic C operators such as division, square root, log, etc. in fixed-point representation, and then implement all the existing variables and functions from C to Verilog using this fixed-point representation. We chose to use a 32-bit fixed-point representation for our base representation in the system, which includes the input samples, constants, and other variables.

Figure 3.1: 32-bit Fixed-point representation

Our ﬁxed-point representation uses a customized 32-bit data representation that contains 16 bits for the exponent part (most signiﬁcant bit for sign representation) and 16 bits in the mantissa,

7 as shown in Figure 3.1. For certain operations, an 80-bit ﬁxed-point representation is used to square values and for all variables where the decimal values exceed 15 bits in the exponent portion of the number. The 80-bit data representation contains 64 bits for the exponent and 16 bits for the mantissa. Whenever there is a demand for accuracy in the fractional part for some variables in the Verilog modules, the length of the exponent and mantissa are modiﬁed while retaining the length of 32-bit and 80-bit data representation throughout the design.

Figure 3.2: FSM model of the Codec2 encoder for one FRAME (20 ms)

3.2 C code to FSM

The next step in converting the C codebase into Verilog is to implement the exact sequential computation in Verilog using Finite State Machines (FSM). The FSM model of the Codec2 encoder for one FRAME is given in Figure 3.2, and this ﬁgure shows the sequential implementation of the C code, where Table 3.2 columns 2 and 1 show how each state corresponds to a block in Figure 2.2, respectively. The purely sequential state machine can be converted into two parallel state machines P1 and P2 as shown in Figure 3.3 where Table 3.2 columns 2 and 1 shows how each state corresponds to a block in Figure 2.2, respectively. First, the two parallel FSMs, P1 and P2 start at

8 Table 3.2: Encoder blocks and states

Encoder block States Fourier Transform(FT), Pitch Estimation, START AOF1, RUN AOF1, Pitch Quantization and START AOF2, RUN AOF2 MBE voicing test LPC Analysis, START SPEECH, LPC to LSP RUN SPEECH START ELSP, LSP Quantization RUN ELSP Wo and START WOE, Energy Quantization RUN WOE

the same time. And the other two parallel FSMs, P2 1 and P2 2 are executed after the completion of the P2. Finally, the encoded bits are combined from FSMs, P1, P2 1 and P2 2.

3.3 External and Internal IP Cores for Base Operations

We need to use a basic set of mathematical operations in the Verilog design, and for this reason, we use existing IP and create our own IP for base operations as described below. For our ﬁxed-point operations of addition and multiplication, we use cores from “Opencores“ Fixed point Math Library [19]. The division and square root operations are written by converting the Newton-Raphson algorithm [20] into an FSM implementation. The logarithmic and trigonometric operations such as cos, acos are written using a CORDIC algorithm [21] and converts those algorithms into Verilog FSM implementations.

Table 3.3: List of IP cores for Base Operations in our 32-bit representation used in the implementation.

Source IP Cores Operation qadd Addition Opencores qmult Multiplication fp div clk Division fpgreaterthan inequality check fp log10 log10 Custom-built acosf arc cosine cossin cordic sine and cosine fpmod modulo fpsqrt square root

The full list of IP cores used by the encoder modules is given in Table 3.3. In this table, column

9 Figure 3.3: FSM model with parallel states

1 shows the source of the core, column 2 shows the name of the Verilog module in the design, and column 3 shows the operation that can be performed by the core.

3.4 Memory model implementation of the C code in Verilog

Arrays in C are implemented as on-chip Random Access Memory (RAM) or Read Only Memory (ROM) based on input usage. The Verilog modules for the memories are created with the help of the “IP Catalog” available in Quartus (Intel's synthesis tool for FPGAs). Figure 3.4 shows how an RAM module is used across module boundaries which is equivalent to passing arrays as a parameter in a C function.

10 chch Figure 3.4: An example of RAM implementation

From this ﬁgure, the following connections are made. The module codec2 encoder one frame has module instantiations of RAM Sn and speech to uq lsps modules. The data from the RAM Sn is read or written from the speech to uq lsps. So, the input and output parameters of the speech to u -q lsps are connected to the RAM Sn as follows. The address (addr sn), read enable (re), write enable (we), write data (in sn) signals are conﬁgured as output parameters in the speech to uq lsps module. The read data (out sn) from RAM Sn is an input parameter to the speech to uq lsps. There is more than one module inside the codec2 encoder one frame which utilizes the data from RAM Sn, and only one instance of RAM Sn is created.

11 3.5 Codec2 Modules

Table 3.4: Verilog modules implemented for Codec2 Encoder

Modules in Verilog Encoder Blocks fft FT nlp fft nlp Pitch estimation post process sub multiples two stage pitch refinement Pitch refinement hs pitch refinement estimate amplitudes MBE Voicing Test estimate voicing mbe speech to uq lsps LPC Analysis levinson durbin lpc to lsp LPC to LSP encode lsps scalar LSP Quantization quantise encode WoE Wo and Energy compute weights Quantization find nearest weighted

We convert a “C” block to a Verilog implementation with the following steps: 1. Input and output variables are converted to the input and output signals and parameters in a Verilog module. This can include traditional signals that include data, or in the case of larger pieces of data, we use memories to buffer the data.

2. The arithmetic, trigonometric and other math ﬂoating-point operations in C are implemented by the ﬁxed-point IP cores as described above.

3. An FSM is designed that implements the C code based on the sequential steps in function(s). Figure 3.5 shows how a basic “for” loop in C has been converted to an FSM in Verilog for reference. Once we’ve implemented a sequential version of the module, we then consider if it can be parallelized and how to achieve that parallelization with traditional optimizations such as loop unrolling, parallel operation execution, etc. The modules written for the different blocks of the Codec2 encoder are shown in Table 3.4 where column 1 has the Verilog module name, and the second column lists the implementation of the Codec2 blocks in Figure 2.2. Figure 3.6 shows the modules and sub-modules implemented in Verilog for the Codec2 encoder blocks. Table 3.5 shows each of the Verilog modules and the sub-modules in Table 3.4 and their resource usage on the Cyclone IV EP4CE115F29C7 FPGA. Column 1 lists each of the encoder

12 Figure 3.5: C to FSM conversion blocks, column 2 has the modules and sub-modules implemented in Verilog, column 3, 4, and 5 shows the respective utilization for the module in terms of Logic Elements, Memory bits, and 9-bit multiplier blocks. The FSMs and Verilog code of the top modules are listed in Appendix A and B respectively.

13 Table 3.5: Resource utilization of the encoder blocks

Encoder Blocks Modules & Sub-modules Logic Elements Memory bits Multipliers FT fft 1,053 40,960 16 nlp 8,995 277,504 174 Pitch estimation fft nlp 2,379 90,112 40 post process sub multiples 1,591 0 28 two stage pitch refinement 5,182 0 40 Pitch Refinement hs pitch refinement 1,642 0 8 estimate amplitudes 2,277 0 16 MBE Voicing test estimate voicing mbe 3,933 16,384 40 speech to uq lsps 18,287 15,712 138 LPC Analysis levinson durbin 7,594 0 60 LPC to LSP lpc to lsp 6,643 0 48 encode lsp scalar 3,091 0 80 LSP Quantization quantise 2,187 0 0 encode WoE 6,123 0 76 W0 and compute weights 963 0 16 Energy Quantization find nearest weighted 2,053 0 32

14 Figure 3.6: Codec2 Verilog module names overlaid in the block diagram

15 Chapter 4 : Results

For our experiments, we evaluate our FPGA implementation of Codec2 encoder (called FPGA C2 from now on in this section) with that of the software implementation of Codec2 running on Rasp- berry Pi. The FPGA is a small FPGA available from Intel that is part of the DE2-115 prototyping board from Terasic [3]. The FPGA is a Cyclone IV EP4CE115F29C7 FPGA, and we use Intel’s Quartus tool (Quartus Prime 16.1.0) to synthesize and program the FPGA. Our testing framework uses a combination of simulation and a tool called signal-tap, which is an on-board logic analysis tool [22]. The DE2-115 has a 50MHz clock, and our results are reported at this clock rate. When synthesizing our design for analysis, we use the following optimization parameters in the Quartus tool.

• “Optimization Technique“ for area or speed is chosen as “Balanced”

• “Optimize Timing” is chosen as “Normal”

All other settings are in their default setting. We compare our FPGA implementation to a RaspberryPi 2 that includes the quad-core ARM Cortex-A7 CPU and runs the Raspbian Linux distribution. This processor has a 900 MHz clock frequency. Speciﬁcally, through our experiments, we intend to address the following research questions.

1. What is the hardware utilization of our proposed implementation FPGA C2.

2. How does FPGA C2 perform against software implementation of Codec2 in Raspberry Pi in terms of quality.

3. How fast are the major modules of FPGA C2 compared against the Raspberry Pi implementation in terms of time.

4. How do the major modules of FPGA C2 compare against Raspberry Pi implementation in terms of clock cycles.

4.1 FPGA Utilization

The resource utilization of the FPGA for our Codec2 encoder processing one FRAME and for processing 150 FRAMEs (which is 3 seconds of input speech) are shown in Table 4.1 and 4.2 respectively. In these tables, column 1 lists the FPGA resource type, column 2 shows the total available resource count on the Cyclone IV EP4CE115F29C7, column 3 shows the number of those resources used in our synthesized design, and column 4 gives a utilization percentage of that resource (divide column 3 by column 2). In the previous chapter, we provided resource utilization details for each of the design components. Note that these utilization numbers can be improved by analyzing the design and determining which functional units can be shared. For example, a

16 multiplier unit can be shared by two modules if they are executed at different times. This process is part of the binding and scheduling done by High-Level Synthesis tools. Note, however, there may be a tradeoff in speed vs. area to share resources.

Table 4.1: Cyclone IV EP4CE115F29C7 resource utilization of Codec2 encoder to process one FRAME

Available Used Utilization Logic Elements 114,480 59,894 52% Memory Bits 3,981,312 426,336 11% 9-bit embedded Multipliers 532 532 100%

Table 4.2: Cyclone IV EP4CE115F29C7 resource utilization of Codec2 encoder to process 150 FRAMES

Available Used Utilization Logic Elements 114,480 60,890 53% I/O Pins 529 424 80% Memory Bits 3,981,312 1,230,528 31% 9-bit embedded Multipliers 532 532 100%

To verify the compatibility of the FPGA C2 on other FPGAs, we compiled the design on EP4CGX150DF31I7AD FPGA from the Cyclone IV GX family. The resource utilization to process one FRAME and to process 150 FRAMEs are shown in Table 4.3 and 4.4 respectively.

Table 4.3: Cyclone IV EP4CGX150DF31I7AD resource utilization of Codec2 encoder to process one FRAME

Available Used Utilization Logic Elements 149,760 57,287 38% Memory Bits 6,635,520 426,336 6% 9-bit embedded Multipliers 720 596 83%

4.2 Quality of Implementation

The module codec2 encoder 2400 processes 900 bytes of the input data, which contains 150 frames and gives an encoded output of 7200 bits (2400 bits/s). The output bits from the Ver- ilog module are copied to a “.bit” file. This encoded file is then decoded using the software version of Codec2 decoder running on a Linux system to generate the “.raw” file. Finally, the decoded

17 Table 4.4: Cyclone IV EP4CGX150DF31I7AD resource utilization of Codec2 encoder to process 150 FRAMES

Available Used Utilization Logic Elements 149,760 58,301 39% I/O Pins 508 424 83% Memory Bits 6,635,520 1,230,528 19% 9-bit embedded Multipliers 720 596 100%

“.raw” file from codec2 encoder 2400 is compared with the decoded file of the same input data from codec2 software running on a Linux system. We took two samples for verifying the Codec2 written in Verilog. The samples are “hts1a.raw” and “hts2a.raw”, which are male and female voice samples that contain 3-seconds of speech (150 frames). When we listen to the decoded samples of the encoded bits from the Verilog module, they are intelligible as compared to the original samples. The source code and the speech files are uploaded in the GitHub repository [23].

Figure 4.1: Codec2 output of the hts1a.raw processed in C

Figures 4.1 and 4.3 show the Codec2 output of the speech samples “hts1a.raw” and “hts2a.raw” when processed on the software version. Figure 4.2 and 4.4 show the Codec2 output from the software Codec2 processing the encoded bits from Verilog implementation of the Codec2 encoder. We have stacked the software and hardware ﬁgures on top of each other so the reader can do an easy visual comparison of the waveforms. The design loses some accuracy in the 16-bit fractional part of the ﬁxed-point representations while performing repetitive multiplications and additions in the modules for Fourier Transform

18 Figure 4.2: Codec2 output of the hts1a.raw processed in Verilog

Figure 4.3: Codec2 output of the hts2a.raw processed in C

and auto-correlation. So, for each frame of encoded data, which is 48 bits, we can see that some bits are off from the expected encoded bits in each frame. The average number of bits that vary per frame is 6.55 bits/frame. The bit error rate for 3 seconds of input data (900 bytes) is 13.6%.

19 Figure 4.4: Codec2 output of the hts2a.raw processed in Verilog

4.3 Performance Results

For this analysis, we compare the software and hardware implementations in terms of speed. As mentioned, the clock frequency of the FPGA is 50 MHz, while the clock frequency of the ARM processor in RaspberryPi is 900 MHz. So, in terms of speed, the processor is 18 times faster than the FPGA we are using. In the Verilog implementation, the time taken to process 3s of input speech by Codec2 encoder is calculated by using clock tick counters to record the number of clock cycles for the execution of the codec2 encoder 2400 module. Then, given the FPGA's 50 MHz clock, the counter variable multiplied by 20 ns gives the time of execution for processing 3s input data. When we run the same encoder block to process the same input data of 3s in RaspberryPi 2, we use the system time to compute internal timing results [24]. These two measurements allow for this comparison. Table 4.5 provides a detailed analysis of the time to process all the modules and submodules of the encoder blocks in FPGA C2 vs. RaspberryPi. In this table, column 1 lists the top modules and the sub-modules used in the FPGA C2 design, columns 2 and 3 show the number of clock cycles taken by the Verilog modules in FPGA C2 and by the corresponding functions in the encoder blocks written in ‘C’ when processed using RaspberryPi. Columns 4 and 5 show the time taken in microseconds by the Verilog modules in FPGA C2 vs. the functions in ‘C’ when run on the RaspberryPi. Finally, column 6 shows the ratio of the processing time of FPGA vs. RaspberryPi. This ratio is calculated by column 4 divided by column 5, and the result divided by the timing factor 18 to report a ratio that when less than 1 shows the FPGA processing this computation faster than the RaspberryPi implementation. For additional clarity, we mark the ratios less than 1 with green so that we can see the modules that are better when implemented on the FPGA. From the timing analysis table 4.5, we see that the most of the Verilog modules (highlighted in

20 Table 4.5: Timing Analysis of FPGA C2 Vs RaspberryPi’s ARM processor

Time Clock Cycles Ratio (micro s) Encoder Modules FPGA Pi FPGA Pi FPGA/ Pi analyse one frame 4,66,090 361,749 9,321.80 401.94 1.2884 fft 56,628 187,155 1,132.95 207.95 0.3026 nlp 139,300 229,995 2,786.00 255.55 0.6057 fft nlp 56,628 127,080 1,132.56 141.20 0.4456 ppsr 665 3,690 13.3 4.10 0.1803 tspr 128,373 57,285 2,567.46 63.65 2.2410 hspr 101,073 24,885 2021.46 27.65 4.0616 estimate amplitudes 3,114 11,700 62.28 13.00 0.2662 estimate voicing mbe 2,162 14,625 43.24 16.25 0.1478 speech to uq lsps 65,099 123,858 1,301.98 137.62 0.5256 levinson durbin 1,502 5,310 30.04 5.90 0.2829 lpc to lsp 15,128 68,670 302.56 76.30 0.2203 encode lsp scalar 908 13,320 18.16 14.80 0.0682 quantise 17 2,394 0.46 2.66 0.0096 encode WoE 1,504 21,042 30.08 23.38 0.0715 compute weights 8 2,250 0.16 2.50 0.0036 ﬁnd nearest weighted 1,284 20,430 25.68 22.70 0.0628 analyse one frame*2 1,168,995 723,498 23,379.90 803.88 1.6158 codec2 encoder one frame 1,249,132 1,830,282 24,982.64 2033.65 0.6825 codec2 encoder mode2400 172,334,234 298,785,186 3,446,684.68 331,983.54 0.5768

green) which are implemented for the encoder blocks execute faster in FPGA C2 when compared to the corresponding functions in ‘C’ processed on the ARM processor. The modules Pitch Refinement encoder blocks, two stage pitch refinement (given as tspr in the table) and it's sub-module hs pitch refinemement (hspr) are nearly 2 and 4 times slower in FPGA C2. This is because both these modules utilize the fixed-point division IP core (fp div), which takes an average of 200 clock cycles and is used multiple times. So, in the future, we would aim to implement the division module for efficient run time, which makes the tspr and hspr modules to process faster. This is the reason that at the top-level, the Verilog module analyse one frame takes more time to process on an FPGA compared to the Arm processor. Since the modules for the other encoder blocks of LPC Analysis, LPC to LSP, LSP Quantiza- tion, Wo & energy Quantization execute faster in FPGA C2 when compared to the corresponding functions in ‘C’ processed on the ARM processor, we could see that the module codec2 encoder one frame which processes one FRAME of input, executes faster on the FPGA compared to the Arm processor. Conclusively, the time of execution to process 150 FRAMES on FPGA is, currently, 3.4466 seconds with the 50 MHZ clock while the time taken in RaspberryPi is 0.3319 seconds with a 900 MHz clock. When comparing the ratio of speed, FPGA C2 implementation is 1.73 times faster than the Codec2 encoder on RaspberryPi. If we have to speed up the FPGA C2 design further, we would need to pipeline our architecture so that we can more quickly process the computation. This

21 is doable since there is little dependence between frames that are processed.

22 Chapter 5 : Discussion on Converting Other Codec2 Conﬁgurations

Codec 2 operates on different compression rates of 3200, 2400, 1600, 1400, 1300, 1200, 700, and 450 bit/s. We chose to implement Codec2 encoder operating at 2400 bits/s because of the following reasons.

1. The other available open-source speech Codecs are MELP, AMBE, and LPC-10. They operate in the range of 2000 to 2400 bits/s. So, the MODE2400 of the FPGA C2 would be much suitable if we want to compare the hardware implementations of other Codecs.

2. The software implementation of MODE2400 has most of the functions which can be reused for the other modes lower than MODE2400. So, building the Verilog modules for MODE2400 allows having most modules that can be utilized while implementing the Codec2 encoder in other modes. The list of modules to be altered are discussed below.

As our work is based on the MODE2400, some modifications should be taken to convert to other modes in the Codec2. The Verilog modules for the encoder blocks such as FT, Pitch estimation, Pitch Quantization, MBE Voicing test, LPC analysis, and LPC to LSP can be reused when converting to other bit rates. Also, the IP cores from the “OpenCores“ and the custom-built cores can be reused without any modifications. All the custom-built IP Cores have parameters that can be altered to any other bit-width of the fixed-point representation. The significant changes will focus on a subset of modules, including LSP Quantization, Wo, and Energy Quantization blocks, which must be created according to the C implementations for each mode. In each of these cases, it took approximately 15 days to implement these cores, and we would expect similar design time to make new ones with a slight reduction given that our implementations could be used as templates.

23 Chapter 6 : Conclusion

In this work, we described the implementation and evaluation of the Codec2 lossy speech compression codec on an FPGA. We implemented this design in Verilog and mapped it to an Intel CycloneIV FPGA, which we then compared to the Codec2 C implementation running on a Rasp- berryPi. We implemented this project as an open source project, so that the future designers could test Codec2 on other FPGAs. We included the details of our implementation approach, such as how we convert the C code of the Codec2 to Verilog, how we represent data inside the hardware implementation, and the associated silicon area cost of this implementation on a real FPGA. We then compared this implementation to a microprocessor implementation to observe what performance benefits we could get on an FPGA versus a microprocessor. The performance of the hardware implementation is measured in terms of quality and speed. In terms of quality, the hardware implementation of Codec2 is qualitatively the same when we hear the final spoken result. The Codec2 encoder has an average error rate of 6.55 bits per frame. In terms of speed, the hardware implementation on FPGA is significantly faster than that of the software implementation on RaspberryPi. For the implementation of the Codec2 decoder, we can utilize the same IP cores for the basic fixed-point operations written for the encoder and proceed for the development of the decoder modules.

24 References

[1] Hossein Shafagh, Lukas Burkhalter, Anwar Hithnawi, and Simon Duquennoy. Towards blockchain-based auditable storage and sharing of iot data. In Proceedings of the 2017 on Cloud Computing Security Workshop, pages 45–50. ACM, 2017. [2] David Rowe. Codec 2. http://www.rowetel.com/?page_id=452. Accessed: 06-30-2019. [3] Altera de2-115 development board. https://www.intel.com/content/www/us/en/ programmable/solutions/partners/partner-profile/terasic-inc-/board/ altera-de2-115-development-and-education-board.html. Accessed: 07-07-2019. [4] Cyclone IV FPGA. https://www.intel.com/content/www/us/en/products/ programmable/fpga/cyclone-iv.html. Accessed: 07-07-2019. [5] Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason H Anderson, Stephen Brown, and Tomasz Czajkowski. Legup: high-level synthesis for fpga- based processor/accelerator systems. In Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays, pages 33–36. ACM, 2011. [6] Lempel–ziv algorithm. https://en.wikipedia.org/wiki/Lempel-Ziv-Welch. Ac- cessed: 07-07-2019. [7] MP3. https://en.wikipedia.org/wiki/MP3. Accessed: 07-07-2019. [8] P Kavitha. A survey on lossless and lossy data compression methods. International Journal of Computer Science & Engineering Technology, 7(03):110–114, 2016. [9] J Uthayakumar, T Vengattaraman, and P Dhavachelvan. A survey on data compression techniques: From the perspective of data quality, coding schemes, data type and applications. Journal of King Saud University-Computer and Information Sciences, 2018. [10] Melp codec. https://www.vocal.com/speech-coders/melp/. Accessed: 07-07-2019. [11] Speex : A free codec for free speech. https://www.speex.org/. Accessed: 07-07-2019. [12] Staffan Gadd and Thomas Lenart. A hardware accelerated mp3 decoder with bluetooth streaming capabilities. Master of science Thesis, 2001. [13] Sekyoung Hong, Byungcheol Park, Yoonseok Song, Hangyo See, Jonghyun Kim, Hyungjong Lee, Dalsoo Kim, and Minkyu Song. A full accuracy mpeg1 audio layer 3 (mp3) decoder with internal data converters. In Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No. 00CH37044), pages 563–566. IEEE, 2000. [14] Lucana Santos, Enrico Magli, Raffaele Vitulli, Jose´ F Lopez,´ and Roberto Sarmiento. Highly- parallel gpu architecture for lossy hyperspectral image compression. IEEE Journal of Se- lected Topics in Applied Earth Observations and Remote Sensing, 6(2):670–681, 2013.

25 [15] M Koushik, Shashidhar Shivanagi, Jawed Qumar, Jyoti Yadav, and D Saravanan. Implemen- tation of melp encoder on zynq fpga using hls. In 2017 International Conference on Current Trends in Computer, Electrical, Electronics and Communication (CTCEEC), pages 87–91. IEEE, 2017.

[16] Kapil Mahawar, Vishal Kumar, and HO Gupta. Design and implementation of ambe based voice codec module over custom fpga platform. In 2012 International Conference on Com- puting, Communication and Applications, pages 1–5. IEEE, 2012.

[17] Sumek Wisayataksin. An Efﬁcient Hardware Architecture of Codec2 Low Bit-rate Speech Decoder. In 2019 5th International Conference on Engineering, Applied Sciences and Tech- nology (ICEAST), pages 1–4. IEEE, 2019.

[18] Codec2 software. https://svn.code.sf.net/p/freetel/code/codec2/branches/. Accessed: 01-12-2019.

[19] Fixed-point Math Library. https://opencores.org/projects/verilog_fixed_point_ math_library. Accessed: 07-07-2019.

[20] Newton-Raphson Algorithm. https://en.wikipedia.org/wiki/Division_algorithm. Accessed: 07-07-2019.

[21] CORDIC Algorithm. https://people.sc.fsu.edu/~jburkardt/cpp_src/cordic/ cordic.html. Accessed: 07-07-2019.

[22] Signal Tap Logic Analyzer. https://www.intel.com/content/dam/www/ programmable/us/en/pdfs/literature/ug/signal.pdf. Accessed: 01-17-2019.

[23] Santhiya Sampath Kumar. Verilog Codec2. https://github.com/santhiyaskumar/ FPGA_Codec2Encoder, 2020.

[24] sys/time.h - Time types. http://manpages.ubuntu.com/manpages/trusty/man7/sys_ time.h.7posix.html. Accessed: 01-17-2019.

26 Finite State Machines of the Top Verilog Modules

A.1 codec2 encoder mode2400.v

Figure A.1: FSM of codec2 encoder mode2400.v

27 A.2 codec2 encoder one frame mode2400.v

Figure A.2: FSM of codec2 encoder one frame mode2400.v

28 Figure A.3: FSM of CODEC2 encoder one frame mode2400.v (continued)

29 A.3 analyse one frame.v

Figure A.4: FSM of analyse one frame.v

30 A.4 speech to uq lsps.v

Figure A.5: FSM of speech to uq lsps.v

31 Figure A.6: FSM of speech to uq lsps.v (continued)

32 A.5 encode lsp scalar.v

Figure A.7: FSM of encode lsp scalar.v

33 A.6 encode WoE.v

Figure A.8: FSM of encode WoE.v

34 Verilog Implementation

B.1 codec2 encoder mode2400.v

1 /* 2 * Module- codec2_encoder_2400 3 * Top module-N/A-- Final Module 4 * Project- CODEC2_ENCODE_2400 5 * Developer- SanthiyaS 6 * Date- Dec 10, 2019 7 * 8 * Description- To encode3s of speech to 7200 bits. 9 * Input(s)-3s of speech stored in RAMs. 10 * Output(s)- encoded_bits

12 * 32-bit or 80-bit fixed point representation 13 S-E-MS-E-M 14 1- 15- 161- 63- 16 15 */

18 module codec2_encoder_mode2400(start_codec2,clk,rst,

20 encoded_bits_0, 21 clk_count, 22 done_codec2);

25 //------26 //-- Input/Output Declarations-- 27 //------28 parameterN = 32; 29 parameterQ = 16; 30 parameterBITS_WIDTH = 48; 31 parameter N1 = 80; 32 parameter Q1 = 16;

34 input clk,rst,start_codec2;

36 output reg[BITS_WIDTH-1:0] encoded_bits_0; 37 reg[BITS_WIDTH-1:0] encoded_bits_1, 38 encoded_bits_2,encoded_bits_3,encoded_bits_4,encoded_bits_5, 39 encoded_bits_6,encoded_bits_7,encoded_bits_8,encoded_bits_9;

35 41

42 reg[N-1:0] sp0,sp1,sp2,sp3,sp4,sp5,sp6,sp7,sp8,sp9; 43 reg[N-1:0] c_encode_woe,c_nlp_pitch1,c_nlp_pitch2;

45 output reg done_codec2;

47 reg[N1-1:0] check_sig;

49 output reg [69:0] clk_count; 50 reg [4:0] count; 51 //------52 //-- State& Reg Declarations-- 53 //------

55 parameterSTART =3’d0, 56 INIT_FOR =3’d1, 57 CHECK_I =3’d2, 58 START_CODEC_ONE_FRAME =3’d3, 59 RUN_CODEC_ONE_FRAME =3’d4, 60 GET_CODEC_ONE_FRAME =3’d5, 61 INCR_I =3’d6, 62 DONE =3’d7;

64 reg [2:0]STATE,NEXT_STATE;

66 reg [9:0]i;

68 //------69 //-- Module Instantiations-- 70 //------

72 reg start_oneframe; 73 reg[N-1:0] in_prevf0,in_xq0,in_xq1,c_out_speech,c_read_c2_sn_out; 74 reg[N1-1:0] in_mem_x,in_mem_y,c_out_mem_fir,c_out_sq;

76 wire[N1-1:0] out_mem_x,out_mem_y,c_in_mem_fir,c_in_sq; 77 wire[N-1:0] out_prevf0, out_xq0, out_xq1,c_write_c2_sn; 78 wire [47: 0] c_encoded_bits; 79 wire done_oneframe,c_re_c2_sn,c_we_c2_sn, c_read_fir,c_write_fir;

81 wire [9:0] c_addr_speech,c_addr_sn,c_addr_mem_fir,c_addr_nlp_sq; 82 wire c_read_sq,c_write_sq; 83 wire [3:0] clsp9; 84 wire[N-1:0] check_sum,c_sn,c_encode_model_wo,c_pitch1,c_pitch2;

36 86

87 wire [4:0] c_lsp0,c_lsp1,c_lsp2,c_lsp3,c_lsp4,c_lsp5,c_lsp6,c_lsp7,c_lsp8,c_lsp9; 88 wire [9:0] c_cmax1,c_cmax2; 89 wire[N1-1:0] c_outreal1, c_outreal2, c_check_in_real,c_check_in_imag;

91 CODEC2_encoder_one_frame_mode2400 codec2_one_frame(start_oneframe,clk, rst,

93 in_mem_x, in_mem_y, in_prevf0, in_xq0, in_xq1, 94 c_out_speech,c_read_c2_sn_out,c_out_mem_fir,c_out_sq,

96 out_mem_x,out_mem_y, out_prevf0, out_xq0, out_xq1, 97 c_encoded_bits,c_addr_speech,c_addr_sn,c_write_c2_sn,

99 c_re_c2_sn,c_we_c2_sn,

100

101 c_addr_mem_fir,c_in_mem_fir,c_read_fir,c_write_fir, 102 c_addr_nlp_sq,c_in_sq,c_read_sq,c_write_sq, 103 done_oneframe, 104 c_encode_model_wo,c_pitch1,c_pitch2, c_cmax1, c_cmax2 105 );

106

107

108 /*------RAM_speech for one_frame- 160 samples------*/ 109 reg [9:0] addr_speech; 110 wire[N-1:0] out_speech; 111 RAM_speech_samples r_speech(addr_speech, clk,,1,0,out_speech);

112

113

114 reg [9:0] addr_speech_0; 115 wire[N-1:0] out_speech_0; 116 RAM_speech_0 r_speech_0(addr_speech_0,clk,,1,0,out_speech_0);

117

118 reg [9:0] addr_speech_1; 119 wire[N-1:0] out_speech_1; 120 RAM_speech_1 r_speech_1(addr_speech_1,clk,,1,0,out_speech_1);

121

122 reg [9:0] addr_speech_2; 123 wire[N-1:0] out_speech_2; 124 RAM_speech_2 r_speech_2(addr_speech_2,clk,,1,0,out_speech_2);

125

126 reg [9:0] addr_speech_3; 127 wire[N-1:0] out_speech_3; 128 RAM_speech_3 r_speech_3(addr_speech_3,clk,,1,0,out_speech_3);

129

130 reg [9:0] addr_speech_4;

37 131 wire[N-1:0] out_speech_4; 132 RAM_speech_4 r_speech_4(addr_speech_4,clk,,1,0,out_speech_4);

133

134 reg [9:0] addr_speech_5; 135 wire[N-1:0] out_speech_5; 136 RAM_speech_5 r_speech_5(addr_speech_5,clk,,1,0,out_speech_5);

137

138 reg [9:0] addr_speech_6; 139 wire[N-1:0] out_speech_6; 140 RAM_speech_6 r_speech_6(addr_speech_6,clk,,1,0,out_speech_6);

141

142 reg [9:0] addr_speech_7; 143 wire[N-1:0] out_speech_7; 144 RAM_speech_7 r_speech_7(addr_speech_7,clk,,1,0,out_speech_7);

145

146 reg [9:0] addr_speech_8; 147 wire[N-1:0] out_speech_8; 148 RAM_speech_8 r_speech_8(addr_speech_8,clk,,1,0,out_speech_8);

149

150 reg [9:0] addr_speech_9; 151 wire[N-1:0] out_speech_9; 152 RAM_speech_9 r_speech_9(addr_speech_9,clk,,1,0,out_speech_9);

153

154 reg [9:0] addr_speech_10; 155 wire[N-1:0] out_speech_10; 156 RAM_speech_10 r_speech_10(addr_speech_10,clk,,1,0,out_speech_10);

157

158 reg [9:0] addr_speech_11; 159 wire[N-1:0] out_speech_11; 160 RAM_speech_11 r_speech_11(addr_speech_11,clk,,1,0,out_speech_11);

161

162 reg [9:0] addr_speech_12; 163 wire[N-1:0] out_speech_12; 164 RAM_speech_12 r_speech_12(addr_speech_12,clk,,1,0,out_speech_12);

165

166 reg [9:0] addr_speech_13; 167 wire[N-1:0] out_speech_13; 168 RAM_speech_13 r_speech_13(addr_speech_13,clk,,1,0,out_speech_13);

169

170 reg [9:0] addr_speech_14; 171 wire[N-1:0] out_speech_14; 172 RAM_speech_14 r_speech_14(addr_speech_14,clk,,1,0,out_speech_14);

173

174 reg [9:0] addr_speech_15; 175 wire[N-1:0] out_speech_15;

38 176 RAM_speech_15 r_speech_15(addr_speech_15,clk,,1,0,out_speech_15);

177

178 reg [9:0] addr_speech_16; 179 wire[N-1:0] out_speech_16; 180 RAM_speech_16 r_speech_16(addr_speech_16,clk,,1,0,out_speech_16);

181

182 reg [9:0] addr_speech_17; 183 wire[N-1:0] out_speech_17; 184 RAM_speech_17 r_speech_17(addr_speech_17,clk,,1,0,out_speech_17);

185

186 reg [9:0] addr_speech_18; 187 wire[N-1:0] out_speech_18; 188 RAM_speech_18 r_speech_18(addr_speech_18,clk,,1,0,out_speech_18);

189

190 reg [9:0] addr_speech_19; 191 wire[N-1:0] out_speech_19; 192 RAM_speech_19 r_speech_19(addr_speech_19,clk,,1,0,out_speech_19);

193

194 reg [9:0] addr_speech_20; 195 wire[N-1:0] out_speech_20; 196 RAM_speech_20 r_speech_20(addr_speech_20,clk,,1,0,out_speech_20);

197

198 reg [9:0] addr_speech_21; 199 wire[N-1:0] out_speech_21; 200 RAM_speech_21 r_speech_21(addr_speech_21,clk,,1,0,out_speech_21);

201

202 reg [9:0] addr_speech_22; 203 wire[N-1:0] out_speech_22; 204 RAM_speech_22 r_speech_22(addr_speech_22,clk,,1,0,out_speech_22);

205

206 reg [9:0] addr_speech_23; 207 wire[N-1:0] out_speech_23; 208 RAM_speech_23 r_speech_23(addr_speech_23,clk,,1,0,out_speech_23);

209

210 reg [9:0] addr_speech_24; 211 wire[N-1:0] out_speech_24; 212 RAM_speech_24 r_speech_24(addr_speech_24,clk,,1,0,out_speech_24);

213

214 reg [9:0] addr_speech_25; 215 wire[N-1:0] out_speech_25; 216 RAM_speech_25 r_speech_25(addr_speech_25,clk,,1,0,out_speech_25);

217

218 reg [9:0] addr_speech_26; 219 wire[N-1:0] out_speech_26; 220 RAM_speech_26 r_speech_26(addr_speech_26,clk,,1,0,out_speech_26);

39 221

222 reg [9:0] addr_speech_27; 223 wire[N-1:0] out_speech_27; 224 RAM_speech_27 r_speech_27(addr_speech_27,clk,,1,0,out_speech_27);

225

226 reg [9:0] addr_speech_28; 227 wire[N-1:0] out_speech_28; 228 RAM_speech_28 r_speech_28(addr_speech_28,clk,,1,0,out_speech_28);

229

230 reg [9:0] addr_speech_29; 231 wire[N-1:0] out_speech_29; 232 RAM_speech_29 r_speech_29(addr_speech_29,clk,,1,0,out_speech_29);

233

234 reg [9:0] addr_speech_30; 235 wire[N-1:0] out_speech_30; 236 RAM_speech_30 r_speech_30(addr_speech_30,clk,,1,0,out_speech_30);

237

238 reg [9:0] addr_speech_31; 239 wire[N-1:0] out_speech_31; 240 RAM_speech_31 r_speech_31(addr_speech_31,clk,,1,0,out_speech_31);

241

242 reg [9:0] addr_speech_32; 243 wire[N-1:0] out_speech_32; 244 RAM_speech_32 r_speech_32(addr_speech_32,clk,,1,0,out_speech_32);

245

246 reg [9:0] addr_speech_33; 247 wire[N-1:0] out_speech_33; 248 RAM_speech_33 r_speech_33(addr_speech_33,clk,,1,0,out_speech_33);

249

250 reg [9:0] addr_speech_34; 251 wire[N-1:0] out_speech_34; 252 RAM_speech_34 r_speech_34(addr_speech_34,clk,,1,0,out_speech_34);

253

254 reg [9:0] addr_speech_35; 255 wire[N-1:0] out_speech_35; 256 RAM_speech_35 r_speech_35(addr_speech_35,clk,,1,0,out_speech_35);

257

258 reg [9:0] addr_speech_36; 259 wire[N-1:0] out_speech_36; 260 RAM_speech_36 r_speech_36(addr_speech_36,clk,,1,0,out_speech_36);

261

262 reg [9:0] addr_speech_37; 263 wire[N-1:0] out_speech_37; 264 RAM_speech_37 r_speech_37(addr_speech_37,clk,,1,0,out_speech_37);

265

40 266 reg [9:0] addr_speech_38; 267 wire[N-1:0] out_speech_38; 268 RAM_speech_38 r_speech_38(addr_speech_38,clk,,1,0,out_speech_38);

269

270 reg [9:0] addr_speech_39; 271 wire[N-1:0] out_speech_39; 272 RAM_speech_39 r_speech_39(addr_speech_39,clk,,1,0,out_speech_39);

273

274 reg [9:0] addr_speech_40; 275 wire[N-1:0] out_speech_40; 276 RAM_speech_40 r_speech_40(addr_speech_40,clk,,1,0,out_speech_40);

277

278 reg [9:0] addr_speech_41; 279 wire[N-1:0] out_speech_41; 280 RAM_speech_41 r_speech_41(addr_speech_41,clk,,1,0,out_speech_41);

281

282 reg [9:0] addr_speech_42; 283 wire[N-1:0] out_speech_42; 284 RAM_speech_42 r_speech_42(addr_speech_42,clk,,1,0,out_speech_42);

285

286 reg [9:0] addr_speech_43; 287 wire[N-1:0] out_speech_43; 288 RAM_speech_43 r_speech_43(addr_speech_43,clk,,1,0,out_speech_43);

289

290 reg [9:0] addr_speech_44; 291 wire[N-1:0] out_speech_44; 292 RAM_speech_44 r_speech_44(addr_speech_44,clk,,1,0,out_speech_44);

293

294 reg [9:0] addr_speech_45; 295 wire[N-1:0] out_speech_45; 296 RAM_speech_45 r_speech_45(addr_speech_45,clk,,1,0,out_speech_45);

297

298 reg [9:0] addr_speech_46; 299 wire[N-1:0] out_speech_46; 300 RAM_speech_46 r_speech_46(addr_speech_46,clk,,1,0,out_speech_46);

301

302 reg [9:0] addr_speech_47; 303 wire[N-1:0] out_speech_47; 304 RAM_speech_47 r_speech_47(addr_speech_47,clk,,1,0,out_speech_47);

305

306 reg [9:0] addr_speech_48; 307 wire[N-1:0] out_speech_48; 308 RAM_speech_48 r_speech_48(addr_speech_48,clk,,1,0,out_speech_48);

309

310 reg [9:0] addr_speech_49;

41 311 wire[N-1:0] out_speech_49; 312 RAM_speech_49 r_speech_49(addr_speech_49,clk,,1,0,out_speech_49);

313

314 reg [9:0] addr_speech_50; 315 wire[N-1:0] out_speech_50; 316 RAM_speech_50 r_speech_50(addr_speech_50,clk,,1,0,out_speech_50);

317

318 reg [9:0] addr_speech_51; 319 wire[N-1:0] out_speech_51; 320 RAM_speech_51 r_speech_51(addr_speech_51,clk,,1,0,out_speech_51);

321

322 reg [9:0] addr_speech_52; 323 wire[N-1:0] out_speech_52; 324 RAM_speech_52 r_speech_52(addr_speech_52,clk,,1,0,out_speech_52);

325

326 reg [9:0] addr_speech_53; 327 wire[N-1:0] out_speech_53; 328 RAM_speech_53 r_speech_53(addr_speech_53,clk,,1,0,out_speech_53);

329

330 reg [9:0] addr_speech_54; 331 wire[N-1:0] out_speech_54; 332 RAM_speech_54 r_speech_54(addr_speech_54,clk,,1,0,out_speech_54);

333

334 reg [9:0] addr_speech_55; 335 wire[N-1:0] out_speech_55; 336 RAM_speech_55 r_speech_55(addr_speech_55,clk,,1,0,out_speech_55);

337

338 reg [9:0] addr_speech_56; 339 wire[N-1:0] out_speech_56; 340 RAM_speech_56 r_speech_56(addr_speech_56,clk,,1,0,out_speech_56);

341

342 reg [9:0] addr_speech_57; 343 wire[N-1:0] out_speech_57; 344 RAM_speech_57 r_speech_57(addr_speech_57,clk,,1,0,out_speech_57);

345

346 reg [9:0] addr_speech_58; 347 wire[N-1:0] out_speech_58; 348 RAM_speech_58 r_speech_58(addr_speech_58,clk,,1,0,out_speech_58);

349

350 reg [9:0] addr_speech_59; 351 wire[N-1:0] out_speech_59; 352 RAM_speech_59 r_speech_59(addr_speech_59,clk,,1,0,out_speech_59);

353

354 reg [9:0] addr_speech_60; 355 wire[N-1:0] out_speech_60;

42 356 RAM_speech_60 r_speech_60(addr_speech_60,clk,,1,0,out_speech_60);

357

358 reg [9:0] addr_speech_61; 359 wire[N-1:0] out_speech_61; 360 RAM_speech_61 r_speech_61(addr_speech_61,clk,,1,0,out_speech_61);

361

362 reg [9:0] addr_speech_62; 363 wire[N-1:0] out_speech_62; 364 RAM_speech_62 r_speech_62(addr_speech_62,clk,,1,0,out_speech_62);

365

366 reg [9:0] addr_speech_63; 367 wire[N-1:0] out_speech_63; 368 RAM_speech_63 r_speech_63(addr_speech_63,clk,,1,0,out_speech_63);

369

370 reg [9:0] addr_speech_64; 371 wire[N-1:0] out_speech_64; 372 RAM_speech_64 r_speech_64(addr_speech_64,clk,,1,0,out_speech_64);

373

374 reg [9:0] addr_speech_65; 375 wire[N-1:0] out_speech_65; 376 RAM_speech_65 r_speech_65(addr_speech_65,clk,,1,0,out_speech_65);

377

378 reg [9:0] addr_speech_66; 379 wire[N-1:0] out_speech_66; 380 RAM_speech_66 r_speech_66(addr_speech_66,clk,,1,0,out_speech_66);

381

382 reg [9:0] addr_speech_67; 383 wire[N-1:0] out_speech_67; 384 RAM_speech_67 r_speech_67(addr_speech_67,clk,,1,0,out_speech_67);

385

386 reg [9:0] addr_speech_68; 387 wire[N-1:0] out_speech_68; 388 RAM_speech_68 r_speech_68(addr_speech_68,clk,,1,0,out_speech_68);

389

390 reg [9:0] addr_speech_69; 391 wire[N-1:0] out_speech_69; 392 RAM_speech_69 r_speech_69(addr_speech_69,clk,,1,0,out_speech_69);

393

394 reg [9:0] addr_speech_70; 395 wire[N-1:0] out_speech_70; 396 RAM_speech_70 r_speech_70(addr_speech_70,clk,,1,0,out_speech_70);

397

398 reg [9:0] addr_speech_71; 399 wire[N-1:0] out_speech_71; 400 RAM_speech_71 r_speech_71(addr_speech_71,clk,,1,0,out_speech_71);

43 401

402 reg [9:0] addr_speech_72; 403 wire[N-1:0] out_speech_72; 404 RAM_speech_72 r_speech_72(addr_speech_72,clk,,1,0,out_speech_72);

405

406 reg [9:0] addr_speech_73; 407 wire[N-1:0] out_speech_73; 408 RAM_speech_73 r_speech_73(addr_speech_73,clk,,1,0,out_speech_73);

409

410 reg [9:0] addr_speech_74; 411 wire[N-1:0] out_speech_74; 412 RAM_speech_74 r_speech_74(addr_speech_74,clk,,1,0,out_speech_74);

413

414 reg [9:0] addr_speech_75; 415 wire[N-1:0] out_speech_75; 416 RAM_speech_75 r_speech_75(addr_speech_75,clk,,1,0,out_speech_75);

417

418 reg [9:0] addr_speech_76; 419 wire[N-1:0] out_speech_76; 420 RAM_speech_76 r_speech_76(addr_speech_76,clk,,1,0,out_speech_76);

421

422 reg [9:0] addr_speech_77; 423 wire[N-1:0] out_speech_77; 424 RAM_speech_77 r_speech_77(addr_speech_77,clk,,1,0,out_speech_77);

425

426 reg [9:0] addr_speech_78; 427 wire[N-1:0] out_speech_78; 428 RAM_speech_78 r_speech_78(addr_speech_78,clk,,1,0,out_speech_78);

429

430 reg [9:0] addr_speech_79; 431 wire[N-1:0] out_speech_79; 432 RAM_speech_79 r_speech_79(addr_speech_79,clk,,1,0,out_speech_79);

433

434 reg [9:0] addr_speech_80; 435 wire[N-1:0] out_speech_80; 436 RAM_speech_80 r_speech_80(addr_speech_80,clk,,1,0,out_speech_80);

437

438 reg [9:0] addr_speech_81; 439 wire[N-1:0] out_speech_81; 440 RAM_speech_81 r_speech_81(addr_speech_81,clk,,1,0,out_speech_81);

441

442 reg [9:0] addr_speech_82; 443 wire[N-1:0] out_speech_82; 444 RAM_speech_82 r_speech_82(addr_speech_82,clk,,1,0,out_speech_82);

445

44 446 reg [9:0] addr_speech_83; 447 wire[N-1:0] out_speech_83; 448 RAM_speech_83 r_speech_83(addr_speech_83,clk,,1,0,out_speech_83);

449

450 reg [9:0] addr_speech_84; 451 wire[N-1:0] out_speech_84; 452 RAM_speech_84 r_speech_84(addr_speech_84,clk,,1,0,out_speech_84);

453

454 reg [9:0] addr_speech_85; 455 wire[N-1:0] out_speech_85; 456 RAM_speech_85 r_speech_85(addr_speech_85,clk,,1,0,out_speech_85);

457

458 reg [9:0] addr_speech_86; 459 wire[N-1:0] out_speech_86; 460 RAM_speech_86 r_speech_86(addr_speech_86,clk,,1,0,out_speech_86);

461

462 reg [9:0] addr_speech_87; 463 wire[N-1:0] out_speech_87; 464 RAM_speech_87 r_speech_87(addr_speech_87,clk,,1,0,out_speech_87);

465

466 reg [9:0] addr_speech_88; 467 wire[N-1:0] out_speech_88; 468 RAM_speech_88 r_speech_88(addr_speech_88,clk,,1,0,out_speech_88);

469

470 reg [9:0] addr_speech_89; 471 wire[N-1:0] out_speech_89; 472 RAM_speech_89 r_speech_89(addr_speech_89,clk,,1,0,out_speech_89);

473

474 reg [9:0] addr_speech_90; 475 wire[N-1:0] out_speech_90; 476 RAM_speech_90 r_speech_90(addr_speech_90,clk,,1,0,out_speech_90);

477

478 reg [9:0] addr_speech_91; 479 wire[N-1:0] out_speech_91; 480 RAM_speech_91 r_speech_91(addr_speech_91,clk,,1,0,out_speech_91);

481

482 reg [9:0] addr_speech_92; 483 wire[N-1:0] out_speech_92; 484 RAM_speech_92 r_speech_92(addr_speech_92,clk,,1,0,out_speech_92);

485

486 reg [9:0] addr_speech_93; 487 wire[N-1:0] out_speech_93; 488 RAM_speech_93 r_speech_93(addr_speech_93,clk,,1,0,out_speech_93);

489

490 reg [9:0] addr_speech_94;

45 491 wire[N-1:0] out_speech_94; 492 RAM_speech_94 r_speech_94(addr_speech_94,clk,,1,0,out_speech_94);

493

494 reg [9:0] addr_speech_95; 495 wire[N-1:0] out_speech_95; 496 RAM_speech_95 r_speech_95(addr_speech_95,clk,,1,0,out_speech_95);

497

498 reg [9:0] addr_speech_96; 499 wire[N-1:0] out_speech_96; 500 RAM_speech_96 r_speech_96(addr_speech_96,clk,,1,0,out_speech_96);

501

502 reg [9:0] addr_speech_97; 503 wire[N-1:0] out_speech_97; 504 RAM_speech_97 r_speech_97(addr_speech_97,clk,,1,0,out_speech_97);

505

506 reg [9:0] addr_speech_98; 507 wire[N-1:0] out_speech_98; 508 RAM_speech_98 r_speech_98(addr_speech_98,clk,,1,0,out_speech_98);

509

510 reg [9:0] addr_speech_99; 511 wire[N-1:0] out_speech_99; 512 RAM_speech_99 r_speech_99(addr_speech_99,clk,,1,0,out_speech_99);

513

514 reg [9:0] addr_speech_100; 515 wire[N-1:0] out_speech_100; 516 RAM_speech_100 r_speech_100(addr_speech_100,clk,,1,0,out_speech_100);

517

518 reg [9:0] addr_speech_101; 519 wire[N-1:0] out_speech_101; 520 RAM_speech_101 r_speech_101(addr_speech_101,clk,,1,0,out_speech_101);

521

522 reg [9:0] addr_speech_102; 523 wire[N-1:0] out_speech_102; 524 RAM_speech_102 r_speech_102(addr_speech_102,clk,,1,0,out_speech_102);

525

526 reg [9:0] addr_speech_103; 527 wire[N-1:0] out_speech_103; 528 RAM_speech_103 r_speech_103(addr_speech_103,clk,,1,0,out_speech_103);

529

530 reg [9:0] addr_speech_104; 531 wire[N-1:0] out_speech_104; 532 RAM_speech_104 r_speech_104(addr_speech_104,clk,,1,0,out_speech_104);

533

534 reg [9:0] addr_speech_105; 535 wire[N-1:0] out_speech_105;

46 536 RAM_speech_105 r_speech_105(addr_speech_105,clk,,1,0,out_speech_105);

537

538 reg [9:0] addr_speech_106; 539 wire[N-1:0] out_speech_106; 540 RAM_speech_106 r_speech_106(addr_speech_106,clk,,1,0,out_speech_106);

541

542 reg [9:0] addr_speech_107; 543 wire[N-1:0] out_speech_107; 544 RAM_speech_107 r_speech_107(addr_speech_107,clk,,1,0,out_speech_107);

545

546 reg [9:0] addr_speech_108; 547 wire[N-1:0] out_speech_108; 548 RAM_speech_108 r_speech_108(addr_speech_108,clk,,1,0,out_speech_108);

549

550 reg [9:0] addr_speech_109; 551 wire[N-1:0] out_speech_109; 552 RAM_speech_109 r_speech_109(addr_speech_109,clk,,1,0,out_speech_109);

553

554 reg [9:0] addr_speech_110; 555 wire[N-1:0] out_speech_110; 556 RAM_speech_110 r_speech_110(addr_speech_110,clk,,1,0,out_speech_110);

557

558 reg [9:0] addr_speech_111; 559 wire[N-1:0] out_speech_111; 560 RAM_speech_111 r_speech_111(addr_speech_111,clk,,1,0,out_speech_111);

561

562 reg [9:0] addr_speech_112; 563 wire[N-1:0] out_speech_112; 564 RAM_speech_112 r_speech_112(addr_speech_112,clk,,1,0,out_speech_112);

565

566 reg [9:0] addr_speech_113; 567 wire[N-1:0] out_speech_113; 568 RAM_speech_113 r_speech_113(addr_speech_113,clk,,1,0,out_speech_113);

569

570 reg [9:0] addr_speech_114; 571 wire[N-1:0] out_speech_114; 572 RAM_speech_114 r_speech_114(addr_speech_114,clk,,1,0,out_speech_114);

573

574 reg [9:0] addr_speech_115; 575 wire[N-1:0] out_speech_115; 576 RAM_speech_115 r_speech_115(addr_speech_115,clk,,1,0,out_speech_115);

577

578 reg [9:0] addr_speech_116; 579 wire[N-1:0] out_speech_116; 580 RAM_speech_116 r_speech_116(addr_speech_116,clk,,1,0,out_speech_116);

47 581

582 reg [9:0] addr_speech_117; 583 wire[N-1:0] out_speech_117; 584 RAM_speech_117 r_speech_117(addr_speech_117,clk,,1,0,out_speech_117);

585

586 reg [9:0] addr_speech_118; 587 wire[N-1:0] out_speech_118; 588 RAM_speech_118 r_speech_118(addr_speech_118,clk,,1,0,out_speech_118);

589

590 reg [9:0] addr_speech_119; 591 wire[N-1:0] out_speech_119; 592 RAM_speech_119 r_speech_119(addr_speech_119,clk,,1,0,out_speech_119);

593

594 reg [9:0] addr_speech_120; 595 wire[N-1:0] out_speech_120; 596 RAM_speech_120 r_speech_120(addr_speech_120,clk,,1,0,out_speech_120);

597

598 reg [9:0] addr_speech_121; 599 wire[N-1:0] out_speech_121; 600 RAM_speech_121 r_speech_121(addr_speech_121,clk,,1,0,out_speech_121);

601

602 reg [9:0] addr_speech_122; 603 wire[N-1:0] out_speech_122; 604 RAM_speech_122 r_speech_122(addr_speech_122,clk,,1,0,out_speech_122);

605

606 reg [9:0] addr_speech_123; 607 wire[N-1:0] out_speech_123; 608 RAM_speech_123 r_speech_123(addr_speech_123,clk,,1,0,out_speech_123);

609

610 reg [9:0] addr_speech_124; 611 wire[N-1:0] out_speech_124; 612 RAM_speech_124 r_speech_124(addr_speech_124,clk,,1,0,out_speech_124);

613

614 reg [9:0] addr_speech_125; 615 wire[N-1:0] out_speech_125; 616 RAM_speech_125 r_speech_125(addr_speech_125,clk,,1,0,out_speech_125);

617

618 reg [9:0] addr_speech_126; 619 wire[N-1:0] out_speech_126; 620 RAM_speech_126 r_speech_126(addr_speech_126,clk,,1,0,out_speech_126);

621

622 reg [9:0] addr_speech_127; 623 wire[N-1:0] out_speech_127; 624 RAM_speech_127 r_speech_127(addr_speech_127,clk,,1,0,out_speech_127);

625

48 626 reg [9:0] addr_speech_128; 627 wire[N-1:0] out_speech_128; 628 RAM_speech_128 r_speech_128(addr_speech_128,clk,,1,0,out_speech_128);

629

630 reg [9:0] addr_speech_129; 631 wire[N-1:0] out_speech_129; 632 RAM_speech_129 r_speech_129(addr_speech_129,clk,,1,0,out_speech_129);

633

634 reg [9:0] addr_speech_130; 635 wire[N-1:0] out_speech_130; 636 RAM_speech_130 r_speech_130(addr_speech_130,clk,,1,0,out_speech_130);

637

638 reg [9:0] addr_speech_131; 639 wire[N-1:0] out_speech_131; 640 RAM_speech_131 r_speech_131(addr_speech_131,clk,,1,0,out_speech_131);

641

642 reg [9:0] addr_speech_132; 643 wire[N-1:0] out_speech_132; 644 RAM_speech_132 r_speech_132(addr_speech_132,clk,,1,0,out_speech_132);

645

646 reg [9:0] addr_speech_133; 647 wire[N-1:0] out_speech_133; 648 RAM_speech_133 r_speech_133(addr_speech_133,clk,,1,0,out_speech_133);

649

650 reg [9:0] addr_speech_134; 651 wire[N-1:0] out_speech_134; 652 RAM_speech_134 r_speech_134(addr_speech_134,clk,,1,0,out_speech_134);

653

654 reg [9:0] addr_speech_135; 655 wire[N-1:0] out_speech_135; 656 RAM_speech_135 r_speech_135(addr_speech_135,clk,,1,0,out_speech_135);

657

658 reg [9:0] addr_speech_136; 659 wire[N-1:0] out_speech_136; 660 RAM_speech_136 r_speech_136(addr_speech_136,clk,,1,0,out_speech_136);

661

662 reg [9:0] addr_speech_137; 663 wire[N-1:0] out_speech_137; 664 RAM_speech_137 r_speech_137(addr_speech_137,clk,,1,0,out_speech_137);

665

666 reg [9:0] addr_speech_138; 667 wire[N-1:0] out_speech_138; 668 RAM_speech_138 r_speech_138(addr_speech_138,clk,,1,0,out_speech_138);

669

670 reg [9:0] addr_speech_139;

49 671 wire[N-1:0] out_speech_139; 672 RAM_speech_139 r_speech_139(addr_speech_139,clk,,1,0,out_speech_139);

673

674 reg [9:0] addr_speech_140; 675 wire[N-1:0] out_speech_140; 676 RAM_speech_140 r_speech_140(addr_speech_140,clk,,1,0,out_speech_140);

677

678 reg [9:0] addr_speech_141; 679 wire[N-1:0] out_speech_141; 680 RAM_speech_141 r_speech_141(addr_speech_141,clk,,1,0,out_speech_141);

681

682 reg [9:0] addr_speech_142; 683 wire[N-1:0] out_speech_142; 684 RAM_speech_142 r_speech_142(addr_speech_142,clk,,1,0,out_speech_142);

685

686 reg [9:0] addr_speech_143; 687 wire[N-1:0] out_speech_143; 688 RAM_speech_143 r_speech_143(addr_speech_143,clk,,1,0,out_speech_143);

689

690 reg [9:0] addr_speech_144; 691 wire[N-1:0] out_speech_144; 692 RAM_speech_144 r_speech_144(addr_speech_144,clk,,1,0,out_speech_144);

693

694 reg [9:0] addr_speech_145; 695 wire[N-1:0] out_speech_145; 696 RAM_speech_145 r_speech_145(addr_speech_145,clk,,1,0,out_speech_145);

697

698 reg [9:0] addr_speech_146; 699 wire[N-1:0] out_speech_146; 700 RAM_speech_146 r_speech_146(addr_speech_146,clk,,1,0,out_speech_146);

701

702 reg [9:0] addr_speech_147; 703 wire[N-1:0] out_speech_147; 704 RAM_speech_147 r_speech_147(addr_speech_147,clk,,1,0,out_speech_147);

705

706 reg [9:0] addr_speech_148; 707 wire[N-1:0] out_speech_148; 708 RAM_speech_148 r_speech_148(addr_speech_148,clk,,1,0,out_speech_148);

709

710 reg [9:0] addr_speech_149; 711 wire[N-1:0] out_speech_149; 712 RAM_speech_149 r_speech_149(addr_speech_149,clk,,1,0,out_speech_149);

713

714 /*------RAM_speech for one_frame- 320 size------*/ 715 reg [9:0] addr_sn;

50 716 reg[N-1:0] write_c2_sn; 717 reg re_c2_sn,we_c2_sn; 718 wire[N-1:0] read_c2_sn_out;

719

720 RAM_Sn_codec2_enc c2_sn(addr_sn,clk,write_c2_sn,re_c2_sn, 721 we_c2_sn,read_c2_sn_out);

722

723 /*------RAM_nlp_mem_fir- size 48------*/ 724 reg [9:0] addr_mem_fir; 725 reg[N1-1:0] in_mem_fir; 726 reg read_fir, write_fir; 727 wire[N1-1:0] out_mem_fir;

728

729 RAM_nlp_mem_fir_80 mem_fir(addr_mem_fir,clk,in_mem_fir,read_fir, 730 write_fir,out_mem_fir);

731

732 /*------RAM_nlp_sq- size 320------*/ 733 reg [9:0] addr_nlp_sq; 734 reg[N1-1:0] in_sq; 735 reg read_sq,write_sq; 736 wire[N1-1:0] out_sq;

737

738 RAM_nlp_sq_80 nlp_sq(addr_nlp_sq,clk,in_sq,read_sq,write_sq,out_sq);

739

740

741 //------742 //-- Begin Declarations& Coding-- 743 //------

744

745 always@(posedge clk or negedge rst)// DetermineSTATE 746 begin

747

748 if(rst == 1’b0) 749 STATE <=START; 750 else 751 STATE <=NEXT_STATE;

752

753 end

754

755 always@(*) 756 begin 757 case(STATE)

758

759 START: 760 begin

51 761 if(start_codec2) 762 begin 763 NEXT_STATE=INIT_FOR; 764 end 765 else 766 begin 767 NEXT_STATE=START; 768 end

769

770 end

771

772 INIT_FOR: 773 begin 774 NEXT_STATE=CHECK_I; 775 end

776

777 CHECK_I: 778 begin 779 if(i < 10’d150) 780 begin 781 NEXT_STATE=START_CODEC_ONE_FRAME; 782 end 783 else 784 begin 785 NEXT_STATE=DONE; 786 end 787 end

788

789 START_CODEC_ONE_FRAME: 790 begin 791 NEXT_STATE=RUN_CODEC_ONE_FRAME; 792 end

793

794 RUN_CODEC_ONE_FRAME: 795 begin 796 if(done_oneframe) 797 begin 798 NEXT_STATE=GET_CODEC_ONE_FRAME; 799 end 800 else 801 begin 802 NEXT_STATE=RUN_CODEC_ONE_FRAME; 803 end

804

805 end

52 806

807 GET_CODEC_ONE_FRAME: 808 begin 809 NEXT_STATE=INCR_I; 810 end

811

812 INCR_I: 813 begin 814 NEXT_STATE=CHECK_I; 815 end

816

817 DONE: 818 begin 819 NEXT_STATE=DONE; 820 end

821

822 endcase 823 end

824

825

826 always@(*)//RAM Assignments 827 begin

828

829

830 case(STATE)

831

832 RUN_CODEC_ONE_FRAME: 833 begin 834 addr_sn= c_addr_sn; 835 c_read_c2_sn_out= read_c2_sn_out; 836 re_c2_sn= c_re_c2_sn; 837 we_c2_sn= c_we_c2_sn; 838 write_c2_sn= c_write_c2_sn;

839

840

841 //mem_fir[48] 842 addr_mem_fir= c_addr_mem_fir; 843 c_out_mem_fir= out_mem_fir; 844 read_fir= c_read_fir; 845 write_fir= c_write_fir; 846 in_mem_fir= c_in_mem_fir;

847

848 //sq[320] 849 addr_nlp_sq= c_addr_nlp_sq; 850 c_out_sq= out_sq;

53 851 read_sq= c_read_sq; 852 write_sq= c_write_sq; 853 in_sq= c_in_sq;

854

855 case(i) 856 10’d0: 857 begin 858 addr_speech_0= c_addr_speech; 859 c_out_speech= out_speech_0; 860 end

861

862 10’d1: 863 begin 864 addr_speech_1= c_addr_speech; 865 c_out_speech= out_speech_1; 866 end 867 10’d2: 868 begin 869 addr_speech_2= c_addr_speech; 870 c_out_speech= out_speech_2; 871 end

872

873 10’d3: 874 begin 875 addr_speech_3= c_addr_speech; 876 c_out_speech= out_speech_3; 877 end 878 10’d4: 879 begin 880 addr_speech_4= c_addr_speech; 881 c_out_speech= out_speech_4; 882 end 883 10’d5: 884 begin 885 addr_speech_5= c_addr_speech; 886 c_out_speech= out_speech_5; 887 end 888 10’d6: 889 begin 890 addr_speech_6= c_addr_speech; 891 c_out_speech= out_speech_6; 892 end 893 10’d7: 894 begin 895 addr_speech_7= c_addr_speech;

54 896 c_out_speech= out_speech_7; 897 end 898 10’d8: 899 begin 900 addr_speech_8= c_addr_speech; 901 c_out_speech= out_speech_8; 902 end 903 10’d9: 904 begin 905 addr_speech_9= c_addr_speech; 906 c_out_speech= out_speech_9; 907 end

908

909 10’d10: 910 begin 911 addr_speech_10= c_addr_speech; 912 c_out_speech= out_speech_10; 913 end

914

915 10’d11: 916 begin 917 addr_speech_11= c_addr_speech; 918 c_out_speech= out_speech_11; 919 end

920

921 10’d12: 922 begin 923 addr_speech_12= c_addr_speech; 924 c_out_speech= out_speech_12; 925 end

926

927 10’d13: 928 begin 929 addr_speech_13= c_addr_speech; 930 c_out_speech= out_speech_13; 931 end

932

933 10’d14: 934 begin 935 addr_speech_14= c_addr_speech; 936 c_out_speech= out_speech_14; 937 end

938

939 10’d15: 940 begin

55 941 addr_speech_15= c_addr_speech; 942 c_out_speech= out_speech_15; 943 end

944

945 10’d16: 946 begin 947 addr_speech_16= c_addr_speech; 948 c_out_speech= out_speech_16; 949 end

950

951 10’d17: 952 begin 953 addr_speech_17= c_addr_speech; 954 c_out_speech= out_speech_17; 955 end

956

957 10’d18: 958 begin 959 addr_speech_18= c_addr_speech; 960 c_out_speech= out_speech_18; 961 end

962

963 10’d19: 964 begin 965 addr_speech_19= c_addr_speech; 966 c_out_speech= out_speech_19; 967 end

968

969 10’d20: 970 begin 971 addr_speech_20= c_addr_speech; 972 c_out_speech= out_speech_20; 973 end

974

975 10’d21: 976 begin 977 addr_speech_21= c_addr_speech; 978 c_out_speech= out_speech_21; 979 end

980

981 10’d22: 982 begin 983 addr_speech_22= c_addr_speech; 984 c_out_speech= out_speech_22; 985 end

56 986

987 10’d23: 988 begin 989 addr_speech_23= c_addr_speech; 990 c_out_speech= out_speech_23; 991 end

992

993 10’d24: 994 begin 995 addr_speech_24= c_addr_speech; 996 c_out_speech= out_speech_24; 997 end

998

999 10’d25: 1000 begin 1001 addr_speech_25= c_addr_speech; 1002 c_out_speech= out_speech_25; 1003 end

1004

1005 10’d26: 1006 begin 1007 addr_speech_26= c_addr_speech; 1008 c_out_speech= out_speech_26; 1009 end

1010

1011 10’d27: 1012 begin 1013 addr_speech_27= c_addr_speech; 1014 c_out_speech= out_speech_27; 1015 end

1016

1017 10’d28: 1018 begin 1019 addr_speech_28= c_addr_speech; 1020 c_out_speech= out_speech_28; 1021 end

1022

1023 10’d29: 1024 begin 1025 addr_speech_29= c_addr_speech; 1026 c_out_speech= out_speech_29; 1027 end

1028

1029 10’d30: 1030 begin

57 1031 addr_speech_30= c_addr_speech; 1032 c_out_speech= out_speech_30; 1033 end

1034

1035 10’d31: 1036 begin 1037 addr_speech_31= c_addr_speech; 1038 c_out_speech= out_speech_31; 1039 end

1040

1041 10’d32: 1042 begin 1043 addr_speech_32= c_addr_speech; 1044 c_out_speech= out_speech_32; 1045 end

1046

1047 10’d33: 1048 begin 1049 addr_speech_33= c_addr_speech; 1050 c_out_speech= out_speech_33; 1051 end

1052

1053 10’d34: 1054 begin 1055 addr_speech_34= c_addr_speech; 1056 c_out_speech= out_speech_34; 1057 end

1058

1059 10’d35: 1060 begin 1061 addr_speech_35= c_addr_speech; 1062 c_out_speech= out_speech_35; 1063 end

1064

1065 10’d36: 1066 begin 1067 addr_speech_36= c_addr_speech; 1068 c_out_speech= out_speech_36; 1069 end

1070

1071 10’d37: 1072 begin 1073 addr_speech_37= c_addr_speech; 1074 c_out_speech= out_speech_37; 1075 end

58 1076

1077 10’d38: 1078 begin 1079 addr_speech_38= c_addr_speech; 1080 c_out_speech= out_speech_38; 1081 end

1082

1083 10’d39: 1084 begin 1085 addr_speech_39= c_addr_speech; 1086 c_out_speech= out_speech_39; 1087 end

1088

1089 10’d40: 1090 begin 1091 addr_speech_40= c_addr_speech; 1092 c_out_speech= out_speech_40; 1093 end

1094

1095 10’d41: 1096 begin 1097 addr_speech_41= c_addr_speech; 1098 c_out_speech= out_speech_41; 1099 end

1100

1101 10’d42: 1102 begin 1103 addr_speech_42= c_addr_speech; 1104 c_out_speech= out_speech_42; 1105 end

1106

1107 10’d43: 1108 begin 1109 addr_speech_43= c_addr_speech; 1110 c_out_speech= out_speech_43; 1111 end

1112

1113 10’d44: 1114 begin 1115 addr_speech_44= c_addr_speech; 1116 c_out_speech= out_speech_44; 1117 end

1118

1119 10’d45: 1120 begin

59 1121 addr_speech_45= c_addr_speech; 1122 c_out_speech= out_speech_45; 1123 end

1124

1125 10’d46: 1126 begin 1127 addr_speech_46= c_addr_speech; 1128 c_out_speech= out_speech_46; 1129 end

1130

1131 10’d47: 1132 begin 1133 addr_speech_47= c_addr_speech; 1134 c_out_speech= out_speech_47; 1135 end

1136

1137 10’d48: 1138 begin 1139 addr_speech_48= c_addr_speech; 1140 c_out_speech= out_speech_48; 1141 end

1142

1143 10’d49: 1144 begin 1145 addr_speech_49= c_addr_speech; 1146 c_out_speech= out_speech_49; 1147 end

1148

1149 10’d50: 1150 begin 1151 addr_speech_50= c_addr_speech; 1152 c_out_speech= out_speech_50; 1153 end

1154

1155 10’d51: 1156 begin 1157 addr_speech_51= c_addr_speech; 1158 c_out_speech= out_speech_51; 1159 end

1160

1161 10’d52: 1162 begin 1163 addr_speech_52= c_addr_speech; 1164 c_out_speech= out_speech_52; 1165 end

60 1166

1167 10’d53: 1168 begin 1169 addr_speech_53= c_addr_speech; 1170 c_out_speech= out_speech_53; 1171 end

1172

1173 10’d54: 1174 begin 1175 addr_speech_54= c_addr_speech; 1176 c_out_speech= out_speech_54; 1177 end

1178

1179 10’d55: 1180 begin 1181 addr_speech_55= c_addr_speech; 1182 c_out_speech= out_speech_55; 1183 end

1184

1185 10’d56: 1186 begin 1187 addr_speech_56= c_addr_speech; 1188 c_out_speech= out_speech_56; 1189 end

1190

1191 10’d57: 1192 begin 1193 addr_speech_57= c_addr_speech; 1194 c_out_speech= out_speech_57; 1195 end

1196

1197 10’d58: 1198 begin 1199 addr_speech_58= c_addr_speech; 1200 c_out_speech= out_speech_58; 1201 end

1202

1203 10’d59: 1204 begin 1205 addr_speech_59= c_addr_speech; 1206 c_out_speech= out_speech_59; 1207 end

1208

1209 10’d60: 1210 begin

61 1211 addr_speech_60= c_addr_speech; 1212 c_out_speech= out_speech_60; 1213 end

1214

1215 10’d61: 1216 begin 1217 addr_speech_61= c_addr_speech; 1218 c_out_speech= out_speech_61; 1219 end

1220

1221 10’d62: 1222 begin 1223 addr_speech_62= c_addr_speech; 1224 c_out_speech= out_speech_62; 1225 end

1226

1227 10’d63: 1228 begin 1229 addr_speech_63= c_addr_speech; 1230 c_out_speech= out_speech_63; 1231 end

1232

1233 10’d64: 1234 begin 1235 addr_speech_64= c_addr_speech; 1236 c_out_speech= out_speech_64; 1237 end

1238

1239 10’d65: 1240 begin 1241 addr_speech_65= c_addr_speech; 1242 c_out_speech= out_speech_65; 1243 end

1244

1245 10’d66: 1246 begin 1247 addr_speech_66= c_addr_speech; 1248 c_out_speech= out_speech_66; 1249 end

1250

1251 10’d67: 1252 begin 1253 addr_speech_67= c_addr_speech; 1254 c_out_speech= out_speech_67; 1255 end

62 1256

1257 10’d68: 1258 begin 1259 addr_speech_68= c_addr_speech; 1260 c_out_speech= out_speech_68; 1261 end

1262

1263 10’d69: 1264 begin 1265 addr_speech_69= c_addr_speech; 1266 c_out_speech= out_speech_69; 1267 end

1268

1269 10’d70: 1270 begin 1271 addr_speech_70= c_addr_speech; 1272 c_out_speech= out_speech_70; 1273 end

1274

1275 10’d71: 1276 begin 1277 addr_speech_71= c_addr_speech; 1278 c_out_speech= out_speech_71; 1279 end

1280

1281 10’d72: 1282 begin 1283 addr_speech_72= c_addr_speech; 1284 c_out_speech= out_speech_72; 1285 end

1286

1287 10’d73: 1288 begin 1289 addr_speech_73= c_addr_speech; 1290 c_out_speech= out_speech_73; 1291 end

1292

1293 10’d74: 1294 begin 1295 addr_speech_74= c_addr_speech; 1296 c_out_speech= out_speech_74; 1297 end

1298

1299 10’d75: 1300 begin

63 1301 addr_speech_75= c_addr_speech; 1302 c_out_speech= out_speech_75; 1303 end

1304

1305 10’d76: 1306 begin 1307 addr_speech_76= c_addr_speech; 1308 c_out_speech= out_speech_76; 1309 end

1310

1311 10’d77: 1312 begin 1313 addr_speech_77= c_addr_speech; 1314 c_out_speech= out_speech_77; 1315 end

1316

1317 10’d78: 1318 begin 1319 addr_speech_78= c_addr_speech; 1320 c_out_speech= out_speech_78; 1321 end

1322

1323 10’d79: 1324 begin 1325 addr_speech_79= c_addr_speech; 1326 c_out_speech= out_speech_79; 1327 end

1328

1329 10’d80: 1330 begin 1331 addr_speech_80= c_addr_speech; 1332 c_out_speech= out_speech_80; 1333 end

1334

1335 10’d81: 1336 begin 1337 addr_speech_81= c_addr_speech; 1338 c_out_speech= out_speech_81; 1339 end

1340

1341 10’d82: 1342 begin 1343 addr_speech_82= c_addr_speech; 1344 c_out_speech= out_speech_82; 1345 end

64 1346

1347 10’d83: 1348 begin 1349 addr_speech_83= c_addr_speech; 1350 c_out_speech= out_speech_83; 1351 end

1352

1353 10’d84: 1354 begin 1355 addr_speech_84= c_addr_speech; 1356 c_out_speech= out_speech_84; 1357 end

1358

1359 10’d85: 1360 begin 1361 addr_speech_85= c_addr_speech; 1362 c_out_speech= out_speech_85; 1363 end

1364

1365 10’d86: 1366 begin 1367 addr_speech_86= c_addr_speech; 1368 c_out_speech= out_speech_86; 1369 end

1370

1371 10’d87: 1372 begin 1373 addr_speech_87= c_addr_speech; 1374 c_out_speech= out_speech_87; 1375 end

1376

1377 10’d88: 1378 begin 1379 addr_speech_88= c_addr_speech; 1380 c_out_speech= out_speech_88; 1381 end

1382

1383 10’d89: 1384 begin 1385 addr_speech_89= c_addr_speech; 1386 c_out_speech= out_speech_89; 1387 end

1388

1389 10’d90: 1390 begin

65 1391 addr_speech_90= c_addr_speech; 1392 c_out_speech= out_speech_90; 1393 end

1394

1395 10’d91: 1396 begin 1397 addr_speech_91= c_addr_speech; 1398 c_out_speech= out_speech_91; 1399 end

1400

1401 10’d92: 1402 begin 1403 addr_speech_92= c_addr_speech; 1404 c_out_speech= out_speech_92; 1405 end

1406

1407 10’d93: 1408 begin 1409 addr_speech_93= c_addr_speech; 1410 c_out_speech= out_speech_93; 1411 end

1412

1413 10’d94: 1414 begin 1415 addr_speech_94= c_addr_speech; 1416 c_out_speech= out_speech_94; 1417 end

1418

1419 10’d95: 1420 begin 1421 addr_speech_95= c_addr_speech; 1422 c_out_speech= out_speech_95; 1423 end

1424

1425 10’d96: 1426 begin 1427 addr_speech_96= c_addr_speech; 1428 c_out_speech= out_speech_96; 1429 end

1430

1431 10’d97: 1432 begin 1433 addr_speech_97= c_addr_speech; 1434 c_out_speech= out_speech_97; 1435 end

66 1436

1437 10’d98: 1438 begin 1439 addr_speech_98= c_addr_speech; 1440 c_out_speech= out_speech_98; 1441 end

1442

1443 10’d99: 1444 begin 1445 addr_speech_99= c_addr_speech; 1446 c_out_speech= out_speech_99; 1447 end

1448

1449 10’d100: 1450 begin 1451 addr_speech_100= c_addr_speech; 1452 c_out_speech= out_speech_100; 1453 end

1454

1455 10’d101: 1456 begin 1457 addr_speech_101= c_addr_speech; 1458 c_out_speech= out_speech_101; 1459 end

1460

1461 10’d102: 1462 begin 1463 addr_speech_102= c_addr_speech; 1464 c_out_speech= out_speech_102; 1465 end

1466

1467 10’d103: 1468 begin 1469 addr_speech_103= c_addr_speech; 1470 c_out_speech= out_speech_103; 1471 end

1472

1473 10’d104: 1474 begin 1475 addr_speech_104= c_addr_speech; 1476 c_out_speech= out_speech_104; 1477 end

1478

1479 10’d105: 1480 begin

67 1481 addr_speech_105= c_addr_speech; 1482 c_out_speech= out_speech_105; 1483 end

1484

1485 10’d106: 1486 begin 1487 addr_speech_106= c_addr_speech; 1488 c_out_speech= out_speech_106; 1489 end

1490

1491 10’d107: 1492 begin 1493 addr_speech_107= c_addr_speech; 1494 c_out_speech= out_speech_107; 1495 end

1496

1497 10’d108: 1498 begin 1499 addr_speech_108= c_addr_speech; 1500 c_out_speech= out_speech_108; 1501 end

1502

1503 10’d109: 1504 begin 1505 addr_speech_109= c_addr_speech; 1506 c_out_speech= out_speech_109; 1507 end

1508

1509 10’d110: 1510 begin 1511 addr_speech_110= c_addr_speech; 1512 c_out_speech= out_speech_110; 1513 end

1514

1515 10’d111: 1516 begin 1517 addr_speech_111= c_addr_speech; 1518 c_out_speech= out_speech_111; 1519 end

1520

1521 10’d112: 1522 begin 1523 addr_speech_112= c_addr_speech; 1524 c_out_speech= out_speech_112; 1525 end

68 1526

1527 10’d113: 1528 begin 1529 addr_speech_113= c_addr_speech; 1530 c_out_speech= out_speech_113; 1531 end

1532

1533 10’d114: 1534 begin 1535 addr_speech_114= c_addr_speech; 1536 c_out_speech= out_speech_114; 1537 end

1538

1539 10’d115: 1540 begin 1541 addr_speech_115= c_addr_speech; 1542 c_out_speech= out_speech_115; 1543 end

1544

1545 10’d116: 1546 begin 1547 addr_speech_116= c_addr_speech; 1548 c_out_speech= out_speech_116; 1549 end

1550

1551 10’d117: 1552 begin 1553 addr_speech_117= c_addr_speech; 1554 c_out_speech= out_speech_117; 1555 end

1556

1557 10’d118: 1558 begin 1559 addr_speech_118= c_addr_speech; 1560 c_out_speech= out_speech_118; 1561 end

1562

1563 10’d119: 1564 begin 1565 addr_speech_119= c_addr_speech; 1566 c_out_speech= out_speech_119; 1567 end

1568

1569 10’d120: 1570 begin

69 1571 addr_speech_120= c_addr_speech; 1572 c_out_speech= out_speech_120; 1573 end

1574

1575 10’d121: 1576 begin 1577 addr_speech_121= c_addr_speech; 1578 c_out_speech= out_speech_121; 1579 end

1580

1581 10’d122: 1582 begin 1583 addr_speech_122= c_addr_speech; 1584 c_out_speech= out_speech_122; 1585 end

1586

1587 10’d123: 1588 begin 1589 addr_speech_123= c_addr_speech; 1590 c_out_speech= out_speech_123; 1591 end

1592

1593 10’d124: 1594 begin 1595 addr_speech_124= c_addr_speech; 1596 c_out_speech= out_speech_124; 1597 end

1598

1599 10’d125: 1600 begin 1601 addr_speech_125= c_addr_speech; 1602 c_out_speech= out_speech_125; 1603 end

1604

1605 10’d126: 1606 begin 1607 addr_speech_126= c_addr_speech; 1608 c_out_speech= out_speech_126; 1609 end

1610

1611 10’d127: 1612 begin 1613 addr_speech_127= c_addr_speech; 1614 c_out_speech= out_speech_127; 1615 end

70 1616

1617 10’d128: 1618 begin 1619 addr_speech_128= c_addr_speech; 1620 c_out_speech= out_speech_128; 1621 end

1622

1623 10’d129: 1624 begin 1625 addr_speech_129= c_addr_speech; 1626 c_out_speech= out_speech_129; 1627 end

1628

1629 10’d130: 1630 begin 1631 addr_speech_130= c_addr_speech; 1632 c_out_speech= out_speech_130; 1633 end

1634

1635 10’d131: 1636 begin 1637 addr_speech_131= c_addr_speech; 1638 c_out_speech= out_speech_131; 1639 end

1640

1641 10’d132: 1642 begin 1643 addr_speech_132= c_addr_speech; 1644 c_out_speech= out_speech_132; 1645 end

1646

1647 10’d133: 1648 begin 1649 addr_speech_133= c_addr_speech; 1650 c_out_speech= out_speech_133; 1651 end

1652

1653 10’d134: 1654 begin 1655 addr_speech_134= c_addr_speech; 1656 c_out_speech= out_speech_134; 1657 end

1658

1659 10’d135: 1660 begin

71 1661 addr_speech_135= c_addr_speech; 1662 c_out_speech= out_speech_135; 1663 end

1664

1665 10’d136: 1666 begin 1667 addr_speech_136= c_addr_speech; 1668 c_out_speech= out_speech_136; 1669 end

1670

1671 10’d137: 1672 begin 1673 addr_speech_137= c_addr_speech; 1674 c_out_speech= out_speech_137; 1675 end

1676

1677 10’d138: 1678 begin 1679 addr_speech_138= c_addr_speech; 1680 c_out_speech= out_speech_138; 1681 end

1682

1683 10’d139: 1684 begin 1685 addr_speech_139= c_addr_speech; 1686 c_out_speech= out_speech_139; 1687 end

1688

1689 10’d140: 1690 begin 1691 addr_speech_140= c_addr_speech; 1692 c_out_speech= out_speech_140; 1693 end

1694

1695 10’d141: 1696 begin 1697 addr_speech_141= c_addr_speech; 1698 c_out_speech= out_speech_141; 1699 end

1700

1701 10’d142: 1702 begin 1703 addr_speech_142= c_addr_speech; 1704 c_out_speech= out_speech_142; 1705 end

72 1706

1707 10’d143: 1708 begin 1709 addr_speech_143= c_addr_speech; 1710 c_out_speech= out_speech_143; 1711 end

1712

1713 10’d144: 1714 begin 1715 addr_speech_144= c_addr_speech; 1716 c_out_speech= out_speech_144; 1717 end

1718

1719 10’d145: 1720 begin 1721 addr_speech_145= c_addr_speech; 1722 c_out_speech= out_speech_145; 1723 end

1724

1725 10’d146: 1726 begin 1727 addr_speech_146= c_addr_speech; 1728 c_out_speech= out_speech_146; 1729 end

1730

1731 10’d147: 1732 begin 1733 addr_speech_147= c_addr_speech; 1734 c_out_speech= out_speech_147; 1735 end

1736

1737 10’d148: 1738 begin 1739 addr_speech_148= c_addr_speech; 1740 c_out_speech= out_speech_148; 1741 end

1742

1743 10’d149: 1744 begin 1745 addr_speech_149= c_addr_speech; 1746 c_out_speech= out_speech_149; 1747 end

1748

1749 endcase

1750

73 1751 end

1752

1753 /*GET_CODEC_ONE_FRAME: 1754 begin

1755

1756 end

1757

1758 INCR_I: 1759 begin

1760

1761 end

1762

1763 DONE: 1764 begin

1765

1766 end*/

1767

1768 default: 1769 begin

1770

1771 end

1772

1773 endcase 1774 end

1775

1776

1777

1778 always@(posedge clk or negedge rst)// Determine outputs 1779 begin

1780

1781 if(rst == 1’b0) 1782 begin 1783 done_codec2 <= 1’b0; 1784 end

1785

1786 else 1787 begin 1788 case(STATE)

1789

1790 START: 1791 begin 1792 done_codec2 <= 1’b0; 1793 // clk_count <= 80’b0; 1794 end

1795

74 1796 INIT_FOR: 1797 begin 1798 i <= 10’d0; 1799 // clk_count <= clk_count+ 80’b1; 1800 end

1801

1802 CHECK_I: 1803 begin

1804

1805 end

1806

1807 START_CODEC_ONE_FRAME: 1808 begin 1809 //clk_count <= clk_count+ 80’b1; 1810 start_oneframe <= 1’b1;

1811

1812 if(i == 10’d0) 1813 begin 1814 in_mem_x <= 32’b0; 1815 in_mem_y <= 32’b0; 1816 in_prevf0 <= {16’d50,16’d0}; 1817 in_xq0 <= 32’b0; 1818 in_xq1 <= 32’b0; 1819 end 1820 else 1821 begin 1822 in_mem_x <= out_mem_x; 1823 in_mem_y <= out_mem_y; 1824 in_prevf0 <= out_prevf0; 1825 in_xq0 <= out_xq0; 1826 in_xq1 <= out_xq1; 1827 end

1828

1829 end

1830

1831 RUN_CODEC_ONE_FRAME: 1832 begin 1833 //clk_count <= clk_count+ 80’b1; 1834 start_oneframe <= 1’b0; 1835 end

1836

1837 GET_CODEC_ONE_FRAME: 1838 begin 1839 // clk_count <= clk_count+ 80’b1; 1840 case(i)

75 1841 10’d140: 1842 begin 1843 encoded_bits_0 <= c_encoded_bits; 1844 end 1845 10’d141: 1846 begin 1847 encoded_bits_1 <= c_encoded_bits; 1848 end 1849 10’d142: 1850 begin 1851 encoded_bits_2 <= c_encoded_bits; 1852 end 1853 10’d143: 1854 begin 1855 encoded_bits_3 <= c_encoded_bits;

1856

1857 end 1858 10’d144: 1859 begin 1860 encoded_bits_4 <= c_encoded_bits; 1861 end 1862 10’d145: 1863 begin 1864 encoded_bits_5 <= c_encoded_bits; 1865 end 1866 10’d146: 1867 begin 1868 encoded_bits_6 <= c_encoded_bits; 1869 end 1870 10’d147: 1871 begin 1872 encoded_bits_7 <= c_encoded_bits; 1873 end 1874 10’d148: 1875 begin 1876 encoded_bits_8 <= c_encoded_bits; 1877 end

1878

1879 10’d149: 1880 begin 1881 encoded_bits_9 <= c_encoded_bits; 1882 end

1883

1884 default: 1885 begin

76 1886 //encoded_bits_0 <= 48’b0; 1887 end

1888

1889 endcase

1890

1891 end

1892

1893 INCR_I: 1894 begin 1895 i <=i + 10’d1; 1896 //clk_count <= clk_count+ 80’b1; 1897 end

1898

1899 DONE: 1900 begin 1901 done_codec2 <= 1’b1; 1902 // clk_count <= clk_count; 1903 end

1904

1905 endcase 1906 end

1907

1908 end

1909

1910

1911 endmodule

B.2 CODEC2 encoder one frame mode2400.v

1 module CODEC2_encoder_one_frame_mode2400(start_oneframe,clk, rst, 2 in_mex_x, in_mem_y, in_prevf0, in_xq0, in_xq1, 3 out_speech,read_c2_sn_out,out_mem_fir,out_sq,

5 // output 6 out_mem_x,out_mem_y,out_prevf0, out_xq0, out_xq1, 7 encoded_bits, 8 addr_speech,addr_sn,write_c2_sn, 9 re_c2_sn,we_c2_sn, 10 addr_mem_fir, in_mem_fir,read_fir,write_fir, 11 addr_nlp_sq, in_sq,read_sq,write_sq, 12 done_oneframe,

14 c_encode_model_wo,c_pitch1,c_pitch2, c_cmax1, c_cmax2 15 );

77 16

18 //------19 //-- Input/Output Declarations-- 20 //------21 parameterN = 32; 22 parameterQ = 16; 23 parameterBITS_WIDTH = 48;

25 parameter N1 = 80; 26 parameter Q1 = 16;

28 input clk,rst,start_oneframe; 29 input[N1-1:0] in_mex_x,in_mem_y; 30 input[N-1:0] in_prevf0,in_xq0, in_xq1; 31 input[N-1:0] out_speech,read_c2_sn_out; 32 input[N1-1:0] out_mem_fir,out_sq;

36 output reg[BITS_WIDTH-1: 0] encoded_bits;

38 output reg[N1-1:0] out_mem_x,out_mem_y; 39 output reg[N-1:0] out_prevf0, out_xq0, out_xq1; 40 output reg [9:0] addr_speech, addr_sn, addr_mem_fir, addr_nlp_sq; 41 output reg[N-1:0] write_c2_sn; 42 output reg[N1-1:0] in_mem_fir, in_sq;

44 output reg [9:0] c_cmax1, c_cmax2;

46 output reg done_oneframe,re_c2_sn, we_c2_sn, read_fir, 47 write_fir, read_sq,write_sq;

49 reg[N-1:0] check_sum;

51 reg[N-1:0] c_w0_1,c_w0_2,c_w0,c_w1;

53 reg[N-1:0] check_pitch1, check_best_fo1, check_pitch2, check_best_fo2;

55 reg[N-1:0] c_e,ch_lsp;

57 output reg[N-1:0] c_encode_model_wo,c_pitch1,c_pitch2;

59 reg[N-1:0] c_sn;

78 61

63 /* module CODEC2_encoder_one_frame_mode2400( start_oneframe,clk, rst,

65 out_mem_x,out_mem_y,out_prevf0, out_xq0, out_xq1, 66 encoded_bits,

68 done_oneframe,c_encode_model_wo,c_pitch1,c_pitch2,c_cmax1, c_cmax2,c_e,c_sn

70 );

72 //------73 //-- Input/Output Declarations-- 74 //------75 parameterN= 32; 76 parameterQ= 16; 77 parameterBITS_WIDTH= 48;

79 parameter N1= 80; 80 parameter Q1= 16;

82 input clk,rst,start_oneframe; 83 reg[N-1:0] in_prevf0,in_xq0, in_xq1;

85 output reg[BITS_WIDTH-1: 0] encoded_bits;

87 output reg[N1-1:0] out_mem_x,out_mem_y; 88 output reg[N-1:0] out_prevf0, out_xq0, out_xq1;

90 output reg [9:0] c_cmax1, c_cmax2;

92 output reg done_oneframe;

94 reg[N-1:0] check_sum;

96 reg[N-1:0] c_w0_1,c_w0_2,c_w0,c_w1;

98 reg[N-1:0] check_pitch1, check_pitch2;

100 output reg[N-1:0] c_encode_model_wo,c_pitch1,c_pitch2;

101

102 output reg[N-1:0] c_e,c_sn;

103

104

105

79 106 reg [9:0] addr_speech; 107 wire[N-1:0] out_speech; 108 RAM_speech_0 r_speech_0(addr_speech,clk,,1,0,out_speech);

109

110 //------RAM_speech for one_frame- 320 size------111 reg [9:0] addr_sn; 112 reg[N-1:0] write_c2_sn; 113 reg re_c2_sn,we_c2_sn; 114 wire[N-1:0] read_c2_sn_out;

115

116 RAM_c2_sn_test_nlp c2_sn(addr_sn,clk,write_c2_sn, 117 re_c2_sn,we_c2_sn,read_c2_sn_out); 118 //------RAM_nlp_mem_fir- size 48------119 reg [9:0] addr_mem_fir; 120 reg[N1-1:0] in_mem_fir; 121 reg read_fir, write_fir; 122 wire[N1-1:0] out_mem_fir;

123

124 RAM_nlp_mem_fir_80 mem_fir(addr_mem_fir,clk, 125 in_mem_fir,read_fir,write_fir,out_mem_fir); 126 //------RAM_nlp_sq- size 320------127 reg [9:0] addr_nlp_sq; 128 reg[N1-1:0] in_sq; 129 reg read_sq,write_sq; 130 wire[N1-1:0] out_sq;

131

132 RAM_nlp_sq_80 nlp_sq(addr_nlp_sq,clk,in_sq, 133 read_sq,write_sq,out_sq);*/

134

135 //------136 //-- State& Reg Declarations-- 137 //------

138

139 parameterSTART =7’d0, 140 START_AOF1 =7’d1, 141 RUN_AOF1 =7’d2, 142 START_AOF2 =7’d3, 143 RUN_AOF2 =7’d4, 144 DONE =7’d5, 145 INIT_FOR_2 =7’d6, 146 CHECK_FOR2 =7’d7, 147 READ_SN2 =7’d8, 148 SET_DELAY_3 =7’d9, 149 SET_DELAY_4 =7’d10, 150 READ_DATA_SN2 =7’d11,

80 151 INCR_FOR2 =7’d12, 152 GET_AOF1 =7’d13, 153 AA_SET_ADDR =7’d14, 154 AA_SET_ADDR1 =7’d15, 155 AA_SET_ADDR2 =7’d16, 156 AA_SET_ADDR_GET =7’d17, 157 INIT_FOR_4 =7’d18, 158 CHECK_FOR_4 =7’d19, 159 READ_SN4 =7’d20, 160 SET_DELAY_5 =7’d21, 161 SET_DELAY_6 =7’d22, 162 READ_DATA_SN4 =7’d23, 163 INCR_FOR_4 =7’d24, 164 GET_AOF2 =7’d25, 165 START_SPEECH =7’d26, 166 RUN_SPEECH =7’d27, 167 GET_SPEECH =7’d28, 168 START_ENCODEWOE =7’d29, 169 RUN_ENCODEWOE =7’d30, 170 GET_ENCODEWOE =7’d31, 171 INIT_FOR_LSP =7’d32, 172 CHECK_LSP =7’d33, 173 SET_DATA_LSP =7’d34, 174 INCR_LSP =7’d35, 175 START_ELSP1 =7’d36, 176 SET_INDEX =7’d37, 177 RUN_ELSP =7’d38, 178 GET_ELSP =7’d39, 179 INCR_INDEX =7’d40, 180 CHECK_INDEX =7’d41, 181 INDEX_TO_GRAY =7’d42, 182 SET_ENCODED_BITS =7’d43, 183 INIT_FOR_1 =7’d44, 184 CHECK_FOR1 =7’d45, 185 READ_SN1 =7’d46, 186 SET_DELAY_1 =7’d47, 187 SET_DELAY_2 =7’d48, 188 READ_DATA_SN1 =7’d49, 189 SET_ADDR_SN1 =7’d50, 190 WRITE_SN1 =7’d51, 191 INCR_FOR1 =7’d52, 192 INIT_FOR_3 =7’d53, 193 CHECK_FOR3 =7’d54, 194 READ_SN3 =7’d55, 195 SET_DELAY_7 =7’d56,

81 196 SET_DELAY_8 =7’d57, 197 READ_DATA_SN3 =7’d58, 198 SET_ADDR_SN3 =7’d59, 199 WRITE_SN3 =7’d60, 200 INCR_FOR3 =7’d61;

201

202

203 reg [6:0]STATE,NEXT_STATE;

204

205 parameter [9:0]N_SAMP = 10’d80, 206 M_PITCH = 10’d320; 207 //------208 //-- Module Instantiations-- 209 //------210 reg [9:0]i,j; 211 reg[N-1:0] sn_data;

212

213

214

215 reg[N-1:0] a1_in1; 216 reg[N-1:0] a1_in2; 217 wire[N-1:0] a1_out;

218

219 qadd#(Q,N) adder1(a1_in1,a1_in2,a1_out);

220

221

222

223

224 /*------analyse_one_frame------*/

225

226 reg startaof; 227 reg[N1-1:0] aof_mem_x_in,aof_mem_y_in, aof_out_mem_fir, aof_out_sq; 228 reg[N-1:0] aof_in_prev_f0, aof_out_sn; 229 wire[N1-1:0] aof_mem_x_out,aof_mem_y_out,aof_in_mem_fir,aof_in_sq; 230 wire[N-1:0] aof_out_prev_f0,out_best_f0,aof_w0_out,aof_nlp_pitch; 231 wire [9:0] aof_addr_sn,aof_addr_mem_fir,aof_addr_nlp_sq; 232 wire voiced_bit,doneaof,aof_read_fir,aof_write_fir,aof_read_sq,aof_write_sq; 233 wire [9:0] c_cmax; 234 wire[N-1:0] aof_check_i; 235 wire[N1-1:0] c_outreal,aof_check_in_real,aof_check_in_imag;

236

237 analyse_one_frame aof( startaof,clk,rst, 238 /*--- input------*/ 239 aof_mem_x_in,aof_mem_y_in,aof_in_prev_f0,aof_out_sn, 240 aof_out_mem_fir,aof_out_sq,

82 241 /*------*/ 242 /*--- output------*/ 243 aof_mem_x_out,aof_mem_y_out,aof_out_prev_f0,out_best_f0, 244 aof_w0_out,voiced_bit,aof_addr_sn, 245 aof_addr_mem_fir,aof_in_mem_fir,aof_nlp_pitch,aof_read_fir,aof_write_fir, 246 aof_addr_nlp_sq,aof_in_sq,aof_read_sq,aof_write_sq, 247 /*------*/ 248 doneaof,c_cmax,aof_check_i// c_outreal, aof_check_in_real,aof_check_in_imag

249

250 );

251

252 wire[N-1:0] aof_c_w0,aof_c_w1; 253 reg aof_voiced1;

254

255 reg [9:0] i1,j1;

256

257 /*------speech_to_uq_lsps------*/ 258 reg startspeech; 259 reg[N-1:0] s_out_sn; 260 wire[N-1:0] E_speech,lsp0,lsp1,lsp2,lsp3,lsp4,lsp5,lsp6,lsp7, 261 lsp8,lsp9,check_corr; 262 wire [9:0] s_addr_sn; wire donespeech;

263

264 speech_to_uq_lsps_modified speech_module(startspeech,clk,rst,s_out_sn, 265 E_speech,lsp0,lsp1,lsp2,lsp3,lsp4,lsp5,lsp6,lsp7,lsp8,lsp9,s_addr_sn, 266 donespeech);

267

268

269 /*------encode_WoE------*/

270

271 reg startewoe; 272 reg[N-1:0] encode_model_wo,encode_in_e; 273 reg[N-1:0] xq0, xq1; 274 wire[N-1:0] encode_out_n1,e_out_xq0,e_out_xq1; 275 wire doneewoe;

276

277

278 encode_WoE encode_module(startewoe,clk,rst,encode_model_wo, 279 encode_in_e,xq0,xq1,e_out_xq0,e_out_xq1,encode_out_n1,doneewoe); 280 reg [3:0] lsp; 281 reg [7:0] toGray;

282

283 /*------encode_lsps_scalar module------*/

284

285 reg [3:0] clsp0,clsp1,clsp2,clsp3,clsp4,clsp5,clsp6,clsp7,clsp8,clsp9;

83 286 reg start_elsp; 287 reg [3:0] in_index; 288 reg[N-1:0] in_lsp0,in_lsp1,in_lsp2,in_lsp3,in_lsp4,in_lsp5, 289 in_lsp6,in_lsp7,in_lsp8,in_lsp9; 290 wire [3:0] out_index; 291 wire done_elsp;

292

293 encode_lsp_scalar_index e_lsp_scalar(start_elsp,clk,rst,in_index, 294 in_lsp0,in_lsp1,in_lsp2,in_lsp3,in_lsp4,in_lsp5,in_lsp6,in_lsp7, 295 in_lsp8,in_lsp9,out_index, 296 done_elsp);

297

298

299 //------300 //-- Begin Declarations& Coding-- 301 //------

302

303 always@(posedge clk or negedge rst)// DetermineSTATE 304 begin

305

306 if(rst == 1’b0) 307 STATE <=START; 308 else 309 STATE <=NEXT_STATE;

310

311 end

312

313

314 always@(*) 315 begin 316 case(STATE)

317

318 /*START: 319 begin

320

321 end*/

322

323 //for(i=0;iSn[i]= c2->Sn[i+n_samp]; 325 //for(i=0;iSn[i+m_pitch-n_samp]= speech[i];

327

328 /* INIT_FOR_1: 329 begin

330

84 331 end

332

333 CHECK_FOR1: 334 begin

335

336 end*/

337

338 READ_SN1: 339 begin 340 addr_sn=i+N_SAMP; 341 re_c2_sn =1’b1; 342 we_c2_sn =1’b0; 343 end

344

345 SET_DELAY_1: 346 begin 347 addr_sn=i+N_SAMP; 348 re_c2_sn =1’b1; 349 we_c2_sn =1’b0; 350 end

351

352 SET_DELAY_2: 353 begin 354 addr_sn=i+N_SAMP; 355 re_c2_sn =1’b1; 356 we_c2_sn =1’b0; 357 end

358

359 READ_DATA_SN1: 360 begin 361 sn_data= read_c2_sn_out; 362 addr_sn=i+N_SAMP; 363 re_c2_sn =1’b1; 364 we_c2_sn =1’b0; 365 end

366

367 SET_ADDR_SN1: 368 begin 369 addr_sn=i; 370 re_c2_sn =1’d0; 371 we_c2_sn =1’d1; 372 end

373

374 WRITE_SN1: 375 begin

85 376 write_c2_sn= sn_data; 377 addr_sn=i; 378 re_c2_sn =1’d0; 379 we_c2_sn =1’d1; 380 end

381

382 /* INCR_FOR1: 383 begin

384

385 end*/

386

387

388 /*INIT_FOR_2: 389 begin

390

391 end

392

393

394 CHECK_FOR2: 395 begin

396

397 end*/

398

399 READ_SN2: 400 begin 401 addr_speech= i1; 402 addr_sn= i1 + 10’d240; 403 re_c2_sn =1’b0; 404 we_c2_sn =1’b1;

405

406 end

407

408 SET_DELAY_3: 409 begin 410 addr_speech= i1; 411 addr_sn= i1 + 10’d240; 412 re_c2_sn =1’b0; 413 we_c2_sn =1’b1;

414

415 end

416

417 SET_DELAY_4: 418 begin 419 addr_speech= i1; 420 addr_sn= i1 + 10’d240;

86 421 re_c2_sn =1’b0; 422 we_c2_sn =1’b1;

423

424 end

425

426 READ_DATA_SN2: 427 begin 428 //sn_data= out_speech; 429 write_c2_sn= out_speech; 430 addr_speech= i1; 431 addr_sn= i1 + 10’d240; 432 re_c2_sn =1’b0; 433 we_c2_sn =1’b1;

434

435 end

436

437 /* INCR_FOR2: 438 begin

439

440 end*/

441

442 START_AOF1: 443 begin

444

445 we_c2_sn =1’b0; 446 re_c2_sn =1’b1;

447

448 end

449

450 RUN_AOF1: 451 begin

452

453 aof_out_sn= read_c2_sn_out; 454 addr_sn= aof_addr_sn; 455 we_c2_sn =1’b0; 456 re_c2_sn =1’b1;

457

458 addr_mem_fir= aof_addr_mem_fir; 459 aof_out_mem_fir= out_mem_fir; 460 in_mem_fir= aof_in_mem_fir; 461 read_fir= aof_read_fir; 462 write_fir= aof_write_fir;

463

464 addr_nlp_sq= aof_addr_nlp_sq; 465 aof_out_sq= out_sq;

87 466 in_sq= aof_in_sq; 467 read_sq= aof_read_sq; 468 write_sq= aof_write_sq; 469 end

470

471 /* GET_AOF1: 472 begin

473

474 end*/

475

476 /* INIT_FOR_3: 477 begin

478

479 end

480

481 CHECK_FOR3: 482 begin

483

484 end*/

485

486 READ_SN3: 487 begin 488 addr_sn=j+N_SAMP; 489 re_c2_sn =1’b1; 490 we_c2_sn =1’b0; 491 end

492

493 SET_DELAY_5: 494 begin 495 addr_sn=j+N_SAMP; 496 re_c2_sn =1’b1; 497 we_c2_sn =1’b0; 498 end

499

500 SET_DELAY_6: 501 begin 502 addr_sn=j+N_SAMP; 503 re_c2_sn =1’b1; 504 we_c2_sn =1’b0; 505 end

506

507 READ_DATA_SN3: 508 begin 509 sn_data= read_c2_sn_out; 510 addr_sn=j+N_SAMP;

88 511 re_c2_sn =1’b1; 512 we_c2_sn =1’b0; 513 end

514

515 SET_ADDR_SN3: 516 begin 517 addr_sn=j; 518 re_c2_sn =1’d0; 519 we_c2_sn =1’d1; 520 end

521

522 WRITE_SN3: 523 begin 524 write_c2_sn= sn_data; 525 addr_sn=j; 526 re_c2_sn =1’d0; 527 we_c2_sn =1’d1; 528 end

529

530 /* INIT_FOR_4: 531 begin

532

533 end

534

535 CHECK_FOR_4: 536 begin

537

538 end*/

539

540 READ_SN4: 541 begin 542 addr_speech= j1; 543 addr_sn= j1 + 10’d160; 544 re_c2_sn =1’b0; 545 we_c2_sn =1’b1; 546 end

547

548 SET_DELAY_7: 549 begin 550 addr_speech= j1; 551 addr_sn= j1 + 10’d160; 552 re_c2_sn =1’b0; 553 we_c2_sn =1’b1; 554 end

555

89 556 SET_DELAY_8: 557 begin 558 addr_speech= j1; 559 addr_sn= j1 + 10’d160; 560 re_c2_sn =1’b0; 561 we_c2_sn =1’b1; 562 end

563

564 READ_DATA_SN4: 565 begin 566 write_c2_sn= out_speech; 567 addr_speech= j1; 568 addr_sn= j1 + 10’d160; 569 re_c2_sn =1’b0; 570 we_c2_sn =1’b1; 571 end

572

573 /* INCR_FOR_4: 574 begin

575

576 end*/

577

578 START_AOF2: 579 begin 580 we_c2_sn =1’b0; 581 re_c2_sn =1’b1; 582 end

583

584 RUN_AOF2: 585 begin 586 aof_out_sn= read_c2_sn_out; 587 addr_sn= aof_addr_sn; 588 we_c2_sn =1’b0; 589 re_c2_sn =1’b1;

590

591 addr_mem_fir= aof_addr_mem_fir; 592 aof_out_mem_fir= out_mem_fir; 593 in_mem_fir= aof_in_mem_fir; 594 read_fir= aof_read_fir; 595 write_fir= aof_write_fir;

596

597 addr_nlp_sq= aof_addr_nlp_sq; 598 aof_out_sq= out_sq; 599 in_sq= aof_in_sq; 600 read_sq= aof_read_sq;

90 601 write_sq= aof_write_sq; 602 end

603

604 /* GET_AOF2: 605 begin

606

607 end*/

608

609

610 START_SPEECH: 611 begin 612 we_c2_sn =1’b0; 613 re_c2_sn =1’b1;

614

615 end

616

617 RUN_SPEECH: 618 begin 619 s_out_sn= read_c2_sn_out; 620 addr_sn= s_addr_sn; 621 we_c2_sn =1’b0; 622 re_c2_sn =1’b1;

623

624 end

625

626 /* 627 GET_SPEECH: 628 begin

629

630 end*/

631

632

633 AA_SET_ADDR: 634 begin 635 addr_sn = 10’d248; 636 we_c2_sn =1’b0; 637 re_c2_sn =1’b1;

638

639 end

640

641 AA_SET_ADDR1: 642 begin 643 addr_sn = 10’d248; 644 we_c2_sn =1’b0; 645 re_c2_sn =1’b1;

91 646

647 end

648

649 AA_SET_ADDR2: 650 begin 651 addr_sn = 10’d248; 652 we_c2_sn =1’b0; 653 re_c2_sn =1’b1;

654

655 end

656

657 AA_SET_ADDR_GET: 658 begin 659 addr_sn = 10’d248; 660 we_c2_sn =1’b0; 661 re_c2_sn =1’b1;

662

663 end

664

665 default: 666 begin 667 addr_sn = 10’d0; 668 re_c2_sn = 10’d0; 669 we_c2_sn = 10’d0; 670 addr_speech = 10’d0; 671 //sn_data= 32’b0; 672 //write_c2_sn= 32’b0;

673

674 end

675

676 endcase

677

678

679

680 end

681

682

683 always@(*)// DetermineNEXT_STATE 684 begin 685 case(STATE)

686

687 START: 688 begin 689 if(start_oneframe) 690 begin

92 691 NEXT_STATE= INIT_FOR_1; 692 end 693 else 694 begin 695 NEXT_STATE=START; 696 end

697

698 end

699

700 INIT_FOR_1: 701 begin 702 NEXT_STATE= CHECK_FOR1; 703 end

704

705 CHECK_FOR1: 706 begin 707 if(i

716

717 READ_SN1: 718 begin 719 NEXT_STATE= SET_DELAY_1; 720 //addr_sn=i+N_SAMP; 721 end

722

723 SET_DELAY_1: 724 begin 725 NEXT_STATE= SET_DELAY_2; 726 end

727

728 SET_DELAY_2: 729 begin 730 NEXT_STATE= READ_DATA_SN1; 731 end

732

733 READ_DATA_SN1: 734 begin 735 NEXT_STATE= SET_ADDR_SN1;

93 736 end

737

738 SET_ADDR_SN1: 739 begin 740 NEXT_STATE= WRITE_SN1; 741 end

742

743 WRITE_SN1: 744 begin 745 NEXT_STATE= INCR_FOR1; 746 end

747

748 INCR_FOR1: 749 begin 750 NEXT_STATE= CHECK_FOR1; 751 end

752

753 /* for(i=0;iSn[i]= c2->Sn[i+n_samp]; 755 for(i=0;iSn[i+m_pitch-n_samp]= speech[i];*/

757

758 INIT_FOR_2: 759 begin 760 NEXT_STATE= CHECK_FOR2; 761 end

762

763 CHECK_FOR2: 764 begin 765 if(i1

774

775 READ_SN2: 776 begin 777 NEXT_STATE= SET_DELAY_3; 778 end

779

780 SET_DELAY_3:

94 781 begin 782 NEXT_STATE= SET_DELAY_4; 783 end

784

785 SET_DELAY_4: 786 begin 787 NEXT_STATE= READ_DATA_SN2; 788 end

789

790 READ_DATA_SN2: 791 begin 792 NEXT_STATE= INCR_FOR2;//SET_ADDR_SN2; 793 end

794

795

796 INCR_FOR2: 797 begin 798 NEXT_STATE= CHECK_FOR2; 799 end

800

801 START_AOF1: 802 begin 803 NEXT_STATE= RUN_AOF1; 804 end

805

806 RUN_AOF1: 807 begin 808 if(doneaof) 809 begin 810 NEXT_STATE= GET_AOF1; 811 end 812 else 813 begin 814 NEXT_STATE= RUN_AOF1; 815 end 816 end

817

818 GET_AOF1: 819 begin 820 NEXT_STATE= INIT_FOR_3;///DONE; 821 end

822

823 /* for(i=0;iSn[i]= c2->Sn[i+n_samp]; 825 for(i=0;i

95 826 c2->Sn[i+m_pitch-n_samp]= speech[i+80];*/

827

828 INIT_FOR_3: 829 begin 830 NEXT_STATE= CHECK_FOR3; 831 end

832

833 CHECK_FOR3: 834 begin 835 if(j < 10’d160) 836 begin 837 NEXT_STATE= READ_SN3; 838 end 839 else 840 begin 841 NEXT_STATE= INIT_FOR_4; 842 end 843 end

844

845 READ_SN3: 846 begin 847 NEXT_STATE= SET_DELAY_5; 848 end

849

850 SET_DELAY_5: 851 begin 852 NEXT_STATE= SET_DELAY_6; 853 end

854

855 SET_DELAY_6: 856 begin 857 NEXT_STATE= READ_DATA_SN3; 858 end

859

860 READ_DATA_SN3: 861 begin 862 NEXT_STATE= SET_ADDR_SN3; 863 end

864

865 SET_ADDR_SN3: 866 begin 867 NEXT_STATE= WRITE_SN3; 868 end

869

870 WRITE_SN3:

96 871 begin 872 NEXT_STATE= INCR_FOR3; 873 end

874

875 INCR_FOR3: 876 begin 877 NEXT_STATE= CHECK_FOR3; 878 end

879

880 INIT_FOR_4: 881 begin 882 NEXT_STATE= CHECK_FOR_4; 883 end

884

885 CHECK_FOR_4: 886 begin 887 if(j1 < 10’d160) 888 begin 889 NEXT_STATE= READ_SN4; 890 end 891 else 892 begin 893 NEXT_STATE= START_AOF2;//AA_SET_ADDR;// 894 end 895 end

896

897 READ_SN4: 898 begin 899 NEXT_STATE= SET_DELAY_7; 900 end

901

902 SET_DELAY_7: 903 begin 904 NEXT_STATE= SET_DELAY_8; 905 end

906

907 SET_DELAY_8: 908 begin 909 NEXT_STATE= READ_DATA_SN4; 910 end

911

912 READ_DATA_SN4: 913 begin 914 NEXT_STATE= INCR_FOR_4;//SET_ADDR_SN2; 915 end

97 916

917 INCR_FOR_4: 918 begin 919 NEXT_STATE= CHECK_FOR_4; 920 end

921

922 START_AOF2: 923 begin 924 NEXT_STATE= RUN_AOF2; 925 end

926

927 RUN_AOF2: 928 begin 929 if(doneaof) 930 begin 931 NEXT_STATE= GET_AOF2; 932 end 933 else 934 begin 935 NEXT_STATE= RUN_AOF2; 936 end

937

938 end

939

940 GET_AOF2: 941 begin 942 NEXT_STATE=START_SPEECH; 943 end

944

945 START_SPEECH: 946 begin 947 NEXT_STATE=RUN_SPEECH; 948 end

949

950 RUN_SPEECH: 951 begin 952 if(donespeech) 953 begin 954 NEXT_STATE=GET_SPEECH; 955 end 956 else 957 begin 958 NEXT_STATE=RUN_SPEECH; 959 end

960

98 961 end

962

963 GET_SPEECH: 964 begin 965 NEXT_STATE=START_ENCODEWOE; 966 end

967

968 START_ENCODEWOE: 969 begin 970 NEXT_STATE=RUN_ENCODEWOE; 971 end

972

973 RUN_ENCODEWOE: 974 begin 975 if(doneewoe) 976 begin 977 NEXT_STATE=GET_ENCODEWOE; 978 end 979 else 980 begin 981 NEXT_STATE=RUN_ENCODEWOE; 982 end 983 end

984

985 GET_ENCODEWOE: 986 begin 987 NEXT_STATE=INIT_FOR_LSP; 988 end

989

990 INIT_FOR_LSP: 991 begin 992 NEXT_STATE=CHECK_LSP; 993 end

994

995 CHECK_LSP: 996 begin 997 if(lsp <4’d10) 998 begin 999 NEXT_STATE=SET_DATA_LSP; 1000 end 1001 else 1002 begin 1003 NEXT_STATE= START_ELSP1; 1004 end 1005 end

99 1006

1007 SET_DATA_LSP: 1008 begin 1009 NEXT_STATE=INCR_LSP; 1010 end

1011

1012 INCR_LSP: 1013 begin 1014 NEXT_STATE=CHECK_LSP; 1015 end

1016

1017 START_ELSP1: 1018 begin 1019 NEXT_STATE=SET_INDEX; 1020 end

1021

1022 SET_INDEX: 1023 begin 1024 NEXT_STATE=RUN_ELSP; 1025 end

1026

1027 RUN_ELSP: 1028 begin 1029 if(done_elsp) 1030 begin 1031 NEXT_STATE=GET_ELSP; 1032 end 1033 else 1034 begin 1035 NEXT_STATE=RUN_ELSP; 1036 end 1037 end

1038

1039 GET_ELSP: 1040 begin 1041 NEXT_STATE=INCR_INDEX; 1042 end

1043

1044 INCR_INDEX: 1045 begin 1046 NEXT_STATE=CHECK_INDEX; 1047 end

1048

1049 CHECK_INDEX: 1050 begin

100 1051 if(in_index <4’d10) 1052 begin 1053 NEXT_STATE=SET_INDEX; 1054 end 1055 else 1056 begin 1057 NEXT_STATE=INDEX_TO_GRAY; 1058 end

1059

1060 end

1061

1062 INDEX_TO_GRAY: 1063 begin 1064 NEXT_STATE=SET_ENCODED_BITS; 1065 end

1066

1067 SET_ENCODED_BITS: 1068 begin 1069 NEXT_STATE=DONE; 1070 end

1071

1072 AA_SET_ADDR: 1073 begin 1074 NEXT_STATE= AA_SET_ADDR1; 1075 end

1076

1077 AA_SET_ADDR1: 1078 begin 1079 NEXT_STATE= AA_SET_ADDR2; 1080 end

1081

1082 AA_SET_ADDR2: 1083 begin 1084 NEXT_STATE=AA_SET_ADDR_GET; 1085 end

1086

1087 AA_SET_ADDR_GET: 1088 begin 1089 NEXT_STATE=DONE; 1090 end

1091

1092 DONE: 1093 begin 1094 NEXT_STATE=START; 1095 end

101 1096

1097 default: 1098 begin 1099 NEXT_STATE=DONE; 1100 end

1101

1102 endcase 1103 end

1104

1105

1106 always@(posedge clk or negedge rst)// Determine outputs 1107 begin

1108

1109 if(rst == 1’b0) 1110 begin 1111 done_oneframe <= 1’b0;

1112

1113 end

1114

1115 else 1116 begin 1117 case(STATE)

1118

1119 START: 1120 begin 1121 done_oneframe <= 1’b0;

1122

1123 //done_elsp <= 1’b0; 1124 end

1125

1126 /* for(i=0;iSn[i]= c2->Sn[i+n_samp]; 1128 for(i=0;iSn[i+m_pitch-n_samp]= speech[i];*/

1130

1131 INIT_FOR_1: 1132 begin 1133 i <= 10’d0; 1134 encoded_bits <= 48’d0; 1135 check_sum <= 32’b0; 1136 end

1137

1138 CHECK_FOR1: 1139 begin

1140

102 1141 end

1142

1143 READ_SN1: 1144 begin 1145 //addr_sn <=i+N_SAMP; 1146 //re_c2_sn <= 1’b1; 1147 //we_c2_sn <= 1’b0; 1148 end

1149

1150 SET_DELAY_1: 1151 begin

1152

1153 end

1154

1155 SET_DELAY_2: 1156 begin

1157

1158 end

1159

1160 READ_DATA_SN1: 1161 begin 1162 //sn_data <= read_c2_sn_out; 1163 end

1164

1165 SET_ADDR_SN1: 1166 begin 1167 //addr_sn <=i; 1168 //re_c2_sn <= 1’d0; 1169 //we_c2_sn <= 1’d1; 1170 end

1171

1172 WRITE_SN1: 1173 begin 1174 //write_c2_sn <= sn_data;

1175

1176 end

1177

1178 INCR_FOR1: 1179 begin 1180 i <=i + 10’d1; 1181 end

1182

1183

1184 INIT_FOR_2: 1185 begin

103 1186 i1 <= 10’d0; 1187 end

1188

1189

1190 CHECK_FOR2: 1191 begin

1192

1193 end

1194

1195 READ_SN2: 1196 begin 1197 //addr_speech <=i; 1198 //re_c2_sn <= 1’b0; 1199 //we_c2_sn <= 1’b1; 1200 end

1201

1202 SET_DELAY_3: 1203 begin

1204

1205 end

1206

1207 SET_DELAY_4: 1208 begin

1209

1210 end

1211

1212 READ_DATA_SN2: 1213 begin 1214 //sn_data <= out_speech;

1215

1216 end

1217

1218

1219 INCR_FOR2: 1220 begin 1221 i1 <= i1 + 10’d1; 1222 end

1223

1224

1225 START_AOF1: 1226 begin 1227 startaof <= 1’b1;

1228

1229 /* aof_mem_x_in <= 32’b0; 1230 aof_mem_y_in <= 32’b0;

104 1231 aof_in_prev_f0 <= {16’d50,16’d0};*/

1232

1233 aof_mem_x_in <= in_mex_x; 1234 aof_mem_y_in <= in_mem_y; 1235 aof_in_prev_f0 <= in_prevf0;

1236

1237 end

1238

1239 RUN_AOF1: 1240 begin 1241 startaof <= 1’b0; 1242 end

1243

1244 GET_AOF1: 1245 begin

1246

1247 aof_voiced1 <= voiced_bit; 1248 c_w0_1 <= aof_w0_out;

1249

1250 check_pitch1 <= aof_nlp_pitch; 1251 c_cmax1 <= c_cmax;

1252

1253 //check_sum <= aof_w0_out;

1254

1255 c_pitch1 <= aof_nlp_pitch; 1256 c_encode_model_wo <= aof_w0_out; 1257 //c_pitch2 <= aof_check_i;

1258

1259 //out_mem_x <= aof_mem_x_out; 1260 //out_mem_y <= aof_mem_y_out; 1261 //out_prevf0 <= aof_out_prev_f0;

1262

1263

1264

1265

1266

1267 end

1268

1269 INIT_FOR_3: 1270 begin 1271 j <= 10’d0; 1272 end

1273

1274 CHECK_FOR3: 1275 begin

105 1276

1277 end

1278

1279 READ_SN3: 1280 begin 1281 // addr_sn <=i+N_SAMP; 1282 // re_c2_sn <= 1’b1; 1283 // we_c2_sn <= 1’b0; 1284 end

1285

1286 SET_DELAY_5: 1287 begin

1288

1289 end

1290

1291 SET_DELAY_6: 1292 begin

1293

1294 end

1295

1296 READ_DATA_SN3: 1297 begin 1298 // sn_data <= read_c2_sn_out; 1299 end

1300

1301 SET_ADDR_SN3: 1302 begin 1303 // addr_sn <=i; 1304 // re_c2_sn <= 1’d0; 1305 // we_c2_sn <= 1’d1; 1306 end

1307

1308 WRITE_SN3: 1309 begin 1310 // write_c2_sn <= sn_data; 1311 end

1312

1313 INCR_FOR3: 1314 begin 1315 j <=j + 10’d1; 1316 end

1317

1318 INIT_FOR_4: 1319 begin 1320 j1 <= 10’d0;

106 1321 end

1322

1323 CHECK_FOR_4: 1324 begin

1325

1326 end

1327

1328 READ_SN4: 1329 begin

1330

1331 end

1332

1333 SET_DELAY_7: 1334 begin

1335

1336 end

1337

1338 SET_DELAY_8: 1339 begin

1340

1341 end

1342

1343 READ_DATA_SN4: 1344 begin

1345

1346 end

1347

1348 INCR_FOR_4: 1349 begin 1350 j1 <= j1 + 10’d1; 1351 end

1352

1353 START_AOF2: 1354 begin 1355 startaof <= 1’b1;

1356

1357 aof_mem_x_in <= aof_mem_x_out; 1358 aof_mem_y_in <= aof_mem_y_out; 1359 aof_in_prev_f0 <= aof_out_prev_f0; 1360 end

1361

1362 RUN_AOF2: 1363 begin 1364 startaof <= 1’b0; 1365 end

107 1366

1367 GET_AOF2: 1368 begin 1369 c_pitch2 <= aof_nlp_pitch; 1370 c_encode_model_wo <= aof_w0_out;

1371

1372 out_mem_x <= aof_mem_x_out; 1373 out_mem_y <= aof_mem_y_out; 1374 out_prevf0 <= aof_out_prev_f0;

1375

1376 encoded_bits <={aof_voiced1,voiced_bit,46’d0};

1377

1378 c_cmax2 <= aof_check_i; 1379 end

1380

1381 START_SPEECH: 1382 begin 1383 startspeech <= 1’b1;

1384

1385 end

1386

1387 RUN_SPEECH: 1388 begin 1389 //s_out_sn <= read_c2_sn_out; 1390 //addr_sn <= s_addr_sn;

1391

1392 startspeech <= 1’b0; 1393 end

1394

1395 GET_SPEECH: 1396 begin 1397 c_e <= E_speech; 1398 //c_memy <= lsp9; 1399 //c_sn <= aof_w0_out; 1400 //nlp_pitch <= aof_nlp_pitch; 1401 //nlp_pitch1 <= aof_nlp_pitch1;

1402

1403 end

1404

1405 START_ENCODEWOE: 1406 begin 1407 startewoe <= 1’b1; 1408 encode_in_e <= E_speech; 1409 encode_model_wo <= aof_w0_out; 1410 c_encode_model_wo <= aof_w0_out;

108 1411

1412

1413 /* xq0 <= 32’b0; 1414 xq1 <= 32’b0;*/

1415

1416 xq0 <= in_xq0; 1417 xq1 <= in_xq1; 1418 end

1419

1420 RUN_ENCODEWOE: 1421 begin 1422 startewoe <= 1’b0; 1423 end

1424

1425 GET_ENCODEWOE: 1426 begin 1427 c_sn <= encode_out_n1;

1428

1429 out_xq0 <= e_out_xq0; 1430 out_xq1 <= e_out_xq1; 1431 //toGray[8] <= encode_out_n1[8]; 1432 toGray[7] <= encode_out_n1[7]; 1433 toGray[6] <= encode_out_n1[7] ^ encode_out_n1[6]; 1434 toGray[5] <= encode_out_n1[6] ^ encode_out_n1[5]; 1435 toGray[4] <= encode_out_n1[5] ^ encode_out_n1[4]; 1436 toGray[3] <= encode_out_n1[4] ^ encode_out_n1[3]; 1437 toGray[2] <= encode_out_n1[3] ^ encode_out_n1[2]; 1438 toGray[1] <= encode_out_n1[2] ^ encode_out_n1[1]; 1439 toGray[0] <= encode_out_n1[1] ^ encode_out_n1[0]; 1440 end

1441

1442 INIT_FOR_LSP: 1443 begin 1444 lsp <= 4’d0; 1445 encoded_bits <={encoded_bits[47:46],toGray,38’d0}; 1446 end

1447

1448 CHECK_LSP: 1449 begin

1450

1451 end

1452

1453 SET_DATA_LSP: 1454 begin

1455

109 1456

1457 case(lsp)

1458

1459 4’d0: 1460 begin 1461 in_lsp0 <= lsp0; 1462 end 1463 4’d1: 1464 begin 1465 in_lsp1 <= lsp1; 1466 end 1467 4’d2: 1468 begin 1469 in_lsp2 <= lsp2; 1470 end 1471 4’d3: 1472 begin 1473 in_lsp3 <= lsp3; 1474 end 1475 4’d4: 1476 begin 1477 in_lsp4 <= lsp4; 1478 end 1479 4’d5: 1480 begin 1481 in_lsp5 <= lsp5; 1482 end 1483 4’d6: 1484 begin 1485 in_lsp6 <= lsp6; 1486 end 1487 4’d7: 1488 begin 1489 in_lsp7 <= lsp7; 1490 end 1491 4’d8: 1492 begin 1493 in_lsp8 <= lsp8; 1494 end 1495 4’d9: 1496 begin 1497 in_lsp9 <= lsp9; 1498 end

1499

1500 endcase

110 1501

1502 end

1503

1504 INCR_LSP: 1505 begin 1506 lsp <= lsp +4’d1; 1507 end

1508

1509 START_ELSP1: 1510 begin 1511 in_index <= 4’d0; 1512 end

1513

1514 SET_INDEX: 1515 begin 1516 start_elsp <= 1’b1; 1517 end

1518

1519 RUN_ELSP: 1520 begin 1521 start_elsp <= 1’b0; 1522 end

1523

1524 GET_ELSP: 1525 begin 1526 case(in_index) 1527 4’d0: 1528 begin 1529 clsp0 <= out_index; 1530 end 1531 4’d1: 1532 begin 1533 clsp1 <= out_index; 1534 end 1535 4’d2: 1536 begin 1537 clsp2 <= out_index; 1538 end 1539 4’d3: 1540 begin 1541 clsp3 <= out_index; 1542 end 1543 4’d4: 1544 begin 1545 clsp4 <= out_index;

111 1546 end 1547 4’d5: 1548 begin 1549 clsp5 <= out_index; 1550 end 1551 4’d6: 1552 begin 1553 clsp6 <= out_index; 1554 end 1555 4’d7: 1556 begin 1557 clsp7 <= out_index; 1558 end 1559 4’d8: 1560 begin 1561 clsp8 <= out_index; 1562 end 1563 4’d9: 1564 begin 1565 clsp9 <= out_index; 1566 end 1567 endcase

1568

1569 end

1570

1571 INCR_INDEX: 1572 begin 1573 in_index <= in_index +4’d1; 1574 end

1575

1576 CHECK_INDEX: 1577 begin

1578

1579 end

1580

1581 INDEX_TO_GRAY: 1582 begin 1583 case(clsp0) 1584 4’d0: clsp0 <= 4’d0; 1585 4’d1: clsp0 <= 4’d1; 1586 4’d2: clsp0 <= 4’d3; 1587 4’d3: clsp0 <= 4’d2; 1588 4’d4: clsp0 <= 4’d6; 1589 4’d5: clsp0 <= 4’d7; 1590 4’d6: clsp0 <= 4’d5;

112 1591 4’d7: clsp0 <= 4’d4; 1592 4’d8: clsp0 <= 4’d12; 1593 4’d9: clsp0 <= 4’d13; 1594 endcase

1595

1596 case(clsp1) 1597 4’d0: clsp1 <= 4’d0; 1598 4’d1: clsp1 <= 4’d1; 1599 4’d2: clsp1 <= 4’d3; 1600 4’d3: clsp1 <= 4’d2; 1601 4’d4: clsp1 <= 4’d6; 1602 4’d5: clsp1 <= 4’d7; 1603 4’d6: clsp1 <= 4’d5; 1604 4’d7: clsp1 <= 4’d4; 1605 4’d8: clsp1 <= 4’d12; 1606 4’d9: clsp1 <= 4’d13; 1607 endcase

1608

1609 case(clsp2) 1610 4’d0: clsp2 <= 4’d0; 1611 4’d1: clsp2 <= 4’d1; 1612 4’d2: clsp2 <= 4’d3; 1613 4’d3: clsp2 <= 4’d2; 1614 4’d4: clsp2 <= 4’d6; 1615 4’d5: clsp2 <= 4’d7; 1616 4’d6: clsp2 <= 4’d5; 1617 4’d7: clsp2 <= 4’d4; 1618 4’d8: clsp2 <= 4’d12; 1619 4’d9: clsp2 <= 4’d13; 1620 endcase

1621

1622 case(clsp3) 1623 4’d0: clsp3 <= 4’d0; 1624 4’d1: clsp3 <= 4’d1; 1625 4’d2: clsp3 <= 4’d3; 1626 4’d3: clsp3 <= 4’d2; 1627 4’d4: clsp3 <= 4’d6; 1628 4’d5: clsp3 <= 4’d7; 1629 4’d6: clsp3 <= 4’d5; 1630 4’d7: clsp3 <= 4’d4; 1631 4’d8: clsp3 <= 4’d12; 1632 4’d9: clsp3 <= 4’d13; 1633 endcase

1634

1635 case(clsp4)

113 1636 4’d0: clsp4 <= 4’d0; 1637 4’d1: clsp4 <= 4’d1; 1638 4’d2: clsp4 <= 4’d3; 1639 4’d3: clsp4 <= 4’d2; 1640 4’d4: clsp4 <= 4’d6; 1641 4’d5: clsp4 <= 4’d7; 1642 4’d6: clsp4 <= 4’d5; 1643 4’d7: clsp4 <= 4’d4; 1644 4’d8: clsp4 <= 4’d12; 1645 4’d9: clsp4 <= 4’d13; 1646 endcase

1647

1648 case(clsp5) 1649 4’d0: clsp5 <= 4’d0; 1650 4’d1: clsp5 <= 4’d1; 1651 4’d2: clsp5 <= 4’d3; 1652 4’d3: clsp5 <= 4’d2; 1653 4’d4: clsp5 <= 4’d6; 1654 4’d5: clsp5 <= 4’d7; 1655 4’d6: clsp5 <= 4’d5; 1656 4’d7: clsp5 <= 4’d4; 1657 4’d8: clsp5 <= 4’d12; 1658 4’d9: clsp5 <= 4’d13; 1659 endcase

1660

1661 case(clsp6) 1662 4’d0: clsp6 <= 4’d0; 1663 4’d1: clsp6 <= 4’d1; 1664 4’d2: clsp6 <= 4’d3; 1665 4’d3: clsp6 <= 4’d2; 1666 4’d4: clsp6 <= 4’d6; 1667 4’d5: clsp6 <= 4’d7; 1668 4’d6: clsp6 <= 4’d5; 1669 4’d7: clsp6 <= 4’d4; 1670 4’d8: clsp6 <= 4’d12; 1671 4’d9: clsp6 <= 4’d13; 1672 endcase

1673

1674 case(clsp7) 1675 4’d0: clsp7 <= 3’d0; 1676 4’d1: clsp7 <= 3’d1; 1677 4’d2: clsp7 <= 3’d3; 1678 4’d3: clsp7 <= 3’d2; 1679 4’d4: clsp7 <= 3’d6; 1680 4’d5: clsp7 <= 3’d7;

114 1681 4’d6: clsp7 <= 3’d5; 1682 4’d7: clsp7 <= 3’d4; 1683 4’d8: clsp7 <= 3’d12; 1684 4’d9: clsp7 <= 3’d13; 1685 endcase

1686

1687 case(clsp8) 1688 4’d0: clsp8 <= 3’d0; 1689 4’d1: clsp8 <= 3’d1; 1690 4’d2: clsp8 <= 3’d3; 1691 4’d3: clsp8 <= 3’d2; 1692 4’d4: clsp8 <= 3’d6; 1693 4’d5: clsp8 <= 3’d7; 1694 4’d6: clsp8 <= 3’d5; 1695 4’d7: clsp8 <= 3’d4; 1696 4’d8: clsp8 <= 3’d12; 1697 4’d9: clsp8 <= 3’d13;

1698

1699 endcase

1700

1701 case(clsp9) 1702 4’d0: clsp9 <= 2’d0; 1703 4’d1: clsp9 <= 2’d1; 1704 4’d2: clsp9 <= 2’d3; 1705 4’d3: clsp9 <= 2’d2; 1706 4’d4: clsp9 <= 2’d6; 1707 4’d5: clsp9 <= 2’d7; 1708 4’d6: clsp9 <= 2’d5; 1709 4’d7: clsp9 <= 2’d4; 1710 4’d8: clsp9 <= 2’d12; 1711 4’d9: clsp9 <= 2’d13; 1712 endcase

1713

1714

1715 end

1716

1717 SET_ENCODED_BITS: 1718 begin 1719 encoded_bits <={encoded_bits[47:38],clsp0,clsp1,clsp2, 1720 clsp3,clsp4,clsp5,clsp6,clsp7[2:0],clsp8[2:0],clsp9[1:0],2’d0}; 1721 end

1722

1723

1724

1725 AA_SET_ADDR:

115 1726 begin 1727 // addr_sn <= 10’d240; 1728 //we_c2_sn <= 1’b0; 1729 //re_c2_sn <= 1’b1; 1730 end

1731

1732 AA_SET_ADDR1: 1733 begin

1734

1735 end

1736

1737 AA_SET_ADDR2: 1738 begin

1739

1740 end

1741

1742 AA_SET_ADDR_GET: 1743 begin 1744 //c_pitch2 <= read_c2_sn_out; 1745 end

1746

1747 DONE: 1748 begin 1749 done_oneframe <= 1’b1;

1750

1751 end

1752

1753 endcase 1754 end

1755

1756 end

1757

1758

1759 endmodule

B.3 analyse one frame.v

1 module analyse_one_frame( startaof,clk,rst, 2 //--- input------3 mem_x_in,mem_y_in,in_prev_f0, out_sn,out_mem_fir,out_sq, 4 //------

6 //--- output------7 mem_x_out,mem_y_out,out_prev_f0,out_best_f0,aof_w0_out,voiced_bit, addr_sn,addr_mem_fir,in_mem_fir, nlp_pitch, read_fir,write_fir,

116 8

9 addr_nlp_sq,in_sq,read_sq,write_sq, 10 //------11 doneaof

13 );

17 parameterN = 32; 18 parameterQ = 16;

20 parameter N1 = 80; 21 parameter Q1 = 16;

23 input clk,rst,startaof; 24 input[N1-1:0] mem_x_in,mem_y_in; 25 input[N-1:0] out_sn; 26 input[N-1:0] in_prev_f0; 27 input[N1-1:0] out_mem_fir,out_sq;

29 output reg voiced_bit,doneaof,read_fir,write_fir,read_sq,write_sq; 30 output reg[N1-1:0] mem_x_out,mem_y_out; 31 output reg[N-1:0] out_prev_f0,aof_w0_out,nlp_pitch; 32 output reg [9:0] addr_sn,addr_mem_fir,addr_nlp_sq; 33 output reg[N-1:0] aof_check_i;

36 /***------For Module Test------***/

39 /* module analyse_one_frame( startaof,clk,rst, 40 //--- input------/ 41 mem_x_in,mem_y_in,in_prev_f0, 42 //------/

44 //--- output------/ 45 mem_x_out,mem_y_out,out_prev_f0,out_best_f0,aof_w0_out,voiced_bit, nlp_pitch,

48 //------/ 49 doneaof,c_cmax//, c_w0,c_w1, c_cmax,c_outreal,aof_check_in_real,aof_check_in_imag

51 );

117 53 parameterN= 32; 54 parameterQ= 16; 55 parameter N1= 80; 56 parameter Q1= 16;

58 input clk,rst,startaof; 59 input[N1-1:0] mem_x_in,mem_y_in; 60 input[N-1:0] in_prev_f0;

62 output reg voiced_bit,doneaof; 63 output reg[N1-1:0] mem_x_out,mem_y_out; 64 reg[N1-1:0] c_outreal,aof_check_in_real,aof_check_in_imag; 65 output reg[N-1:0] out_prev_f0,aof_w0_out,nlp_pitch; 66 reg[N-1:0] c_w0,c_w1; 67 output reg [9:0] c_cmax; 68 reg [9:0] aof_check_i;

70 //RAM Sn 71 reg [9:0] addr_sn; 72 wire[N-1:0] out_sn; 73 RAM_c2_sn_test_nlp c2_sn(addr_sn,clk,,1,0,out_sn);

75 // RAM_nlp_mem_fir- size 48------76 reg [9:0] addr_mem_fir; 77 reg[N1-1:0] in_mem_fir; 78 reg read_fir, write_fir; 79 wire[N1-1:0] out_mem_fir; 80 RAM_nlp_mem_fir_80 mem_fir(addr_mem_fir,clk,in_mem_fir, 81 read_fir,write_fir,out_mem_fir); 82 // RAM_nlp_sq- size 320------83 reg [9:0] addr_nlp_sq; 84 reg[N1-1:0] in_sq; 85 reg read_sq,write_sq; 86 wire[N1-1:0] out_sq; 87 RAM_nlp_sq_80 nlp_sq(addr_nlp_sq,clk,in_sq, 88 read_sq,write_sq,out_sq);*/

91 //------92 //-- Input/Output Declarations-- 93 //------

96 //------97 //-- State& Reg Declarations--

118 98 //------

100 parameterSTART =8’d3, 101 INIT_FOR_1 =8’d11, 102 CHECK_I_1 =8’d21, 103 SET_ADDR_SN_1 =8’d0, 104 SET_DELAY1 =8’d4, 105 SET_DELAY2 =8’d5, 106 SET_MULT_1 =8’d6, 107 SET_SW_REAL_1 =8’d7, 108 INCR_I_1 =8’d8, 109 INIT_FOR_2 =8’d9, 110 CHECK_I_2 =8’d10, 111 SET_ADDR_SN_2 =8’d1, 112 SET_DELAY3 =8’d12, 113 SET_DELAY4 =8’d13, 114 SET_MULT_2 =8’d14, 115 SET_SW_REAL_2 =8’d15, 116 INCR_I_2 =8’d16, 117 DONE =8’d17, 118 START_DFT =8’d18, 119 RUN_DFT =8’d19, 120 START_NLP =8’d20, 121 RUN_NLP =8’d2, 122 GET_NLP =8’d22, 123 START_TSPR =8’d23, 124 RUN_TSPR =8’d24, 125 GET_TSPR =8’d25, 126 START_EA =8’d26, 127 RUN_EA =8’d27, 128 GET_EA =8’d28, 129 START_EVM =8’d29, 130 RUN_EVM =8’d30, 131 GET_EVM =8’d31, 132 CALC_DIV_PITCH =8’d32, 133 SET_DIV_PITCH =8’d33, 134 CALC_WO =8’d34, 135 CALC_DIV_WO =8’d35, 136 SET_DIV_WO =8’d36, 137 CALC_L =8’d37;

138

139 reg [7:0]STATE,NEXT_STATE;

140

141 parameter [9:0] mpitch = 10’d320, 142 mpitch_by_2 = 10’d160,

119 143 nw = 10’d279, 144 nw_by_2 = 10’d139, 145 fft_enc = 10’d512;

146

147 parameter[N-1:0]PI =32’b00000000000000110010010000111111, 148 TWO_PI =32’b00000000000001100100100001111110;

149

150 parameter[N-1:0] w0 =32’b00000000000000000000000000000000, 151 w1 =32’b00000000000000000000000000000000, 152 w2 =32’b00000000000000000000000000000000, 153 w3 =32’b00000000000000000000000000000000, 154 w4 =32’b00000000000000000000000000000000, 155 w5 =32’b00000000000000000000000000000000, 156 w6 =32’b00000000000000000000000000000000, 157 w7 =32’b00000000000000000000000000000000, 158 w8 =32’b00000000000000000000000000000000, 159 w9 =32’b00000000000000000000000000000000, 160 w10 =32’b00000000000000000000000000000000, 161 w11 =32’b00000000000000000000000000000000, 162 w12 =32’b00000000000000000000000000000000, 163 w13 =32’b00000000000000000000000000000000, 164 w14 =32’b00000000000000000000000000000000, 165 w15 =32’b00000000000000000000000000000000, 166 w16 =32’b00000000000000000000000000000000, 167 w17 =32’b00000000000000000000000000000000, 168 w18 =32’b00000000000000000000000000000000, 169 w19 =32’b00000000000000000000000000000000, 170 w20 =32’b00000000000000000000000000000000, 171 w21 =32’b00000000000000000000000000000000, 172 w22 =32’b00000000000000000000000000000000, 173 w23 =32’b00000000000000000000000000000000, 174 w24 =32’b00000000000000000000000000000000, 175 w25 =32’b00000000000000000000000000000000, 176 w26 =32’b00000000000000000000000000000000, 177 w27 =32’b00000000000000000000000000000001, 178 w28 =32’b00000000000000000000000000000001, 179 w29 =32’b00000000000000000000000000000010, 180 w30 =32’b00000000000000000000000000000010, 181 w31 =32’b00000000000000000000000000000011, 182 w32 =32’b00000000000000000000000000000100, 183 w33 =32’b00000000000000000000000000000101, 184 w34 =32’b00000000000000000000000000000110, 185 w35 =32’b00000000000000000000000000000111, 186 w36 =32’b00000000000000000000000000001000, 187 w37 =32’b00000000000000000000000000001001,

120 188 w38 =32’b00000000000000000000000000001010, 189 w39 =32’b00000000000000000000000000001011, 190 w40 =32’b00000000000000000000000000001100, 191 w41 =32’b00000000000000000000000000001110, 192 w42 =32’b00000000000000000000000000001111, 193 w43 =32’b00000000000000000000000000010001, 194 w44 =32’b00000000000000000000000000010010, 195 w45 =32’b00000000000000000000000000010100, 196 w46 =32’b00000000000000000000000000010110, 197 w47 =32’b00000000000000000000000000010111, 198 w48 =32’b00000000000000000000000000011001, 199 w49 =32’b00000000000000000000000000011011, 200 w50 =32’b00000000000000000000000000011101, 201 w51 =32’b00000000000000000000000000011111, 202 w52 =32’b00000000000000000000000000100001, 203 w53 =32’b00000000000000000000000000100011, 204 w54 =32’b00000000000000000000000000100101, 205 w55 =32’b00000000000000000000000000100111, 206 w56 =32’b00000000000000000000000000101010, 207 w57 =32’b00000000000000000000000000101100, 208 w58 =32’b00000000000000000000000000101110, 209 w59 =32’b00000000000000000000000000110001, 210 w60 =32’b00000000000000000000000000110011, 211 w61 =32’b00000000000000000000000000110110, 212 w62 =32’b00000000000000000000000000111000, 213 w63 =32’b00000000000000000000000000111011, 214 w64 =32’b00000000000000000000000000111101, 215 w65 =32’b00000000000000000000000001000000, 216 w66 =32’b00000000000000000000000001000011, 217 w67 =32’b00000000000000000000000001000101, 218 w68 =32’b00000000000000000000000001001000, 219 w69 =32’b00000000000000000000000001001011, 220 w70 =32’b00000000000000000000000001001110, 221 w71 =32’b00000000000000000000000001010001, 222 w72 =32’b00000000000000000000000001010100, 223 w73 =32’b00000000000000000000000001010111, 224 w74 =32’b00000000000000000000000001011010, 225 w75 =32’b00000000000000000000000001011101, 226 w76 =32’b00000000000000000000000001100000, 227 w77 =32’b00000000000000000000000001100011, 228 w78 =32’b00000000000000000000000001100110, 229 w79 =32’b00000000000000000000000001101001, 230 w80 =32’b00000000000000000000000001101100, 231 w81 =32’b00000000000000000000000001101111, 232 w82 =32’b00000000000000000000000001110010,

121 233 w83 =32’b00000000000000000000000001110101, 234 w84 =32’b00000000000000000000000001111001, 235 w85 =32’b00000000000000000000000001111100, 236 w86 =32’b00000000000000000000000001111111, 237 w87 =32’b00000000000000000000000010000010, 238 w88 =32’b00000000000000000000000010000101, 239 w89 =32’b00000000000000000000000010001001, 240 w90 =32’b00000000000000000000000010001100, 241 w91 =32’b00000000000000000000000010001111, 242 w92 =32’b00000000000000000000000010010010, 243 w93 =32’b00000000000000000000000010010101, 244 w94 =32’b00000000000000000000000010011001, 245 w95 =32’b00000000000000000000000010011100, 246 w96 =32’b00000000000000000000000010011111, 247 w97 =32’b00000000000000000000000010100010, 248 w98 =32’b00000000000000000000000010100101, 249 w99 =32’b00000000000000000000000010101000, 250 w100 =32’b00000000000000000000000010101100, 251 w101 =32’b00000000000000000000000010101111, 252 w102 =32’b00000000000000000000000010110010, 253 w103 =32’b00000000000000000000000010110101, 254 w104 =32’b00000000000000000000000010111000, 255 w105 =32’b00000000000000000000000010111011, 256 w106 =32’b00000000000000000000000010111110, 257 w107 =32’b00000000000000000000000011000001, 258 w108 =32’b00000000000000000000000011000100, 259 w109 =32’b00000000000000000000000011000111, 260 w110 =32’b00000000000000000000000011001010, 261 w111 =32’b00000000000000000000000011001101, 262 w112 =32’b00000000000000000000000011010000, 263 w113 =32’b00000000000000000000000011010010, 264 w114 =32’b00000000000000000000000011010101, 265 w115 =32’b00000000000000000000000011011000, 266 w116 =32’b00000000000000000000000011011011, 267 w117 =32’b00000000000000000000000011011101, 268 w118 =32’b00000000000000000000000011100000, 269 w119 =32’b00000000000000000000000011100011, 270 w120 =32’b00000000000000000000000011100101, 271 w121 =32’b00000000000000000000000011101000, 272 w122 =32’b00000000000000000000000011101010, 273 w123 =32’b00000000000000000000000011101100, 274 w124 =32’b00000000000000000000000011101111, 275 w125 =32’b00000000000000000000000011110001, 276 w126 =32’b00000000000000000000000011110011, 277 w127 =32’b00000000000000000000000011110110,

122 278 w128 =32’b00000000000000000000000011111000, 279 w129 =32’b00000000000000000000000011111010, 280 w130 =32’b00000000000000000000000011111100, 281 w131 =32’b00000000000000000000000011111110, 282 w132 =32’b00000000000000000000000100000000, 283 w133 =32’b00000000000000000000000100000010, 284 w134 =32’b00000000000000000000000100000011, 285 w135 =32’b00000000000000000000000100000101, 286 w136 =32’b00000000000000000000000100000111, 287 w137 =32’b00000000000000000000000100001000, 288 w138 =32’b00000000000000000000000100001010, 289 w139 =32’b00000000000000000000000100001011, 290 w140 =32’b00000000000000000000000100001101, 291 w141 =32’b00000000000000000000000100001110, 292 w142 =32’b00000000000000000000000100010000, 293 w143 =32’b00000000000000000000000100010001, 294 w144 =32’b00000000000000000000000100010010, 295 w145 =32’b00000000000000000000000100010011, 296 w146 =32’b00000000000000000000000100010100, 297 w147 =32’b00000000000000000000000100010101, 298 w148 =32’b00000000000000000000000100010110, 299 w149 =32’b00000000000000000000000100010111, 300 w150 =32’b00000000000000000000000100011000, 301 w151 =32’b00000000000000000000000100011000, 302 w152 =32’b00000000000000000000000100011001, 303 w153 =32’b00000000000000000000000100011001, 304 w154 =32’b00000000000000000000000100011010, 305 w155 =32’b00000000000000000000000100011010, 306 w156 =32’b00000000000000000000000100011011, 307 w157 =32’b00000000000000000000000100011011, 308 w158 =32’b00000000000000000000000100011011, 309 w159 =32’b00000000000000000000000100011011, 310 w160 =32’b00000000000000000000000100011011, 311 w161 =32’b00000000000000000000000100011011, 312 w162 =32’b00000000000000000000000100011011, 313 w163 =32’b00000000000000000000000100011011, 314 w164 =32’b00000000000000000000000100011011, 315 w165 =32’b00000000000000000000000100011010, 316 w166 =32’b00000000000000000000000100011010, 317 w167 =32’b00000000000000000000000100011001, 318 w168 =32’b00000000000000000000000100011001, 319 w169 =32’b00000000000000000000000100011000, 320 w170 =32’b00000000000000000000000100011000, 321 w171 =32’b00000000000000000000000100010111, 322 w172 =32’b00000000000000000000000100010110,

123 323 w173 =32’b00000000000000000000000100010101, 324 w174 =32’b00000000000000000000000100010100, 325 w175 =32’b00000000000000000000000100010011, 326 w176 =32’b00000000000000000000000100010010, 327 w177 =32’b00000000000000000000000100010001, 328 w178 =32’b00000000000000000000000100010000, 329 w179 =32’b00000000000000000000000100001110, 330 w180 =32’b00000000000000000000000100001101, 331 w181 =32’b00000000000000000000000100001011, 332 w182 =32’b00000000000000000000000100001010, 333 w183 =32’b00000000000000000000000100001000, 334 w184 =32’b00000000000000000000000100000111, 335 w185 =32’b00000000000000000000000100000101, 336 w186 =32’b00000000000000000000000100000011, 337 w187 =32’b00000000000000000000000100000010, 338 w188 =32’b00000000000000000000000100000000, 339 w189 =32’b00000000000000000000000011111110, 340 w190 =32’b00000000000000000000000011111100, 341 w191 =32’b00000000000000000000000011111010, 342 w192 =32’b00000000000000000000000011111000, 343 w193 =32’b00000000000000000000000011110110, 344 w194 =32’b00000000000000000000000011110011, 345 w195 =32’b00000000000000000000000011110001, 346 w196 =32’b00000000000000000000000011101111, 347 w197 =32’b00000000000000000000000011101100, 348 w198 =32’b00000000000000000000000011101010, 349 w199 =32’b00000000000000000000000011101000, 350 w200 =32’b00000000000000000000000011100101, 351 w201 =32’b00000000000000000000000011100011, 352 w202 =32’b00000000000000000000000011100000, 353 w203 =32’b00000000000000000000000011011101, 354 w204 =32’b00000000000000000000000011011011, 355 w205 =32’b00000000000000000000000011011000, 356 w206 =32’b00000000000000000000000011010101, 357 w207 =32’b00000000000000000000000011010010, 358 w208 =32’b00000000000000000000000011010000, 359 w209 =32’b00000000000000000000000011001101, 360 w210 =32’b00000000000000000000000011001010, 361 w211 =32’b00000000000000000000000011000111, 362 w212 =32’b00000000000000000000000011000100, 363 w213 =32’b00000000000000000000000011000001, 364 w214 =32’b00000000000000000000000010111110, 365 w215 =32’b00000000000000000000000010111011, 366 w216 =32’b00000000000000000000000010111000, 367 w217 =32’b00000000000000000000000010110101,

124 368 w218 =32’b00000000000000000000000010110010, 369 w219 =32’b00000000000000000000000010101111, 370 w220 =32’b00000000000000000000000010101100, 371 w221 =32’b00000000000000000000000010101000, 372 w222 =32’b00000000000000000000000010100101, 373 w223 =32’b00000000000000000000000010100010, 374 w224 =32’b00000000000000000000000010011111, 375 w225 =32’b00000000000000000000000010011100, 376 w226 =32’b00000000000000000000000010011001, 377 w227 =32’b00000000000000000000000010010101, 378 w228 =32’b00000000000000000000000010010010, 379 w229 =32’b00000000000000000000000010001111, 380 w230 =32’b00000000000000000000000010001100, 381 w231 =32’b00000000000000000000000010001001, 382 w232 =32’b00000000000000000000000010000101, 383 w233 =32’b00000000000000000000000010000010, 384 w234 =32’b00000000000000000000000001111111, 385 w235 =32’b00000000000000000000000001111100, 386 w236 =32’b00000000000000000000000001111001, 387 w237 =32’b00000000000000000000000001110101, 388 w238 =32’b00000000000000000000000001110010, 389 w239 =32’b00000000000000000000000001101111, 390 w240 =32’b00000000000000000000000001101100, 391 w241 =32’b00000000000000000000000001101001, 392 w242 =32’b00000000000000000000000001100110, 393 w243 =32’b00000000000000000000000001100011, 394 w244 =32’b00000000000000000000000001100000, 395 w245 =32’b00000000000000000000000001011101, 396 w246 =32’b00000000000000000000000001011010, 397 w247 =32’b00000000000000000000000001010111, 398 w248 =32’b00000000000000000000000001010100, 399 w249 =32’b00000000000000000000000001010001, 400 w250 =32’b00000000000000000000000001001110, 401 w251 =32’b00000000000000000000000001001011, 402 w252 =32’b00000000000000000000000001001000, 403 w253 =32’b00000000000000000000000001000101, 404 w254 =32’b00000000000000000000000001000011, 405 w255 =32’b00000000000000000000000001000000, 406 w256 =32’b00000000000000000000000000111101, 407 w257 =32’b00000000000000000000000000111011, 408 w258 =32’b00000000000000000000000000111000, 409 w259 =32’b00000000000000000000000000110110, 410 w260 =32’b00000000000000000000000000110011, 411 w261 =32’b00000000000000000000000000110001, 412 w262 =32’b00000000000000000000000000101110,

125 413 w263 =32’b00000000000000000000000000101100, 414 w264 =32’b00000000000000000000000000101010, 415 w265 =32’b00000000000000000000000000100111, 416 w266 =32’b00000000000000000000000000100101, 417 w267 =32’b00000000000000000000000000100011, 418 w268 =32’b00000000000000000000000000100001, 419 w269 =32’b00000000000000000000000000011111, 420 w270 =32’b00000000000000000000000000011101, 421 w271 =32’b00000000000000000000000000011011, 422 w272 =32’b00000000000000000000000000011001, 423 w273 =32’b00000000000000000000000000010111, 424 w274 =32’b00000000000000000000000000010110, 425 w275 =32’b00000000000000000000000000010100, 426 w276 =32’b00000000000000000000000000010010, 427 w277 =32’b00000000000000000000000000010001, 428 w278 =32’b00000000000000000000000000001111, 429 w279 =32’b00000000000000000000000000001110, 430 w280 =32’b00000000000000000000000000001100, 431 w281 =32’b00000000000000000000000000001011, 432 w282 =32’b00000000000000000000000000001010, 433 w283 =32’b00000000000000000000000000001001, 434 w284 =32’b00000000000000000000000000001000, 435 w285 =32’b00000000000000000000000000000111, 436 w286 =32’b00000000000000000000000000000110, 437 w287 =32’b00000000000000000000000000000101, 438 w288 =32’b00000000000000000000000000000100, 439 w289 =32’b00000000000000000000000000000011, 440 w290 =32’b00000000000000000000000000000010, 441 w291 =32’b00000000000000000000000000000010, 442 w292 =32’b00000000000000000000000000000001, 443 w293 =32’b00000000000000000000000000000001, 444 w294 =32’b00000000000000000000000000000000, 445 w295 =32’b00000000000000000000000000000000, 446 w296 =32’b00000000000000000000000000000000, 447 w297 =32’b00000000000000000000000000000000, 448 w298 =32’b00000000000000000000000000000000, 449 w299 =32’b00000000000000000000000000000000, 450 w300 =32’b00000000000000000000000000000000, 451 w301 =32’b00000000000000000000000000000000, 452 w302 =32’b00000000000000000000000000000000, 453 w303 =32’b00000000000000000000000000000000, 454 w304 =32’b00000000000000000000000000000000, 455 w305 =32’b00000000000000000000000000000000, 456 w306 =32’b00000000000000000000000000000000, 457 w307 =32’b00000000000000000000000000000000,

126 458 w308 =32’b00000000000000000000000000000000, 459 w309 =32’b00000000000000000000000000000000, 460 w310 =32’b00000000000000000000000000000000, 461 w311 =32’b00000000000000000000000000000000, 462 w312 =32’b00000000000000000000000000000000, 463 w313 =32’b00000000000000000000000000000000, 464 w314 =32’b00000000000000000000000000000000, 465 w315 =32’b00000000000000000000000000000000, 466 w316 =32’b00000000000000000000000000000000, 467 w317 =32’b00000000000000000000000000000000, 468 w318 =32’b00000000000000000000000000000000, 469 w319 =32’b00000000000000000000000000000000;

470

471

472 reg [9:0]i;

473

474

475 //------476 //-- Module Instantiations-- 477 //------478 reg[N-1:0] m1_in1, m1_in2, m2_in1, m2_in2; 479 wire[N-1:0] m1_out, m2_out;

480

481 reg [9:0] addr_sw_fft_imag,addr_sw_fft_real,addr_sw_imag,addr_sw_real; 482 reg re_sw,we_sw,re_sw_fft,we_sw_fft;

483

484 reg[N-1:0] write_sw_fft_imag,write_sw_fft_real,write_sw_imag,write_sw_real; 485 wire[N-1:0] out_sw_imag,out_sw_real,out_sw_fft_imag,out_sw_fft_real;

486

487 qmult#(Q,N) qmult1(m1_in1,m1_in2,m1_out); 488 qmult#(Q,N) qmult2(m2_in1,m2_in2,m2_out); 489 //------Speech samples------// 490 //------Speech samplesFFT input------// 491 RAM_Sw_in_real in_real(addr_sw_real,clk,write_sw_real, 492 re_sw,we_sw,out_sw_real); 493 RAM_Sw_in_imag in_imag(addr_sw_imag,clk,write_sw_imag, 494 re_sw,we_sw,out_sw_imag);

495

496 //------Speech samplesFFT output------// 497 RAM_Sw_fft_real fft_out_real(addr_sw_fft_real,clk,write_sw_fft_real 498 ,re_sw_fft,we_sw_fft,out_sw_fft_real); 499 RAM_Sw_fft_imag fft_out_imag(addr_sw_fft_imag,clk,write_sw_fft_imag 500 ,re_sw_fft,we_sw_fft,out_sw_fft_imag); 501 //------FFT for nlp------// 502 reg startfft;

127 503 wire[N-1:0] in_imag_data,in_real_data,fft_write_fft_real,fft_write_fft_imag; 504 wire [9:0] fft_addr_in_imag,fft_addr_in_real,fft_addr_out_real,fft_addr_out_imag; 505 wire donefft;

506

507 dft fft_nlp_module(startfft,clk,rst,out_sw_imag,out_sw_real, 508 fft_addr_in_imag,fft_addr_in_real,fft_addr_out_real,fft_addr_out_imag, 509 fft_write_fft_real,fft_write_fft_imag,donefft);

510

511

512 //------NLP module------// 513 reg startnlp; 514 wire [9:0] nlp_addr_sn,nlp_addr_mem_fir,nlp_addr_nlp_sq; 515 reg[N1-1:0] nlp_mem_x,nlp_mem_y,nlp_out_mem_fir,nlp_out_sq; 516 reg[N-1:0] prev_f0,nlp_out_sn,one_by_pitch,one_by_wo; 517 wire[N-1:0] pitch,best_f0,o_prev_f0; 518 wire[N1-1:0] nlp_mem_x_out,nlp_mem_y_out,nlp_in_mem_fir,nlp_in_sq;//nlp_pitch; 519 wire nlp_read_fir,nlp_write_fir,donenlp,nlp_read_sq,nlp_write_sq; 520 output reg[N-1:0] out_best_f0;

521

522 reg[N-1:0] nlp_m1_out; 523 //wire[N-1:0] nlp_m1_in1,nlp_m1_in2; 524 wire [9:0] check_cmax_bin; 525 wire[N-1:0] check_i; 526 wire[N1-1:0] check_in_sq,check_in_real,check_in_imag;

527

528

529

530 nlp_extended_bits nlp_module(startnlp,clk,rst,nlp_out_sn,nlp_out_sq, 531 nlp_out_mem_fir,nlp_mem_x,nlp_mem_y,prev_f0,best_f0,o_prev_f0,pitch, 532 nlp_mem_x_out,nlp_mem_y_out,nlp_addr_sn,nlp_addr_mem_fir,nlp_in_mem_fir, 533 nlp_read_fir,nlp_write_fir,nlp_addr_nlp_sq,nlp_read_sq, 534 nlp_write_sq,nlp_in_sq,donenlp 535 );

536

537 //------Division module------// 538 reg startdiv; 539 reg[N-1:0] div_in; 540 wire[N-1:0] div_ans; 541 wire donediv;

542

543 fpdiv_clk divider(startdiv,clk,rst,div_in,div_ans,donediv);

544

545

546 //------two_stage_pitch_refinement module------// 547 reg starttspr;

128 548 reg[N-1:0] Wo_in,L_in; 549 wire[N-1:0] Wo_out,L_out;//c_w0; 550 wire donetspr;

551

552 reg[N-1:0] out_real, out_imag; 553 wire [9:0] addr_real,addr_imag;

554

555 two_stage_pitch_refinement tspr_module(starttspr,clk,rst,Wo_in,L_in, 556 out_real,out_imag,Wo_out,L_out,addr_real,addr_imag, 557 donetspr,ts_c_w0,ts_c_w1);

558

559 wire[N-1:0] ts_c_w0,ts_c_w1; 560 //------estimate_amplitudes module------//

561

562 reg startea; 563 reg[N-1:0] ea_Wo; 564 reg [9:0] ea_L; 565 wire doneea; 566 wire [9:0] ea_addr_real,ea_addr_imag,ea_addr_a; 567 reg[N-1:0] ea_out_real,ea_out_imag; 568 wire[N-1:0] ea_write_data_a;

569

570 estimate_amplitudes ea_module(startea,clk,rst,ea_Wo,ea_L,ea_out_real,ea_out_imag, 571 ea_addr_real,ea_addr_imag,ea_addr_a,ea_write_data_a, 572 doneea);

573

574 //------estimate_voicing_mbe module------// 575 reg startevmbe; 576 reg [9:0] evm_L_in; 577 reg[N-1:0] evm_Wo_in,evm_out_am,evm_out_sw_real,evm_out_sw_imag; 578 wire[N-1:0] evm_snr; 579 wire [9:0] evm_addr_am,evm_addr_sw_real,evm_addr_sw_imag; 580 wire evm_voiced,doneevmbe;

581

582

583 estimate_voicing_mbe evm_module(startevmbe, clk, rst, evm_L_in, evm_Wo_in, 584 evm_out_am,evm_out_sw_real,evm_out_sw_imag, evm_snr, evm_voiced, 585 evm_addr_am,evm_addr_sw_real,evm_addr_sw_imag,doneevmbe);

586

587 //------model->ARAM module------// 588 reg [9:0] addr_a; 589 wire[N-1:0] out_a; 590 reg[N-1:0] write_data_a; 591 reg re_am,we_am;

592

129 593 RAM_model_A modelram(addr_a,clk,write_data_a,re_am,we_am,out_a);

594

595 //------596 //-- Begin Declarations& Coding-- 597 //------

598

599 always@(posedge clk or negedge rst)// DetermineSTATE 600 begin

601

602 if(rst == 1’b0) 603 STATE <=START; 604 else 605 STATE <=NEXT_STATE;

606

607 end

608

609 always@(*) 610 begin 611 case(STATE)

612

613 SET_ADDR_SN_1: 614 begin 615 addr_sn=i+ mpitch_by_2; 616 nlp_out_sn <= out_sn;

617

618 addr_mem_fir <= nlp_addr_mem_fir; 619 in_mem_fir <= nlp_in_mem_fir; 620 read_fir <= nlp_read_fir; 621 write_fir <= nlp_write_fir; 622 nlp_out_mem_fir <= out_mem_fir;

623

624 addr_nlp_sq <= nlp_addr_nlp_sq; 625 in_sq <= nlp_in_sq; 626 read_sq <= nlp_read_sq; 627 write_sq <= nlp_write_sq; 628 nlp_out_sq <= out_sq; 629 end

630

631 SET_DELAY1: 632 begin 633 addr_sn=i+ mpitch_by_2; 634 nlp_out_sn <= out_sn;

635

636 addr_mem_fir <= nlp_addr_mem_fir; 637 in_mem_fir <= nlp_in_mem_fir;

130 638 read_fir <= nlp_read_fir; 639 write_fir <= nlp_write_fir; 640 nlp_out_mem_fir <= out_mem_fir;

641

642 addr_nlp_sq <= nlp_addr_nlp_sq; 643 in_sq <= nlp_in_sq; 644 read_sq <= nlp_read_sq; 645 write_sq <= nlp_write_sq; 646 nlp_out_sq <= out_sq; 647 end

648

649 SET_DELAY2: 650 begin 651 addr_sn=i+ mpitch_by_2; 652 nlp_out_sn <= out_sn;

653

654 addr_mem_fir <= nlp_addr_mem_fir; 655 in_mem_fir <= nlp_in_mem_fir; 656 read_fir <= nlp_read_fir; 657 write_fir <= nlp_write_fir; 658 nlp_out_mem_fir <= out_mem_fir;

659

660 addr_nlp_sq <= nlp_addr_nlp_sq; 661 in_sq <= nlp_in_sq; 662 read_sq <= nlp_read_sq; 663 write_sq <= nlp_write_sq; 664 nlp_out_sq <= out_sq; 665 end

666

667 SET_ADDR_SN_2: 668 begin 669 addr_sn=i + 10’d21; 670 nlp_out_sn <= out_sn;

671

672 addr_mem_fir <= nlp_addr_mem_fir; 673 in_mem_fir <= nlp_in_mem_fir; 674 read_fir <= nlp_read_fir; 675 write_fir <= nlp_write_fir; 676 nlp_out_mem_fir <= out_mem_fir;

677

678 addr_nlp_sq <= nlp_addr_nlp_sq; 679 in_sq <= nlp_in_sq; 680 read_sq <= nlp_read_sq; 681 write_sq <= nlp_write_sq; 682 nlp_out_sq <= out_sq;

131 683 end

684

685 SET_DELAY3: 686 begin 687 addr_sn=i + 10’d21; 688 nlp_out_sn <= out_sn;

689

690 addr_mem_fir <= nlp_addr_mem_fir; 691 in_mem_fir <= nlp_in_mem_fir; 692 read_fir <= nlp_read_fir; 693 write_fir <= nlp_write_fir; 694 nlp_out_mem_fir <= out_mem_fir;

695

696 addr_nlp_sq <= nlp_addr_nlp_sq; 697 in_sq <= nlp_in_sq; 698 read_sq <= nlp_read_sq; 699 write_sq <= nlp_write_sq; 700 nlp_out_sq <= out_sq; 701 end

702

703 SET_DELAY4: 704 begin 705 addr_sn=i + 10’d21;

706

707 nlp_out_sn <= out_sn;

708

709 addr_mem_fir <= nlp_addr_mem_fir; 710 in_mem_fir <= nlp_in_mem_fir; 711 read_fir <= nlp_read_fir; 712 write_fir <= nlp_write_fir; 713 nlp_out_mem_fir <= out_mem_fir;

714

715 addr_nlp_sq <= nlp_addr_nlp_sq; 716 in_sq <= nlp_in_sq; 717 read_sq <= nlp_read_sq; 718 write_sq <= nlp_write_sq; 719 nlp_out_sq <= out_sq; 720 end

721

722

723 RUN_NLP: 724 begin 725 nlp_out_sn= out_sn; 726 addr_sn= nlp_addr_sn;

727

132 728 addr_mem_fir= nlp_addr_mem_fir; 729 in_mem_fir= nlp_in_mem_fir; 730 read_fir= nlp_read_fir; 731 write_fir= nlp_write_fir; 732 nlp_out_mem_fir= out_mem_fir;

733

734 addr_nlp_sq= nlp_addr_nlp_sq; 735 in_sq= nlp_in_sq; 736 read_sq= nlp_read_sq; 737 write_sq= nlp_write_sq; 738 nlp_out_sq= out_sq; 739 end

740

741 START_NLP: 742 begin 743 nlp_out_sn= out_sn; 744 addr_sn= nlp_addr_sn;

745

746 addr_mem_fir= nlp_addr_mem_fir; 747 in_mem_fir= nlp_in_mem_fir; 748 read_fir= nlp_read_fir; 749 write_fir= nlp_write_fir; 750 nlp_out_mem_fir= out_mem_fir;

751

752 addr_nlp_sq= nlp_addr_nlp_sq; 753 in_sq= nlp_in_sq; 754 read_sq= nlp_read_sq; 755 write_sq= nlp_write_sq; 756 nlp_out_sq= out_sq; 757 end

758

759 default: 760 begin 761 /* addr_sn= 10’d0; 762 nlp_out_sn= 32’b0;

763

764 addr_mem_fir= 10’b0; 765 in_mem_fir= 80’b0; 766 read_fir= 1’b0; 767 write_fir= 1’b0; 768 nlp_out_mem_fir= 80’b0;

769

770 addr_nlp_sq= 10’b0; 771 in_sq= 80’b0; 772 read_sq= 1’b0;

133 773 write_sq= 1’b0; 774 nlp_out_sq= 80’b0;*/

775

776 nlp_out_sn <= out_sn; 777 addr_sn <= nlp_addr_sn;

778

779 addr_mem_fir <= nlp_addr_mem_fir; 780 in_mem_fir <= nlp_in_mem_fir; 781 read_fir <= nlp_read_fir; 782 write_fir <= nlp_write_fir; 783 nlp_out_mem_fir <= out_mem_fir;

784

785 addr_nlp_sq <= nlp_addr_nlp_sq; 786 in_sq <= nlp_in_sq; 787 read_sq <= nlp_read_sq; 788 write_sq <= nlp_write_sq; 789 nlp_out_sq <= out_sq; 790 end

791

792 endcase

793

794 end

795

796

797 always@(*)// DetermineNEXT_STATE 798 begin 799 case(STATE)

800

801 START: 802 begin 803 if(startaof == 1’b1) 804 begin 805 NEXT_STATE= INIT_FOR_1; 806 end 807 else 808 begin 809 NEXT_STATE=START; 810 end 811 end

812

813 INIT_FOR_1: 814 begin 815 NEXT_STATE= CHECK_I_1; 816 end

817

134 818 CHECK_I_1: 819 begin 820 if(i< nw_by_2) 821 begin 822 NEXT_STATE= SET_ADDR_SN_1; 823 end 824 else 825 begin 826 NEXT_STATE= INIT_FOR_2; 827 end 828 end

829

830 SET_ADDR_SN_1: 831 begin 832 NEXT_STATE= SET_DELAY1; 833 end

834

835 SET_DELAY1: 836 begin 837 NEXT_STATE= SET_DELAY2; 838 end

839

840 SET_DELAY2: 841 begin 842 NEXT_STATE= SET_MULT_1; 843 end

844

845 SET_MULT_1: 846 begin 847 NEXT_STATE= SET_SW_REAL_1; 848 end

849

850 SET_SW_REAL_1: 851 begin 852 NEXT_STATE= INCR_I_1; 853 end

854

855 INCR_I_1: 856 begin 857 NEXT_STATE= CHECK_I_1; 858 end

859

860 INIT_FOR_2: 861 begin 862 NEXT_STATE= CHECK_I_2;

135 863 end

864

865 CHECK_I_2: 866 begin 867 if(i< nw_by_2) 868 begin 869 NEXT_STATE= SET_ADDR_SN_2; 870 end 871 else 872 begin 873 NEXT_STATE=START_DFT; 874 end 875 end

876

877 SET_ADDR_SN_2: 878 begin 879 NEXT_STATE= SET_DELAY3; 880 //addr_sn=i+ 10’d21; 881 end

882

883 SET_DELAY3: 884 begin 885 NEXT_STATE= SET_DELAY4; 886 end

887

888 SET_DELAY4: 889 begin 890 NEXT_STATE= SET_MULT_2; 891 end

892

893 SET_MULT_2: 894 begin 895 NEXT_STATE= SET_SW_REAL_2; 896 end

897

898 SET_SW_REAL_2: 899 begin 900 NEXT_STATE= INCR_I_2; 901 end

902

903 INCR_I_2: 904 begin 905 NEXT_STATE= CHECK_I_2; 906 end

907

136 908 START_DFT: 909 begin 910 NEXT_STATE=RUN_DFT; 911 end

912

913 RUN_DFT: 914 begin 915 if(donefft) 916 begin 917 NEXT_STATE=START_NLP; 918 end 919 else 920 begin 921 NEXT_STATE=RUN_DFT; 922 end 923 end

924

925 START_NLP: 926 begin 927 NEXT_STATE=RUN_NLP; 928 end

929

930 RUN_NLP: 931 begin 932 if(donenlp) 933 begin 934 NEXT_STATE=GET_NLP; 935 end 936 else 937 begin 938 NEXT_STATE=RUN_NLP; 939 end

940

941 end

942

943 GET_NLP: 944 begin 945 NEXT_STATE=CALC_DIV_PITCH; 946 end

947

948 CALC_DIV_PITCH: 949 begin 950 NEXT_STATE=SET_DIV_PITCH; 951 end

952

137 953 SET_DIV_PITCH: 954 begin 955 if(donediv) 956 begin 957 NEXT_STATE=CALC_WO; 958 end 959 else 960 begin 961 NEXT_STATE=SET_DIV_PITCH; 962 end 963 end

964

965 CALC_WO: 966 begin 967 NEXT_STATE=CALC_DIV_WO; 968 end

969

970 CALC_DIV_WO: 971 begin 972 if(donediv) 973 begin 974 NEXT_STATE=SET_DIV_WO; 975 end 976 else 977 begin 978 NEXT_STATE=CALC_DIV_WO; 979 end 980 end

981

982 SET_DIV_WO: 983 begin 984 NEXT_STATE=CALC_L; 985 end

986

987 CALC_L: 988 begin 989 NEXT_STATE=START_TSPR; 990 end

991

992 START_TSPR: 993 begin 994 NEXT_STATE=RUN_TSPR; 995 end

996

997 RUN_TSPR:

138 998 begin 999 if(donetspr) 1000 begin 1001 NEXT_STATE=GET_TSPR; 1002 end 1003 else 1004 begin 1005 NEXT_STATE=RUN_TSPR; 1006 end 1007 end

1008

1009 GET_TSPR: 1010 begin 1011 NEXT_STATE=START_EA; 1012 end

1013

1014 START_EA: 1015 begin 1016 NEXT_STATE=RUN_EA; 1017 end

1018

1019 RUN_EA: 1020 begin 1021 if(doneea) 1022 begin 1023 NEXT_STATE=GET_EA; 1024 end 1025 else 1026 begin 1027 NEXT_STATE=RUN_EA; 1028 end 1029 end

1030

1031 GET_EA: 1032 begin 1033 NEXT_STATE=START_EVM; 1034 end

1035

1036 START_EVM: 1037 begin 1038 NEXT_STATE=RUN_EVM; 1039 end

1040

1041 RUN_EVM: 1042 begin

139 1043 if(doneevmbe) 1044 begin 1045 NEXT_STATE=GET_EVM; 1046 end 1047 else 1048 begin 1049 NEXT_STATE=RUN_EVM; 1050 end 1051 end

1052

1053 GET_EVM: 1054 begin 1055 NEXT_STATE=DONE; 1056 end

1057

1058 DONE: 1059 begin 1060 NEXT_STATE=START; 1061 end

1062

1063 default: 1064 begin 1065 NEXT_STATE=DONE;

1066

1067 end

1068

1069 endcase 1070 end

1071

1072

1073 always@(posedge clk or negedge rst)// Determine outputs 1074 begin

1075

1076 if(rst == 1’b0) 1077 begin

1078

1079 doneaof <= 1’b0;

1080

1081 end

1082

1083 else 1084 begin 1085 case(STATE)

1086

1087 START:

140 1088 begin 1089 doneaof <= 1’b0;

1090

1091 end

1092

1093 INIT_FOR_1: 1094 begin 1095 i <= 10’d0; 1096 end

1097

1098 CHECK_I_1: 1099 begin

1100

1101 end

1102

1103 SET_ADDR_SN_1: 1104 begin 1105 //addr_sn <=i+ mpitch_by_2; 1106 end

1107

1108 SET_DELAY1: 1109 begin

1110

1111 end

1112

1113 SET_DELAY2: 1114 begin

1115

1116 end

1117

1118 SET_MULT_1: 1119 begin 1120 m1_in1 <= out_sn; 1121 case(i+ mpitch_by_2) 1122 10’d0: 1123 begin 1124 m1_in2 <= w160; 1125 end 1126 10’d1: 1127 begin 1128 m1_in2 <= w161; 1129 end 1130 10’d2: 1131 begin 1132 m1_in2 <= w162;

141 1133 end 1134 10’d3: 1135 begin 1136 m1_in2 <= w163; 1137 end 1138 10’d4: 1139 begin 1140 m1_in2 <= w164; 1141 end 1142 10’d5: 1143 begin 1144 m1_in2 <= w165; 1145 end 1146 10’d6: 1147 begin 1148 m1_in2 <= w166; 1149 end 1150 10’d7: 1151 begin 1152 m1_in2 <= w167; 1153 end 1154 10’d8: 1155 begin 1156 m1_in2 <= w168; 1157 end 1158 10’d9: 1159 begin 1160 m1_in2 <= w169; 1161 end 1162 10’d10: 1163 begin 1164 m1_in2 <= w170; 1165 end 1166 10’d11: 1167 begin 1168 m1_in2 <= w171; 1169 end 1170 10’d12: 1171 begin 1172 m1_in2 <= w172; 1173 end 1174 10’d13: 1175 begin 1176 m1_in2 <= w173; 1177 end

142 1178 10’d14: 1179 begin 1180 m1_in2 <= w174; 1181 end 1182 10’d15: 1183 begin 1184 m1_in2 <= w175; 1185 end 1186 10’d16: 1187 begin 1188 m1_in2 <= w176; 1189 end 1190 10’d17: 1191 begin 1192 m1_in2 <= w177; 1193 end 1194 10’d18: 1195 begin 1196 m1_in2 <= w178; 1197 end 1198 10’d19: 1199 begin 1200 m1_in2 <= w179; 1201 end 1202 10’d20: 1203 begin 1204 m1_in2 <= w180; 1205 end 1206 10’d21: 1207 begin 1208 m1_in2 <= w181; 1209 end 1210 10’d22: 1211 begin 1212 m1_in2 <= w182; 1213 end 1214 10’d23: 1215 begin 1216 m1_in2 <= w183; 1217 end 1218 10’d24: 1219 begin 1220 m1_in2 <= w184; 1221 end 1222 10’d25:

143 1223 begin 1224 m1_in2 <= w185; 1225 end 1226 10’d26: 1227 begin 1228 m1_in2 <= w186; 1229 end 1230 10’d27: 1231 begin 1232 m1_in2 <= w187; 1233 end 1234 10’d28: 1235 begin 1236 m1_in2 <= w188; 1237 end 1238 10’d29: 1239 begin 1240 m1_in2 <= w189; 1241 end 1242 10’d30: 1243 begin 1244 m1_in2 <= w190; 1245 end 1246 10’d31: 1247 begin 1248 m1_in2 <= w191; 1249 end 1250 10’d32: 1251 begin 1252 m1_in2 <= w192; 1253 end 1254 10’d33: 1255 begin 1256 m1_in2 <= w193; 1257 end 1258 10’d34: 1259 begin 1260 m1_in2 <= w194; 1261 end 1262 10’d35: 1263 begin 1264 m1_in2 <= w195; 1265 end 1266 10’d36: 1267 begin

144 1268 m1_in2 <= w196; 1269 end 1270 10’d37: 1271 begin 1272 m1_in2 <= w197; 1273 end 1274 10’d38: 1275 begin 1276 m1_in2 <= w198; 1277 end 1278 10’d39: 1279 begin 1280 m1_in2 <= w199; 1281 end 1282 10’d40: 1283 begin 1284 m1_in2 <= w200; 1285 end 1286 10’d41: 1287 begin 1288 m1_in2 <= w201; 1289 end 1290 10’d42: 1291 begin 1292 m1_in2 <= w202; 1293 end 1294 10’d43: 1295 begin 1296 m1_in2 <= w203; 1297 end 1298 10’d44: 1299 begin 1300 m1_in2 <= w204; 1301 end 1302 10’d45: 1303 begin 1304 m1_in2 <= w205; 1305 end 1306 10’d46: 1307 begin 1308 m1_in2 <= w206; 1309 end 1310 10’d47: 1311 begin 1312 m1_in2 <= w207;

145 1313 end 1314 10’d48: 1315 begin 1316 m1_in2 <= w208; 1317 end 1318 10’d49: 1319 begin 1320 m1_in2 <= w209; 1321 end 1322 10’d50: 1323 begin 1324 m1_in2 <= w210; 1325 end 1326 10’d51: 1327 begin 1328 m1_in2 <= w211; 1329 end 1330 10’d52: 1331 begin 1332 m1_in2 <= w212; 1333 end 1334 10’d53: 1335 begin 1336 m1_in2 <= w213; 1337 end 1338 10’d54: 1339 begin 1340 m1_in2 <= w214; 1341 end 1342 10’d55: 1343 begin 1344 m1_in2 <= w215; 1345 end 1346 10’d56: 1347 begin 1348 m1_in2 <= w216; 1349 end 1350 10’d57: 1351 begin 1352 m1_in2 <= w217; 1353 end 1354 10’d58: 1355 begin 1356 m1_in2 <= w218; 1357 end

146 1358 10’d59: 1359 begin 1360 m1_in2 <= w219; 1361 end 1362 10’d60: 1363 begin 1364 m1_in2 <= w220; 1365 end 1366 10’d61: 1367 begin 1368 m1_in2 <= w221; 1369 end 1370 10’d62: 1371 begin 1372 m1_in2 <= w222; 1373 end 1374 10’d63: 1375 begin 1376 m1_in2 <= w223; 1377 end 1378 10’d64: 1379 begin 1380 m1_in2 <= w224; 1381 end 1382 10’d65: 1383 begin 1384 m1_in2 <= w225; 1385 end 1386 10’d66: 1387 begin 1388 m1_in2 <= w226; 1389 end 1390 10’d67: 1391 begin 1392 m1_in2 <= w227; 1393 end 1394 10’d68: 1395 begin 1396 m1_in2 <= w228; 1397 end 1398 10’d69: 1399 begin 1400 m1_in2 <= w229; 1401 end 1402 10’d70:

147 1403 begin 1404 m1_in2 <= w230; 1405 end 1406 10’d71: 1407 begin 1408 m1_in2 <= w231; 1409 end 1410 10’d72: 1411 begin 1412 m1_in2 <= w232; 1413 end 1414 10’d73: 1415 begin 1416 m1_in2 <= w233; 1417 end 1418 10’d74: 1419 begin 1420 m1_in2 <= w234; 1421 end 1422 10’d75: 1423 begin 1424 m1_in2 <= w235; 1425 end 1426 10’d76: 1427 begin 1428 m1_in2 <= w236; 1429 end 1430 10’d77: 1431 begin 1432 m1_in2 <= w237; 1433 end 1434 10’d78: 1435 begin 1436 m1_in2 <= w238; 1437 end 1438 10’d79: 1439 begin 1440 m1_in2 <= w239; 1441 end 1442 10’d80: 1443 begin 1444 m1_in2 <= w240; 1445 end 1446 10’d81: 1447 begin

148 1448 m1_in2 <= w241; 1449 end 1450 10’d82: 1451 begin 1452 m1_in2 <= w242; 1453 end 1454 10’d83: 1455 begin 1456 m1_in2 <= w243; 1457 end 1458 10’d84: 1459 begin 1460 m1_in2 <= w244; 1461 end 1462 10’d85: 1463 begin 1464 m1_in2 <= w245; 1465 end 1466 10’d86: 1467 begin 1468 m1_in2 <= w246; 1469 end 1470 10’d87: 1471 begin 1472 m1_in2 <= w247; 1473 end 1474 10’d88: 1475 begin 1476 m1_in2 <= w248; 1477 end 1478 10’d89: 1479 begin 1480 m1_in2 <= w249; 1481 end 1482 10’d90: 1483 begin 1484 m1_in2 <= w250; 1485 end 1486 10’d91: 1487 begin 1488 m1_in2 <= w251; 1489 end 1490 10’d92: 1491 begin 1492 m1_in2 <= w252;

149 1493 end 1494 10’d93: 1495 begin 1496 m1_in2 <= w253; 1497 end 1498 10’d94: 1499 begin 1500 m1_in2 <= w254; 1501 end 1502 10’d95: 1503 begin 1504 m1_in2 <= w255; 1505 end 1506 10’d96: 1507 begin 1508 m1_in2 <= w256; 1509 end 1510 10’d97: 1511 begin 1512 m1_in2 <= w257; 1513 end 1514 10’d98: 1515 begin 1516 m1_in2 <= w258; 1517 end 1518 10’d99: 1519 begin 1520 m1_in2 <= w259; 1521 end 1522 10’d100: 1523 begin 1524 m1_in2 <= w260; 1525 end 1526 10’d101: 1527 begin 1528 m1_in2 <= w261; 1529 end 1530 10’d102: 1531 begin 1532 m1_in2 <= w262; 1533 end 1534 10’d103: 1535 begin 1536 m1_in2 <= w263; 1537 end

150 1538 10’d104: 1539 begin 1540 m1_in2 <= w264; 1541 end 1542 10’d105: 1543 begin 1544 m1_in2 <= w265; 1545 end 1546 10’d106: 1547 begin 1548 m1_in2 <= w266; 1549 end 1550 10’d107: 1551 begin 1552 m1_in2 <= w267; 1553 end 1554 10’d108: 1555 begin 1556 m1_in2 <= w268; 1557 end 1558 10’d109: 1559 begin 1560 m1_in2 <= w269; 1561 end 1562 10’d110: 1563 begin 1564 m1_in2 <= w270; 1565 end 1566 10’d111: 1567 begin 1568 m1_in2 <= w271; 1569 end 1570 10’d112: 1571 begin 1572 m1_in2 <= w272; 1573 end 1574 10’d113: 1575 begin 1576 m1_in2 <= w273; 1577 end 1578 10’d114: 1579 begin 1580 m1_in2 <= w274; 1581 end 1582 10’d115:

151 1583 begin 1584 m1_in2 <= w275; 1585 end 1586 10’d116: 1587 begin 1588 m1_in2 <= w276; 1589 end 1590 10’d117: 1591 begin 1592 m1_in2 <= w277; 1593 end 1594 10’d118: 1595 begin 1596 m1_in2 <= w278; 1597 end 1598 10’d119: 1599 begin 1600 m1_in2 <= w279; 1601 end 1602 10’d120: 1603 begin 1604 m1_in2 <= w280; 1605 end 1606 10’d121: 1607 begin 1608 m1_in2 <= w281; 1609 end 1610 10’d122: 1611 begin 1612 m1_in2 <= w282; 1613 end 1614 10’d123: 1615 begin 1616 m1_in2 <= w283; 1617 end 1618 10’d124: 1619 begin 1620 m1_in2 <= w284; 1621 end 1622 10’d125: 1623 begin 1624 m1_in2 <= w285; 1625 end 1626 10’d126: 1627 begin

152 1628 m1_in2 <= w286; 1629 end 1630 10’d127: 1631 begin 1632 m1_in2 <= w287; 1633 end 1634 10’d128: 1635 begin 1636 m1_in2 <= w288; 1637 end 1638 10’d129: 1639 begin 1640 m1_in2 <= w289; 1641 end 1642 10’d130: 1643 begin 1644 m1_in2 <= w290; 1645 end 1646 10’d131: 1647 begin 1648 m1_in2 <= w291; 1649 end 1650 10’d132: 1651 begin 1652 m1_in2 <= w292; 1653 end 1654 10’d133: 1655 begin 1656 m1_in2 <= w293; 1657 end 1658 10’d134: 1659 begin 1660 m1_in2 <= w294; 1661 end 1662 10’d135: 1663 begin 1664 m1_in2 <= w295; 1665 end 1666 10’d136: 1667 begin 1668 m1_in2 <= w296; 1669 end 1670 10’d137: 1671 begin 1672 m1_in2 <= w297;

153 1673 end 1674 10’d138: 1675 begin 1676 m1_in2 <= w298; 1677 end 1678 endcase

1679

1680 addr_sw_real <=i; 1681 we_sw <= 1’b1; 1682 re_sw <= 1’b0; 1683 end

1684

1685 SET_SW_REAL_1: 1686 begin 1687 write_sw_real <= m1_out; 1688 end

1689

1690 INCR_I_1: 1691 begin 1692 i <=i + 10’d1; 1693 end

1694

1695 INIT_FOR_2: 1696 begin 1697 i <= 10’d0; 1698 end

1699

1700 CHECK_I_2: 1701 begin

1702

1703 end

1704

1705 SET_ADDR_SN_2: 1706 begin 1707 //addr_sn <=i+ 10’d21; 1708 end

1709

1710 SET_DELAY3: 1711 begin

1712

1713 end

1714

1715 SET_DELAY4: 1716 begin

1717

154 1718 end

1719

1720 SET_MULT_2: 1721 begin 1722 m1_in1 <= out_sn; 1723 case(i + 10’d21) 1724 10’d0: 1725 begin 1726 m1_in2 <= w21; 1727 end 1728 10’d1: 1729 begin 1730 m1_in2 <= w22; 1731 end 1732 10’d2: 1733 begin 1734 m1_in2 <= w23; 1735 end 1736 10’d3: 1737 begin 1738 m1_in2 <= w24; 1739 end 1740 10’d4: 1741 begin 1742 m1_in2 <= w25; 1743 end 1744 10’d5: 1745 begin 1746 m1_in2 <= w26; 1747 end 1748 10’d6: 1749 begin 1750 m1_in2 <= w27; 1751 end 1752 10’d7: 1753 begin 1754 m1_in2 <= w28; 1755 end 1756 10’d8: 1757 begin 1758 m1_in2 <= w29; 1759 end 1760 10’d9: 1761 begin 1762 m1_in2 <= w30;

155 1763 end 1764 10’d10: 1765 begin 1766 m1_in2 <= w31; 1767 end 1768 10’d11: 1769 begin 1770 m1_in2 <= w32; 1771 end 1772 10’d12: 1773 begin 1774 m1_in2 <= w33; 1775 end 1776 10’d13: 1777 begin 1778 m1_in2 <= w34; 1779 end 1780 10’d14: 1781 begin 1782 m1_in2 <= w35; 1783 end 1784 10’d15: 1785 begin 1786 m1_in2 <= w36; 1787 end 1788 10’d16: 1789 begin 1790 m1_in2 <= w37; 1791 end 1792 10’d17: 1793 begin 1794 m1_in2 <= w38; 1795 end 1796 10’d18: 1797 begin 1798 m1_in2 <= w39; 1799 end 1800 10’d19: 1801 begin 1802 m1_in2 <= w40; 1803 end 1804 10’d20: 1805 begin 1806 m1_in2 <= w41; 1807 end

156 1808 10’d21: 1809 begin 1810 m1_in2 <= w42; 1811 end 1812 10’d22: 1813 begin 1814 m1_in2 <= w43; 1815 end 1816 10’d23: 1817 begin 1818 m1_in2 <= w44; 1819 end 1820 10’d24: 1821 begin 1822 m1_in2 <= w45; 1823 end 1824 10’d25: 1825 begin 1826 m1_in2 <= w46; 1827 end 1828 10’d26: 1829 begin 1830 m1_in2 <= w47; 1831 end 1832 10’d27: 1833 begin 1834 m1_in2 <= w48; 1835 end 1836 10’d28: 1837 begin 1838 m1_in2 <= w49; 1839 end 1840 10’d29: 1841 begin 1842 m1_in2 <= w50; 1843 end 1844 10’d30: 1845 begin 1846 m1_in2 <= w51; 1847 end 1848 10’d31: 1849 begin 1850 m1_in2 <= w52; 1851 end 1852 10’d32:

157 1853 begin 1854 m1_in2 <= w53; 1855 end 1856 10’d33: 1857 begin 1858 m1_in2 <= w54; 1859 end 1860 10’d34: 1861 begin 1862 m1_in2 <= w55; 1863 end 1864 10’d35: 1865 begin 1866 m1_in2 <= w56; 1867 end 1868 10’d36: 1869 begin 1870 m1_in2 <= w57; 1871 end 1872 10’d37: 1873 begin 1874 m1_in2 <= w58; 1875 end 1876 10’d38: 1877 begin 1878 m1_in2 <= w59; 1879 end 1880 10’d39: 1881 begin 1882 m1_in2 <= w60; 1883 end 1884 10’d40: 1885 begin 1886 m1_in2 <= w61; 1887 end 1888 10’d41: 1889 begin 1890 m1_in2 <= w62; 1891 end 1892 10’d42: 1893 begin 1894 m1_in2 <= w63; 1895 end 1896 10’d43: 1897 begin

158 1898 m1_in2 <= w64; 1899 end 1900 10’d44: 1901 begin 1902 m1_in2 <= w65; 1903 end 1904 10’d45: 1905 begin 1906 m1_in2 <= w66; 1907 end 1908 10’d46: 1909 begin 1910 m1_in2 <= w67; 1911 end 1912 10’d47: 1913 begin 1914 m1_in2 <= w68; 1915 end 1916 10’d48: 1917 begin 1918 m1_in2 <= w69; 1919 end 1920 10’d49: 1921 begin 1922 m1_in2 <= w70; 1923 end 1924 10’d50: 1925 begin 1926 m1_in2 <= w71; 1927 end 1928 10’d51: 1929 begin 1930 m1_in2 <= w72; 1931 end 1932 10’d52: 1933 begin 1934 m1_in2 <= w73; 1935 end 1936 10’d53: 1937 begin 1938 m1_in2 <= w74; 1939 end 1940 10’d54: 1941 begin 1942 m1_in2 <= w75;

159 1943 end 1944 10’d55: 1945 begin 1946 m1_in2 <= w76; 1947 end 1948 10’d56: 1949 begin 1950 m1_in2 <= w77; 1951 end 1952 10’d57: 1953 begin 1954 m1_in2 <= w78; 1955 end 1956 10’d58: 1957 begin 1958 m1_in2 <= w79; 1959 end 1960 10’d59: 1961 begin 1962 m1_in2 <= w80; 1963 end 1964 10’d60: 1965 begin 1966 m1_in2 <= w81; 1967 end 1968 10’d61: 1969 begin 1970 m1_in2 <= w82; 1971 end 1972 10’d62: 1973 begin 1974 m1_in2 <= w83; 1975 end 1976 10’d63: 1977 begin 1978 m1_in2 <= w84; 1979 end 1980 10’d64: 1981 begin 1982 m1_in2 <= w85; 1983 end 1984 10’d65: 1985 begin 1986 m1_in2 <= w86; 1987 end

160 1988 10’d66: 1989 begin 1990 m1_in2 <= w87; 1991 end 1992 10’d67: 1993 begin 1994 m1_in2 <= w88; 1995 end 1996 10’d68: 1997 begin 1998 m1_in2 <= w89; 1999 end 2000 10’d69: 2001 begin 2002 m1_in2 <= w90; 2003 end 2004 10’d70: 2005 begin 2006 m1_in2 <= w91; 2007 end 2008 10’d71: 2009 begin 2010 m1_in2 <= w92; 2011 end 2012 10’d72: 2013 begin 2014 m1_in2 <= w93; 2015 end 2016 10’d73: 2017 begin 2018 m1_in2 <= w94; 2019 end 2020 10’d74: 2021 begin 2022 m1_in2 <= w95; 2023 end 2024 10’d75: 2025 begin 2026 m1_in2 <= w96; 2027 end 2028 10’d76: 2029 begin 2030 m1_in2 <= w97; 2031 end 2032 10’d77:

161 2033 begin 2034 m1_in2 <= w98; 2035 end 2036 10’d78: 2037 begin 2038 m1_in2 <= w99; 2039 end 2040 10’d79: 2041 begin 2042 m1_in2 <= w100; 2043 end 2044 10’d80: 2045 begin 2046 m1_in2 <= w101; 2047 end 2048 10’d81: 2049 begin 2050 m1_in2 <= w102; 2051 end 2052 10’d82: 2053 begin 2054 m1_in2 <= w103; 2055 end 2056 10’d83: 2057 begin 2058 m1_in2 <= w104; 2059 end 2060 10’d84: 2061 begin 2062 m1_in2 <= w105; 2063 end 2064 10’d85: 2065 begin 2066 m1_in2 <= w106; 2067 end 2068 10’d86: 2069 begin 2070 m1_in2 <= w107; 2071 end 2072 10’d87: 2073 begin 2074 m1_in2 <= w108; 2075 end 2076 10’d88: 2077 begin

162 2078 m1_in2 <= w109; 2079 end 2080 10’d89: 2081 begin 2082 m1_in2 <= w110; 2083 end 2084 10’d90: 2085 begin 2086 m1_in2 <= w111; 2087 end 2088 10’d91: 2089 begin 2090 m1_in2 <= w112; 2091 end 2092 10’d92: 2093 begin 2094 m1_in2 <= w113; 2095 end 2096 10’d93: 2097 begin 2098 m1_in2 <= w114; 2099 end 2100 10’d94: 2101 begin 2102 m1_in2 <= w115; 2103 end 2104 10’d95: 2105 begin 2106 m1_in2 <= w116; 2107 end 2108 10’d96: 2109 begin 2110 m1_in2 <= w117; 2111 end 2112 10’d97: 2113 begin 2114 m1_in2 <= w118; 2115 end 2116 10’d98: 2117 begin 2118 m1_in2 <= w119; 2119 end 2120 10’d99: 2121 begin 2122 m1_in2 <= w120;

163 2123 end 2124 10’d100: 2125 begin 2126 m1_in2 <= w121; 2127 end 2128 10’d101: 2129 begin 2130 m1_in2 <= w122; 2131 end 2132 10’d102: 2133 begin 2134 m1_in2 <= w123; 2135 end 2136 10’d103: 2137 begin 2138 m1_in2 <= w124; 2139 end 2140 10’d104: 2141 begin 2142 m1_in2 <= w125; 2143 end 2144 10’d105: 2145 begin 2146 m1_in2 <= w126; 2147 end 2148 10’d106: 2149 begin 2150 m1_in2 <= w127; 2151 end 2152 10’d107: 2153 begin 2154 m1_in2 <= w128; 2155 end 2156 10’d108: 2157 begin 2158 m1_in2 <= w129; 2159 end 2160 10’d109: 2161 begin 2162 m1_in2 <= w130; 2163 end 2164 10’d110: 2165 begin 2166 m1_in2 <= w131; 2167 end

164 2168 10’d111: 2169 begin 2170 m1_in2 <= w132; 2171 end 2172 10’d112: 2173 begin 2174 m1_in2 <= w133; 2175 end 2176 10’d113: 2177 begin 2178 m1_in2 <= w134; 2179 end 2180 10’d114: 2181 begin 2182 m1_in2 <= w135; 2183 end 2184 10’d115: 2185 begin 2186 m1_in2 <= w136; 2187 end 2188 10’d116: 2189 begin 2190 m1_in2 <= w137; 2191 end 2192 10’d117: 2193 begin 2194 m1_in2 <= w138; 2195 end 2196 10’d118: 2197 begin 2198 m1_in2 <= w139; 2199 end 2200 10’d119: 2201 begin 2202 m1_in2 <= w140; 2203 end 2204 10’d120: 2205 begin 2206 m1_in2 <= w141; 2207 end 2208 10’d121: 2209 begin 2210 m1_in2 <= w142; 2211 end 2212 10’d122:

165 2213 begin 2214 m1_in2 <= w143; 2215 end 2216 10’d123: 2217 begin 2218 m1_in2 <= w144; 2219 end 2220 10’d124: 2221 begin 2222 m1_in2 <= w145; 2223 end 2224 10’d125: 2225 begin 2226 m1_in2 <= w146; 2227 end 2228 10’d126: 2229 begin 2230 m1_in2 <= w147; 2231 end 2232 10’d127: 2233 begin 2234 m1_in2 <= w148; 2235 end 2236 10’d128: 2237 begin 2238 m1_in2 <= w149; 2239 end 2240 10’d129: 2241 begin 2242 m1_in2 <= w150; 2243 end 2244 10’d130: 2245 begin 2246 m1_in2 <= w151; 2247 end 2248 10’d131: 2249 begin 2250 m1_in2 <= w152; 2251 end 2252 10’d132: 2253 begin 2254 m1_in2 <= w153; 2255 end 2256 10’d133: 2257 begin

166 2258 m1_in2 <= w154; 2259 end 2260 10’d134: 2261 begin 2262 m1_in2 <= w155; 2263 end 2264 10’d135: 2265 begin 2266 m1_in2 <= w156; 2267 end 2268 10’d136: 2269 begin 2270 m1_in2 <= w157; 2271 end 2272 10’d137: 2273 begin 2274 m1_in2 <= w158; 2275 end 2276 10’d138: 2277 begin 2278 m1_in2 <= w159; 2279 end 2280 endcase 2281 addr_sw_real <= fft_enc- nw_by_2+i; 2282 we_sw <= 1’b1; 2283 re_sw <= 1’b0; 2284 end

2285

2286 SET_SW_REAL_2: 2287 begin 2288 write_sw_real <= m1_out; 2289 end

2290

2291 INCR_I_2: 2292 begin 2293 i <=i + 10’d1; 2294 end

2295

2296 START_DFT: 2297 begin 2298 startfft <= 1’b1;

2299

2300 re_sw <= 1’b1; 2301 we_sw <= 1’b0;

2302

167 2303 re_sw_fft <= 1’b0; 2304 we_sw_fft <= 1’b1;

2305

2306 end

2307

2308 RUN_DFT: 2309 begin 2310 startfft <= 1’b0; 2311 addr_sw_real <= fft_addr_in_real; 2312 addr_sw_imag <= fft_addr_in_imag;

2313

2314 addr_sw_fft_real <= fft_addr_out_real; 2315 addr_sw_fft_imag <= fft_addr_out_imag;

2316

2317 write_sw_fft_real <= fft_write_fft_real; 2318 write_sw_fft_imag <= fft_write_fft_imag;

2319

2320 end

2321

2322 START_NLP: 2323 begin 2324 startnlp <= 1’b1;

2325

2326 /* nlp_mem_x <= 80’h2A40000; 2327 nlp_mem_y <= 80’hCBDE96; 2328 prev_f0 <= {16’d50,16’d0};*/// to test aof2

2329

2330 /* 2331 nlp_mem_x <= 80’d0; 2332 nlp_mem_y <= 80’d0; 2333 prev_f0 <= {16’d50,16’d0};*/// to test aof1

2334

2335 nlp_mem_x <= mem_x_in; 2336 nlp_mem_y <= mem_y_in; 2337 prev_f0 <= in_prev_f0;

2338

2339

2340 end

2341

2342 RUN_NLP: 2343 begin 2344 startnlp <= 1’b0; 2345 end

2346

2347 GET_NLP:

168 2348 begin 2349 mem_x_out <= nlp_mem_x_out; 2350 mem_y_out <= nlp_mem_y_out; 2351 out_best_f0 <= best_f0; 2352 out_prev_f0 <= o_prev_f0; 2353 startdiv <= 1’b1; 2354 end

2355

2356 CALC_DIV_PITCH: 2357 begin 2358 div_in <= pitch; 2359 startdiv <= 1’b0; 2360 end

2361

2362 SET_DIV_PITCH: 2363 begin 2364 one_by_pitch <= div_ans; 2365 end

2366

2367 CALC_WO: 2368 begin 2369 m1_in1 <=TWO_PI; 2370 m1_in2 <= one_by_pitch; 2371 startdiv <= 1’b1; 2372 end

2373

2374 CALC_DIV_WO: 2375 begin 2376 Wo_in <= m1_out; 2377 aof_w0_out <= m1_out; 2378 div_in <= m1_out; 2379 startdiv <= 1’b0; 2380 end

2381

2382 SET_DIV_WO: 2383 begin 2384 one_by_wo <= div_ans; 2385 end

2386

2387 CALC_L: 2388 begin 2389 m1_in1 <=PI; 2390 m1_in2 <= one_by_wo; 2391 end

2392

169 2393

2394 START_TSPR: 2395 begin 2396 starttspr <= 1’b1; 2397 re_sw_fft <= 1’b1; 2398 we_sw_fft <= 1’b0;

2399

2400 L_in <= m1_out;//10’d79;

2401

2402 end

2403

2404 RUN_TSPR: 2405 begin 2406 starttspr <= 1’b0; 2407 out_real <= out_sw_fft_real; 2408 out_imag <= out_sw_fft_imag; 2409 addr_sw_fft_real <= addr_real; 2410 addr_sw_fft_imag <= addr_imag;

2411

2412 end

2413

2414 GET_TSPR: 2415 begin 2416 ea_L <= L_out[25:16]; 2417 ea_Wo <= Wo_out; 2418 end

2419

2420 START_EA: 2421 begin 2422 startea <= 1’b1; 2423 we_am <= 1’b1; 2424 re_am <= 1’b0;

2425

2426 end

2427

2428 RUN_EA: 2429 begin 2430 startea <= 1’b0; 2431 ea_out_real <= out_sw_fft_real; 2432 ea_out_imag <= out_sw_fft_imag; 2433 addr_sw_fft_real <= ea_addr_real; 2434 addr_sw_fft_imag <= ea_addr_imag; 2435 addr_a <= ea_addr_a; 2436 write_data_a <= ea_write_data_a;

2437

170 2438 end

2439

2440 GET_EA: 2441 begin 2442 evm_L_in <= L_out[25:16]; 2443 evm_Wo_in <= Wo_out;

2444

2445 end

2446

2447 START_EVM: 2448 begin 2449 startevmbe <= 1’b1; 2450 we_am <= 1’b0; 2451 re_am <= 1’b1; 2452 end

2453

2454 RUN_EVM: 2455 begin 2456 startevmbe <= 1’b0; 2457 evm_out_sw_real <= out_sw_fft_real; 2458 evm_out_sw_imag <= out_sw_fft_imag; 2459 addr_sw_fft_real <= evm_addr_sw_real; 2460 addr_sw_fft_imag <= evm_addr_sw_imag; 2461 addr_a <= evm_addr_am; 2462 evm_out_am <= out_a;

2463

2464 end

2465

2466 GET_EVM: 2467 begin 2468 voiced_bit <= evm_voiced; 2469 nlp_pitch <= pitch; 2470 end

2471

2472 DONE: 2473 begin 2474 doneaof <= 1’b1; 2475 end

2476

2477 endcase 2478 end

2479

2480 end

2481

2482

171 2483 endmodule

B.4 speech to uq lsps.v

1 /* 2 * Module- speech_to_uq_lsps_ 3 * Top module- codec2_encode_2400 4 * Project- CODEC2_ENCODE_2400

7 * Developer- SanthiyaS 8 * Date- Thu Mar 14 10:47:50 2019 9 * 10 * Description- 11 * Inputs- 12 * Simulation- 13 *32 bits fixed point representation 14 S-E-M 15 1- 15- 16 16 */

19 module speech_to_uq_lsps( startspeech,clk,rst,out_sn, 20 E,lsp0,lsp1,lsp2,lsp3,lsp4,lsp5,lsp6,lsp7,lsp8,lsp9,addr_sn, 21 donespeech 22 //,c_ak0,c_ak1,c_ak2,c_ak3,c_ak4,c_ak5,c_ak6,c_ak7,c_ak8,c_ak9,c_ak10

24 );

27 //------28 //-- Input/Output Declarations-- 29 //------30 parameterN = 32; 31 parameterQ = 16;

33 parameter N1 = 80; 34 parameter Q1 = 16;

36 parameter N2 = 48; 37 parameter Q2 = 32;

39 parameter N3 = 50; 40 parameter Q3 = 32;

172 41

42 parameter N4 = 34; 43 parameter Q4 = 16;

45 input startspeech,clk,rst; 46 input[N-1:0] out_sn; 47 output reg[N-1:0]E; 48 output reg[N-1:0] lsp0,lsp1,lsp2,lsp3,lsp4,lsp5,lsp6,lsp7,lsp8,lsp9; 49 output reg [9:0] addr_sn; 50 output reg donespeech; 51 //output reg [8:0] c_sn_addr1;

53 reg[N-1:0] check_corr; 54 reg[N-1:0] check_ak0_lev,check_ak1_lev;

56 reg[N-1:0] c_ak0,c_ak1,c_ak2,c_ak3,c_ak4,c_ak5 57 ,c_ak6,c_ak7,c_ak8,c_ak9,c_ak10; 58 /* reg [9:0] addr_sn; 59 wire[N-1:0] out_sn; 60 RAM_c2_speech_sn c2_sn(addr_sn,clk,,1,0,out_sn);// frame0- 160 samples */

63 //------64 //-- State& Reg Declarations-- 65 //------

67 parameterSTART =7’d0, 68 INIT =7’d1, 69 SET_READ_SN =7’d2, 70 SET_AUTOCORRELATE =7’d3, 71 SET_LEVINSON =7’d4, 72 INIT_LOOP =7’d5, 73 PRE_CALC_E =7’d6, 74 CALC_E =7’d7, 75 INCR_I =7’d8, 76 CHECK_I =7’d9, 77 READ_AK =7’d10, 78 SET_LPC_TO_LSP =7’d11, 79 DONE =7’d12, 80 INIT_FOR_1 =7’d13, 81 CHECK_I1 =7’d14, 82 SET_ADDR_SN =7’d15, 83 SET_DELAY1 =7’d16, 84 MULT_SN_W =7’d17,

173 85 SQUARE_WN =7’d18, 86 SUM_SMALL_E =7’d19, 87 SET_SMALL_E =7’d20, 88 INCR_I1 =7’d21, 89 RUN_LEVINSON =7’d22, 90 GET_LEVINSON =7’d23, 91 SET_DELAY2 =7’d24, 92 INIT_FOR_AC =7’d25, 93 CHECK_AC =7’d26, 94 INIT_R =7’d27, 95 INIT_FOR_AC1 =7’d28, 96 CHECK_AC1 =7’d29, 97 AUTO_CORR_WN =7’d30, 98 SET_WN_CORR =7’d31, 99 ADD_RN =7’d32, 100 SET_RN =7’d33, 101 INCR_AC1 =7’d34, 102 INCR_AC =7’d35, 103 SET_D_AC1 =7’d36, 104 SET_D_AC2 =7’d37, 105 SET_M1_AC =7’d38, 106 SET_M2_AC_ADDR =7’d39, 107 SET_D_AC3 =7’d40, 108 SET_D_AC4 =7’d41, 109 SET_M2_AC =7’d42, 110 INIT_READ_LPC =7’d43, 111 CHECK_LPC =7’d44, 112 READ_LPC_ADDR =7’d45, 113 SET_D_LPC1 =7’d46, 114 SET_D_LPC2 =7’d47, 115 GET_LPC_TO_AK =7’d48, 116 INCR_LPC =7’d49, 117 INIT_AK_UPDATE =7’d50, 118 CHECK_AK =7’d51, 119 UPDATE_AK =7’d52, 120 SET_AK =7’d53, 121 INCR_AK =7’d54, 122 RUN_LTL =7’d55, 123 GET_LTL =7’d56, 124 SQUARE_WN_2 =7’d57;

125

126

127 reg [6:0]STATE,NEXT_STATE;

128

129

174 130 parameter[N-1:0] powf0 = {15’b0,1’b1,16’b0}, 131 powf1 = {16’b0,16’b1111111001110110}, 132 powf2 = {16’b0,16’b1111110011101111}, 133 powf3 = {16’b0,16’b1111101101101011}, 134 powf4 = {16’b0,16’b1111100111101001}, 135 powf5 = {16’b0,16’b1111100001101001}, 136 powf6 = {16’b0,16’b1111011011101011}, 137 powf7 = {16’b0,16’b1111010101110000}, 138 powf8 = {16’b0,16’b1111001111110111}, 139 powf9 = {16’b0,16’b1111001010000000}, 140 powf10 = {16’b0,16’b1111000100001100};

141

142

143 //------144 //-- Module Instantiations-- 145 //------

146

147

148 reg [3:0]i; 149 reg [9:0] i1,ac,ac1; 150 reg[N-1:0] m1_in1,m1_in2,a1_in1,a1_in2; 151 wire[N-1:0] m1_out,a1_out; 152 reg[N-1:0] ak0,ak1,ak2,ak3,ak4,ak5,ak6,ak7,ak8,ak9,ak10;

153

154 reg[N4-1:0] Rn0,Rn1,Rn2,Rn3,Rn4,Rn5,Rn6,Rn7,Rn8,Rn9,Rn10;

155

156 wire [9:0] sn_addr1; 157 reg[N-1:0] sn_read_data1; 158 reg startac; 159 wire doneac;

160

161 reg [9:0] lp,ak;

162

163 reg[N2-1:0] wn_corr; 164 reg[N3-1:0]e;

165

166 reg[N2-1:0] ms1_in1,ms1_in2,ms2_in1,ms2_in2,as1_in1,as1_in2; 167 wire[N2-1:0] ms1_out,ms2_out,as1_out; 168 reg[N3-1:0] as2_in1,as2_in2; 169 wire[N3-1:0] as2_out;

170

171 reg[N4-1:0] m2_in1,m2_in2; 172 wire[N4-1:0] m2_out;

173

174

175 175 qadd#(Q,N) adder1(a1_in1,a1_in2,a1_out);

176

177 qmult#(Q,N) qmult1(m1_in1,m1_in2,m1_out); 178 qmult#(Q4,N4) qmult_34(m2_in1,m2_in2,m2_out);

179

180 qmult#(Q2,N2) qmult_48_1(ms1_in1,ms1_in2,ms1_out); 181 //qmult#(Q2,N2) qmult_48_2(ms2_in1,ms2_in2,ms2_out); 182 qadd#(Q2,N2) adder_48_1(as1_in1,as1_in2,as1_out); 183 qadd#(Q3,N3) adder_50_1(as2_in1,as2_in2,as2_out);

184

185 /*------autocorrelate module------*/ 186 //RAM_autocorrelate_Sn ram1_sn(sn_addr1,clk,,1,0,sn_read_data1); 187 //RAM_autocorrelate_Sn ram2_sn(sn_addr2,clk,,1,0,sn_read_data2);

188

189 reg [9:0] addr_wn; 190 reg[N2-1:0] write_wn; 191 reg we_wn, re_wn; 192 wire[N2-1:0] read_wn_out;

193

194 RAM_ac_Wn_48 RAM_ac_Wn_module(addr_wn, clk, write_wn,; 195 //re_wn, we_wn, read_wn_out) 196 //autocorrelate_rn_ram auto_mod(startac,clk,rst,sn_read_data1, 197 // Rn0,Rn1,Rn2,Rn3,Rn4,Rn5, 198 // Rn6,Rn7,Rn8,Rn9,Rn10,sn_addr1,doneac); 199 //

200

201

202 /*------RAM_ld_lpcs module------*/ 203 /*------for storing lpc values from levinson durbin module------*/

204

205 wire [3:0] ld_addr_ld,ld_in_lpc; 206 wire[N-1:0] in_lpc; 207 reg re_ld,we_ld; 208 wire[N-1:0] out_lpc; 209 reg [3:0] addr_ld;

210

211 RAM_ld_lpcs RAM_ld(addr_ld,clk,in_lpc,re_ld,we_ld,out_lpc);

212

213 /*------levinson_durbin module------*/

214

215 reg startld; 216 reg[N3-1:0] R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10; 217 reg[N4-1:0] ld_R0,ld_R1,ld_R2,ld_R3,ld_R4,ld_R5, 218 ld_R6,ld_R7,ld_R8,ld_R9,ld_R10; 219 wire doneld;

176 220 wire[N-1:0] check_ak0,check_ak1;

221

222

223 levinson_durbin_3mult lev_dur_module(startld,clk,rst,ld_R0 224 ,ld_R1,ld_R2,ld_R3,ld_R4,ld_R5, 225 ld_R6,ld_R7,ld_R8,ld_R9,ld_R10,in_lpc,ld_addr_ld,doneld);

226

227

228

229 /*------dummyRAM for speech module------*/

230

231 /* reg [9:0] addr_sn; 232 wire[N-1:0] out_sn;

233

234 RAM_speech ram_sn_module(addr_sn,clk,,1,0,out_sn);*/

235

236 /*------RAM_ak------*/ 237 /* reg [3:0] ak_addr; 238 reg[N-1:0] write_ak; 239 reg re_ak,we_ak; 240 wire[N-1:0] read_ak_out;

241

242 RAM_ak module_RAM_ak(ak_addr,clk,write_ak,re_ak,we_ak,read_ak_out);*/

243

244 /*------lpc_to_lsp------*/

245

246 reg startltl; 247 wire[N-1:0] freq0,freq1,freq2,freq3,freq4,freq5,freq6,freq7,freq8,freq9; 248 wire [3:0] ltl_ak_addr; 249 reg[N-1:0] ltl_ak_out; 250 reg[N-1:0] ll_ak0,ll_ak1,ll_ak2,ll_ak3,ll_ak4,ll_ak5,ll_ak6, 251 ll_ak7,ll_ak8,ll_ak9,ll_ak10; 252 wire doneltl;

253

254 lpc_to_lsp ltl_module(startltl,clk,rst,ltl_ak_out, 255 ll_ak0,ll_ak1,ll_ak2,ll_ak3,ll_ak4,ll_ak5,ll_ak6,ll_ak7,ll_ak8,ll_ak9,ll_ak10, 256 freq0,freq1,freq2,freq3,freq4,freq5,freq6,freq7,freq8,freq9, 257 ltl_ak_addr,doneltl);

258

259 /*------ROM_w------*/ 260 reg [9:0] addr_speech_w; 261 wire[N2-1:0] data_out_speech_w;

262

263 ROM_speech_w_48 speech_w(addr_speech_w, data_out_speech_w);

264

177 265

266 //------267 //-- Begin Declarations& Coding-- 268 //------

269

270 always@(posedge clk or negedge rst)// DetermineSTATE 271 begin

272

273 if(rst == 1’b0) 274 STATE <=START; 275 else 276 STATE <=NEXT_STATE;

277

278 end

279

280

281 /* always@(*) 282 begin 283 case(STATE) 284 RUN_LEVINSON: 285 begin 286 addr_ld= ld_addr_ld; 287 end

288

289 READ_LPC_ADDR: 290 begin 291 addr_ld= lp; 292 end

293

294 default: 295 begin 296 // addr_ld= 4’d0; 297 end

298

299 endcase

300

301 end*/

302

303

304 always@(*)// DetermineNEXT_STATE 305 begin 306 case(STATE)

307

308 START: 309 begin

178 310 if(startspeech) 311 begin 312 NEXT_STATE=INIT; 313 end 314 else 315 begin 316 NEXT_STATE=START; 317 end 318 end

319

320 INIT: 321 begin 322 NEXT_STATE= INIT_FOR_1; 323 end

324

325 INIT_FOR_1: 326 begin 327 NEXT_STATE= CHECK_I1; 328 end

329

330 CHECK_I1: 331 begin 332 if(i1 < 10’d320)//fix this 333 begin 334 NEXT_STATE=SET_ADDR_SN; 335 end 336 else 337 begin 338 NEXT_STATE=INIT_FOR_AC; 339 end 340 end

341

342 SET_ADDR_SN: 343 begin 344 NEXT_STATE= SET_DELAY1; 345 end

346

347 SET_DELAY1: 348 begin 349 NEXT_STATE= SET_DELAY2; 350 end

351

352 SET_DELAY2: 353 begin 354 NEXT_STATE=MULT_SN_W;

179 355 end

356

357 MULT_SN_W: 358 begin 359 NEXT_STATE=SQUARE_WN; 360 end

361

362 SQUARE_WN: 363 begin 364 NEXT_STATE= SQUARE_WN_2; 365 end

366

367 SQUARE_WN_2: 368 begin 369 NEXT_STATE=SUM_SMALL_E; 370 end

371

372 SUM_SMALL_E: 373 begin 374 NEXT_STATE=SET_SMALL_E; 375 end

376

377 SET_SMALL_E: 378 begin 379 NEXT_STATE= INCR_I1; 380 end

381

382 INCR_I1: 383 begin 384 NEXT_STATE= CHECK_I1; 385 end

386

387 INIT_FOR_AC: 388 begin 389 NEXT_STATE=CHECK_AC; 390 end

391

392 CHECK_AC: 393 begin 394 if(ac <= 10’d10) 395 begin 396 NEXT_STATE=INIT_R; 397 end 398 else 399 begin

180 400 NEXT_STATE=SET_LEVINSON; 401 end 402 end

403

404 INIT_R: 405 begin 406 NEXT_STATE= INIT_FOR_AC1; 407 end

408

409 INIT_FOR_AC1: 410 begin 411 NEXT_STATE= CHECK_AC1; 412 end

413

414 CHECK_AC1: 415 begin 416 if(ac1 < 10’d320- ac) 417 begin 418 NEXT_STATE=AUTO_CORR_WN; 419 end 420 else 421 begin 422 NEXT_STATE=INCR_AC; 423 end 424 end

425

426 AUTO_CORR_WN: 427 begin 428 NEXT_STATE= SET_D_AC1; 429 end

430

431 SET_D_AC1: 432 begin 433 NEXT_STATE= SET_D_AC2; 434 end

435

436 SET_D_AC2: 437 begin 438 NEXT_STATE= SET_M1_AC; 439 end

440

441 SET_M1_AC: 442 begin 443 NEXT_STATE= SET_M2_AC_ADDR; 444 end

181 445

446 SET_M2_AC_ADDR: 447 begin 448 NEXT_STATE= SET_D_AC3; 449 end

450

451 SET_D_AC3: 452 begin 453 NEXT_STATE= SET_D_AC4; 454 end

455

456 SET_D_AC4: 457 begin 458 NEXT_STATE= SET_M2_AC; 459 end

460

461 SET_M2_AC: 462 begin 463 NEXT_STATE=SET_WN_CORR; 464 end

465

466 SET_WN_CORR: 467 begin 468 NEXT_STATE=ADD_RN; 469 end

470

471 ADD_RN: 472 begin 473 NEXT_STATE=SET_RN; 474 end

475

476 SET_RN: 477 begin 478 NEXT_STATE= INCR_AC1; 479 end

480

481 INCR_AC1: 482 begin 483 NEXT_STATE= CHECK_AC1; 484 end

485

486 INCR_AC: 487 begin 488 NEXT_STATE=CHECK_AC; 489 end

182 490

491 SET_LEVINSON: 492 begin 493 NEXT_STATE=RUN_LEVINSON; 494 end

495

496 RUN_LEVINSON: 497 begin 498 if(doneld) 499 begin 500 NEXT_STATE=GET_LEVINSON; 501 end 502 else 503 begin 504 NEXT_STATE=RUN_LEVINSON; 505 end 506 end

507

508 GET_LEVINSON: 509 begin 510 NEXT_STATE=INIT_READ_LPC; 511 end

512

513 INIT_READ_LPC: 514 begin 515 NEXT_STATE=CHECK_LPC; 516 end

517

518 CHECK_LPC: 519 begin 520 if(lp <= 10’d10) 521 begin 522 NEXT_STATE=READ_LPC_ADDR; 523 end 524 else 525 begin 526 NEXT_STATE=INIT_LOOP; 527 end 528 end

529

530 READ_LPC_ADDR: 531 begin 532 NEXT_STATE= SET_D_LPC1;

533

534 end

183 535

536 SET_D_LPC1: 537 begin 538 NEXT_STATE= SET_D_LPC2; 539 end

540

541 SET_D_LPC2: 542 begin 543 NEXT_STATE=GET_LPC_TO_AK; 544 end

545

546 GET_LPC_TO_AK: 547 begin 548 NEXT_STATE=INCR_LPC; 549 end

550

551 INCR_LPC: 552 begin 553 NEXT_STATE=CHECK_LPC; 554 end

555

556 INIT_LOOP: 557 begin 558 NEXT_STATE=PRE_CALC_E; 559 end

560

561 PRE_CALC_E: 562 begin 563 NEXT_STATE=CALC_E; 564 end

565

566 CALC_E: 567 begin 568 NEXT_STATE=INCR_I; 569 end

570

571 INCR_I: 572 begin 573 NEXT_STATE=CHECK_I; 574 end

575

576 CHECK_I: 577 begin 578 if(i <= 4’d10) 579 begin

184 580 NEXT_STATE=PRE_CALC_E; 581 end 582 else 583 begin 584 NEXT_STATE=INIT_AK_UPDATE; 585 end 586 end

587

588 INIT_AK_UPDATE: 589 begin 590 NEXT_STATE=CHECK_AK; 591 end

592

593 CHECK_AK: 594 begin 595 if(ak <= 10’d10) 596 begin 597 NEXT_STATE=UPDATE_AK; 598 end 599 else 600 begin 601 NEXT_STATE=SET_LPC_TO_LSP; 602 end 603 end

604

605 UPDATE_AK: 606 begin 607 NEXT_STATE=SET_AK; 608 end

609

610 SET_AK: 611 begin 612 NEXT_STATE=INCR_AK; 613 end

614

615 INCR_AK: 616 begin 617 NEXT_STATE=CHECK_AK; 618 end

619

620

621 SET_LPC_TO_LSP: 622 begin 623 NEXT_STATE=RUN_LTL; 624 end

185 625

626 RUN_LTL: 627 begin 628 if(doneltl) 629 begin 630 NEXT_STATE=GET_LTL; 631 end 632 else 633 begin 634 NEXT_STATE=RUN_LTL; 635 end 636 end

637

638 GET_LTL: 639 begin 640 NEXT_STATE=DONE; 641 end

642

643 DONE: 644 begin 645 NEXT_STATE=START; 646 end

647

648 default: 649 begin 650 NEXT_STATE=DONE; 651 end

652

653 endcase 654 end

655

656

657 always@(posedge clk or negedge rst)// Determine outputs 658 begin

659

660 if(rst == 1’b0) 661 begin

662

663 donespeech <= 1’b0;

664

665 end

666

667 else 668 begin 669 case(STATE)

186 670

671 START: 672 begin 673 donespeech <= 1’b0; 674 end

675

676 INIT: 677 begin 678 check_corr <= 32’b0; 679 end

680

681 // first for loop- calc of’e’ 682 INIT_FOR_1: 683 begin 684 i1 <= 10’d0; 685 end

686

687 CHECK_I1: 688 begin

689

690 end

691

692 SET_ADDR_SN: 693 begin 694 addr_sn <= i1; 695 end

696

697 SET_DELAY1: 698 begin

699

700 end

701

702 SET_DELAY2: 703 begin 704 addr_speech_w <= i1; 705 end

706

707 MULT_SN_W: 708 begin 709 ms1_in1 <={out_sn,16’b0}; 710 ms1_in2 <= data_out_speech_w;

711

712 addr_wn <= i1; 713 we_wn <= 1’d1; 714 re_wn <= 1’d0;

187 715 end

716

717 SQUARE_WN: 718 begin 719 write_wn <= ms1_out; 720 end

721

722 SQUARE_WN_2: 723 begin 724 ms1_in1 <= ms1_out; 725 ms1_in2 <= ms1_out; 726 end

727

728

729 SUM_SMALL_E: 730 begin 731 as2_in1 <={ms1_out[N2-1],2’b0,ms1_out[N2-2:0]}; 732 as2_in2 <=e; 733 end

734

735 SET_SMALL_E: 736 begin 737 e <= as2_out; 738 //c_e <= Wn260; 739 end

740

741 INCR_I1: 742 begin 743 i1 <= i1 + 10’d1; 744 end

745

746 INIT_FOR_AC: 747 begin 748 ac <= 10’d0; 749 end

750

751 CHECK_AC: 752 begin

753

754 end

755

756 INIT_R: 757 begin 758 case(ac) 759 4’d0: R0 <= 32’d0;

188 760 4’d1: R1 <= 32’d0; 761 4’d2: R2 <= 32’d0; 762 4’d3: R3 <= 32’d0; 763 4’d4: R4 <= 32’d0; 764 4’d5: R5 <= 32’d0; 765 4’d6: R6 <= 32’d0; 766 4’d7: R7 <= 32’d0; 767 4’d8: R8 <= 32’d0; 768 4’d9: R9 <= 32’d0; 769 4’d10: R10 <= 32’d0;

770

771 endcase 772 end

773

774 INIT_FOR_AC1: 775 begin 776 ac1 <= 10’d0; 777 end

778

779 CHECK_AC1: 780 begin

781

782 end

783

784 AUTO_CORR_WN: 785 begin 786 addr_wn <= ac1; 787 re_wn <= 1’b1; 788 we_wn <= 1’b0; 789 end

790

791 SET_D_AC1: 792 begin

793

794 end

795

796 SET_D_AC2: 797 begin

798

799 end

800

801 SET_M1_AC: 802 begin 803 ms1_in1 <= read_wn_out; 804 end

189 805

806 SET_M2_AC_ADDR: 807 begin 808 addr_wn <= ac+ ac1; 809 end

810

811 SET_D_AC3: 812 begin

813

814 end

815

816 SET_D_AC4: 817 begin

818

819 end

820

821 SET_M2_AC: 822 begin 823 ms1_in2 <= read_wn_out; 824 end

825

826 SET_WN_CORR: 827 begin 828 wn_corr <= ms1_out; 829 end

830

831 ADD_RN: 832 begin 833 as2_in1 <={wn_corr[N2-1],2’b0,wn_corr[N2-2:0]}; 834 case(ac) 835 10’d0: as2_in2 <= R0; 836 10’d1: as2_in2 <= R1; 837 10’d2: as2_in2 <= R2; 838 10’d3: as2_in2 <= R3; 839 10’d4: as2_in2 <= R4; 840 10’d5: as2_in2 <= R5; 841 10’d6: as2_in2 <= R6; 842 10’d7: as2_in2 <= R7; 843 10’d8: as2_in2 <= R8; 844 10’d9: as2_in2 <= R9; 845 10’d10: as2_in2 <= R10;

846

847 endcase 848 end

849

190 850 SET_RN: 851 begin 852 case(ac) 853 10’d0: R0 <= as2_out; 854 10’d1: R1 <= as2_out; 855 10’d2: R2 <= as2_out; 856 10’d3: R3 <= as2_out; 857 10’d4: R4 <= as2_out; 858 10’d5: R5 <= as2_out; 859 10’d6: R6 <= as2_out; 860 10’d7: R7 <= as2_out; 861 10’d8: R8 <= as2_out; 862 10’d9: R9 <= as2_out; 863 10’d10: R10 <= as2_out; 864 endcase 865 end

866

867 INCR_AC1: 868 begin 869 ac1 <= ac1 + 10’d1; 870 end

871

872 INCR_AC: 873 begin 874 ac <= ac + 10’d1; 875 end

876

877

878 SET_LEVINSON: 879 begin 880 startld <= 1’b1; 881 re_ld <= 1’b0; 882 we_ld <= 1’b1; 883 Rn0 <= R0[N3-1:16]; 884 Rn1 <= R1[N3-1:16]; 885 Rn2 <= R2[N3-1:16]; 886 Rn3 <= R3[N3-1:16]; 887 Rn4 <= R4[N3-1:16]; 888 Rn5 <= R5[N3-1:16]; 889 Rn6 <= R6[N3-1:16]; 890 Rn7 <= R7[N3-1:16]; 891 Rn8 <= R8[N3-1:16]; 892 Rn9 <= R9[N3-1:16]; 893 Rn10 <= R10[N3-1:16];

894

191 895

896

897 ld_R0 <= R0[N3-1:16]; 898 ld_R1 <= R1[N3-1:16]; 899 ld_R2 <= R2[N3-1:16]; 900 ld_R3 <= R3[N3-1:16]; 901 ld_R4 <= R4[N3-1:16]; 902 ld_R5 <= R5[N3-1:16]; 903 ld_R6 <= R6[N3-1:16]; 904 ld_R7 <= R7[N3-1:16]; 905 ld_R8 <= R8[N3-1:16]; 906 ld_R9 <= R9[N3-1:16]; 907 ld_R10 <= R10[N3-1:16];

908

909 end

910

911 RUN_LEVINSON: 912 begin 913 addr_ld <= ld_addr_ld; 914 startld <= 1’b0; 915 end

916

917 GET_LEVINSON: 918 begin

919

920 end

921

922 INIT_READ_LPC: 923 begin 924 lp <= 10’d0; 925 end

926

927 CHECK_LPC: 928 begin

929

930 end

931

932 READ_LPC_ADDR: 933 begin 934 addr_ld <= lp; 935 we_ld <= 1’b0; 936 re_ld <= 1’b1; 937 end

938

939 SET_D_LPC1:

192 940 begin

941

942 end

943

944 SET_D_LPC2: 945 begin

946

947 end

948

949 GET_LPC_TO_AK: 950 begin 951 case(lp) 952 10’d0: 953 begin 954 ak0 <= out_lpc; 955 //c_ak0 <= out_lpc;// from levinson 956 end 957 10’d1: 958 begin 959 ak1 <= out_lpc; 960 //c_ak1 <= out_lpc; 961 end 962 10’d2: 963 begin 964 ak2 <= out_lpc; 965 //c_ak2 <= out_lpc; 966 end 967 10’d3: 968 begin 969 ak3 <= out_lpc; 970 //c_ak3 <= out_lpc; 971 end 972 10’d4: 973 begin 974 ak4 <= out_lpc; 975 //c_ak4 <= out_lpc; 976 end 977 10’d5: 978 begin 979 ak5 <= out_lpc; 980 //c_ak5 <= out_lpc; 981 end 982 10’d6: 983 begin 984 ak6 <= out_lpc;

193 985 //c_ak6 <= out_lpc; 986 end 987 10’d7: 988 begin 989 ak7 <= out_lpc; 990 //c_ak7 <= out_lpc; 991 end 992 10’d8: 993 begin 994 ak8 <= out_lpc; 995 //c_ak8 <= out_lpc; 996 end 997 10’d9: 998 begin 999 ak9 <= out_lpc; 1000 //c_ak9 <= out_lpc; 1001 end 1002 10’d10: 1003 begin 1004 ak10 <= out_lpc; 1005 //c_ak10 <= out_lpc; 1006 end

1007

1008 endcase

1009

1010

1011 end

1012

1013 INCR_LPC: 1014 begin 1015 lp <= lp + 10’d1; 1016 end

1017

1018 INIT_LOOP: 1019 begin 1020 E <= 32’b0; 1021 i <= 4’d0; 1022 end

1023

1024 PRE_CALC_E: 1025 begin 1026 case(i) 1027 4’d0: 1028 begin 1029 m2_in1 <={ak0[N-1],2’b0,ak0[N-2:0]};

194 1030 m2_in2 <= Rn0; 1031 end 1032 4’d1: 1033 begin 1034 m2_in1<= {ak1[N-1],2’b0,ak1[N-2:0]}; 1035 m2_in2 <= Rn1; 1036 end 1037 4’d2: 1038 begin 1039 m2_in1<= {ak2[N-1],2’b0,ak2[N-2:0]}; 1040 m2_in2 <= Rn2; 1041 end 1042 4’d3: 1043 begin 1044 m2_in1<= {ak3[N-1],2’b0,ak3[N-2:0]}; 1045 m2_in2 <= Rn3; 1046 end 1047 4’d4: 1048 begin 1049 m2_in1<= {ak4[N-1],2’b0,ak4[N-2:0]}; 1050 m2_in2 <= Rn4; 1051 end 1052 4’d5: 1053 begin 1054 m2_in1<= {ak5[N-1],2’b0,ak5[N-2:0]}; 1055 m2_in2 <= Rn5; 1056 end 1057 4’d6: 1058 begin 1059 m2_in1<= {ak6[N-1],2’b0,ak6[N-2:0]}; 1060 m2_in2 <= Rn6; 1061 end 1062 4’d7: 1063 begin 1064 m2_in1<= {ak7[N-1],2’b0,ak7[N-2:0]}; 1065 m2_in2 <= Rn7; 1066 end 1067 4’d8: 1068 begin 1069 m2_in1<= {ak8[N-1],2’b0,ak8[N-2:0]}; 1070 m2_in2 <= Rn8; 1071 end 1072 4’d9: 1073 begin 1074 m2_in1<= {ak9[N-1],2’b0,ak9[N-2:0]};

195 1075 m2_in2 <= Rn9; 1076 end 1077 4’d10: 1078 begin 1079 m2_in1<= {ak10[N-1],2’b0,ak10[N-2:0]}; 1080 m2_in2 <= Rn10; 1081 end

1082

1083 endcase 1084 end

1085

1086 CALC_E: 1087 begin 1088 a1_in1 <=E; 1089 a1_in2 <={m2_out[N4-1],m2_out[30:0]}; 1090 end

1091

1092 INCR_I: 1093 begin 1094 i <=i + 4’d1; 1095 E <= a1_out; 1096 end

1097

1098 CHECK_I: 1099 begin

1100

1101 end

1102

1103 INIT_AK_UPDATE: 1104 begin 1105 ak <= 10’d0; 1106 end

1107

1108 CHECK_AK: 1109 begin

1110

1111 end

1112

1113 UPDATE_AK: 1114 begin 1115 // ak_addr <= ak; 1116 // we_ak <= 1’b1; 1117 // re_ak <= 1’b0; 1118 case(ak) 1119 10’d0:

196 1120 begin 1121 m1_in1 <= ak0; 1122 m1_in2 <= powf0; 1123 end 1124 10’d1: 1125 begin 1126 m1_in1 <= ak1; 1127 m1_in2 <= powf1; 1128 end 1129 10’d2: 1130 begin 1131 m1_in1 <= ak2; 1132 m1_in2 <= powf2; 1133 end 1134 10’d3: 1135 begin 1136 m1_in1 <= ak3; 1137 m1_in2 <= powf3; 1138 end 1139 10’d4: 1140 begin 1141 m1_in1 <= ak4; 1142 m1_in2 <= powf4; 1143 end 1144 10’d5: 1145 begin 1146 m1_in1 <= ak5; 1147 m1_in2 <= powf5; 1148 end 1149 10’d6: 1150 begin 1151 m1_in1 <= ak6; 1152 m1_in2 <= powf6; 1153 end 1154 10’d7: 1155 begin 1156 m1_in1 <= ak7; 1157 m1_in2 <= powf7; 1158 end 1159 10’d8: 1160 begin 1161 m1_in1 <= ak8; 1162 m1_in2 <= powf8; 1163 end 1164 10’d9:

197 1165 begin 1166 m1_in1 <= ak9; 1167 m1_in2 <= powf9; 1168 end 1169 10’d10: 1170 begin 1171 m1_in1 <= ak10; 1172 m1_in2 <= powf10; 1173 end

1174

1175 endcase 1176 end

1177

1178

1179 SET_AK: 1180 begin 1181 case(ak) 1182 10’d0: 1183 begin 1184 ak0 <= m1_out; 1185 check_ak0_lev <= m1_out; 1186 end 1187 10’d1: ak1 <= m1_out; 1188 10’d2: ak2 <= m1_out; 1189 10’d3: ak3 <= m1_out; 1190 10’d4: ak4 <= m1_out; 1191 10’d5: ak5 <= m1_out; 1192 10’d6: ak6 <= m1_out; 1193 10’d7: ak7 <= m1_out; 1194 10’d8: ak8 <= m1_out; 1195 10’d9: ak9 <= m1_out; 1196 10’d10: ak10 <= m1_out;

1197

1198 endcase

1199

1200

1201 end

1202

1203 INCR_AK: 1204 begin 1205 ak <= ak + 10’d1; 1206 //write_ak <= m1_out; 1207 end

1208

1209 SET_LPC_TO_LSP:

198 1210 begin 1211 startltl <= 1’b1; 1212 //we_ak <= 1’b0; 1213 //re_ak <= 1’b1;

1214

1215 ll_ak0 <= ak0; 1216 ll_ak1 <= ak1; 1217 ll_ak2 <= ak2; 1218 ll_ak3 <= ak3; 1219 ll_ak4 <= ak4; 1220 ll_ak5 <= ak5; 1221 ll_ak6 <= ak6; 1222 ll_ak7 <= ak7; 1223 ll_ak8 <= ak8; 1224 ll_ak9 <= ak9; 1225 ll_ak10 <= ak10;

1226

1227 end

1228

1229 RUN_LTL: 1230 begin 1231 //ak_addr <= ltl_ak_addr; 1232 //ltl_ak_out <= read_ak_out; 1233 startltl <= 1’b0; 1234 end

1235

1236 GET_LTL: 1237 begin 1238 lsp0 <= freq0; 1239 lsp1 <= freq1; 1240 lsp2 <= freq2; 1241 lsp3 <= freq3; 1242 lsp4 <= freq4; 1243 lsp5 <= freq5; 1244 lsp6 <= freq6; 1245 lsp7 <= freq7; 1246 lsp8 <= freq8; 1247 lsp9 <= freq9; 1248 end

1249

1250

1251 DONE: 1252 begin 1253 donespeech <= 1’b1; 1254 end

199 1255

1256 endcase 1257 end

1258

1259 end

1260

1261

1262 endmodule

B.5 encode lsp scalar.v

1 /* 2 * Module- encode_lsps_scalar 3 * Top module- codec2_encode_2400 4 * Project- CODEC2_ENCODE_2400 5 * Developer- SanthiyaS 6 * Date- Wed Feb 06 16:25:02 2019 7 * 8 * Description- 9 * Input(s)- lsp[10](from RAM_lsp) 10 * Output(s)- indexes 11 * Simulation- Waveform18.vwf 12 * 32 bits fixed point representation 13 S-E-M 14 1- 15- 16 15 */

17 module encode_lsp_scalar(start_elsp,clk,rst,index, 18 in_lsp0,in_lsp1,in_lsp2,in_lsp3,in_lsp4,in_lsp5,in_lsp6,in_lsp7,in_lsp8,in_lsp9, 19 out_index, 20 done_elsp

22 ); 23 //in_lsp_hz_check0,besti_check0);

27 //------28 //-- Input/Output Declarations-- 29 //------30 parameterN = 32; 31 parameterQ = 16; 32 parameter[N-1:0]RADTOHZ = 32’b00000100111110010011110101010010;

200 34 input clk,rst; 35 input start_elsp; 36 //input[N-1:0] lsp_out; 37 input [3:0] index; 38 output reg done_elsp; 39 output reg [3:0] out_index; 40 //addr_lsp;//,besti_check0;

42 //output reg[N-1:0] c_lsp;

44 input[N-1:0] in_lsp0,in_lsp1,in_lsp2,in_lsp3,in_lsp4, 45 in_lsp5,in_lsp6,in_lsp7,in_lsp8,in_lsp9; 46 // reg [3:0] addr_lsp; 47 // 48 // wire[N-1:0] lsp_out; 49 // 50 //RAM_encode_lsp ram_lsps0(addr_lsp,clk,,1,0,lsp_out);

52 //------53 //-- Reg Declarations-- 54 //------55 wire[N-1:0] lsp_hz0,lsp_hz1,lsp_hz2,lsp_hz3,lsp_hz4, 56 lsp_hz5,lsp_hz6,lsp_hz7,lsp_hz8,lsp_hz9; 57 wire[N-1:0] lsp0,lsp1,lsp2,lsp3,lsp4, 58 lsp5,lsp6,lsp7,lsp8,lsp9; 59 wire [3:0] besti; 60 reg [3:0] besti0,besti1,besti2,besti3,besti4, 61 besti5,besti6,besti7,besti8,besti9;

63 reg[N-1:0] in_lsp_hz,in_lsp_hz0,in_lsp_hz1,in_lsp_hz2,in_lsp_hz3, 64 in_lsp_hz4,in_lsp_hz5,in_lsp_hz6,in_lsp_hz7,in_lsp_hz8,in_lsp_hz9;

69 reg startq; 70 reg [4:0]m,quanti; 71 reg [3:0] orderi;

73 parameter [4:0] m0 =5’d16, 74 m1 =5’d16, 75 m2 =5’d16, 76 m3 =5’d16, 77 m4 =5’d16, 78 m5 =5’d16,

201 79 m6 =5’d16, 80 m7 =5’d8, 81 m8 =5’d8, 82 m9 =5’d4;

84 parameter [3:0] orderi0 =4’d0, 85 orderi1 =4’d1, 86 orderi2 =4’d2, 87 orderi3 =4’d3, 88 orderi4 =4’d4, 89 orderi5 =4’d5, 90 orderi6 =4’d6, 91 orderi7 =4’d7, 92 orderi8 =4’d8, 93 orderi9 =4’d9;

95 wire doneq,doneq0,doneq1,doneq2,doneq3,doneq4,doneq5, 96 doneq6,doneq7,doneq8,doneq9;

98 //------99 //-- State Declarations-- 100 //------

101

102 parameterSTART =6’d0, 103 INITVALUES =6’d1, 104 CALC_LSPHZ =6’d2, 105 INIT_QUANTISE =6’d3, 106 START_QUANTISE =6’d4, 107 CALC_INDEX =6’d5, 108 RECORD_INDEX =6’d6, 109 DONE =6’d7, 110 INCR_FOR_I =6’d8, 111 INIT_FOR =6’d9, 112 CHECK_FOR_I =6’d10, 113 SET_ADDR =6’d11, 114 SET_DELAY1 =6’d12, 115 SET_DELAY2 =6’d13, 116 INIT_QUANT_FOR =6’d14, 117 CHECK_QUANT_I =6’d15, 118 INCR_QUANT_I =6’d16, 119 RECORD_BEST_I =6’d17;

120

121

122 reg [5:0]STATE,NEXT_STATE;

123

202 124

125

126 //------127 //-- Module Instantiations-- 128 //------

129

130 quantise quantise0(clk,1,startq,m,orderi,in_lsp_hz,besti,doneq);

131

132

133

134 qmult#(Q,N) mult0(RADTOHZ, in_lsp0, lsp_hz0); 135 qmult#(Q,N) mult1(RADTOHZ, in_lsp1, lsp_hz1); 136 qmult#(Q,N) mult2(RADTOHZ, in_lsp2, lsp_hz2); 137 qmult#(Q,N) mult3(RADTOHZ, in_lsp3, lsp_hz3); 138 qmult#(Q,N) mult4(RADTOHZ, in_lsp4, lsp_hz4); 139 qmult#(Q,N) mult5(RADTOHZ, in_lsp5, lsp_hz5); 140 qmult#(Q,N) mult6(RADTOHZ, in_lsp6, lsp_hz6); 141 qmult#(Q,N) mult7(RADTOHZ, in_lsp7, lsp_hz7); 142 qmult#(Q,N) mult8(RADTOHZ, in_lsp8, lsp_hz8); 143 qmult#(Q,N) mult9(RADTOHZ, in_lsp9, lsp_hz9);

144

145

146 reg [3:0]i;

147

148

149

150

151 //------152 //-- Begin Declarations& Coding-- 153 //------

154

155 always@(posedge clk or negedge rst)// DetermineSTATE 156 begin

157

158 if(rst == 1’b0) 159 STATE <=START; 160 else 161 STATE <=NEXT_STATE;

162

163 end

164

165

166 always@(*)// DetermineNEXT_STATE 167 begin 168 case(STATE)

203 169

170 START: 171 begin 172 if(start_elsp == 1’b1) 173 begin 174 NEXT_STATE=INITVALUES; 175 end 176 else 177 begin 178 NEXT_STATE=START; 179 end 180 end

181

182 INITVALUES: 183 begin 184 NEXT_STATE=INIT_FOR; 185 end

186

187 INIT_FOR: 188 begin 189 NEXT_STATE=CHECK_FOR_I; 190 end

191

192 CHECK_FOR_I: 193 begin 194 if(i <4’d10) 195 begin 196 NEXT_STATE=SET_ADDR; 197 end 198 else 199 begin 200 NEXT_STATE=INIT_QUANT_FOR;//INIT_QUANTISE; 201 end 202 end

203

204 SET_ADDR: 205 begin 206 NEXT_STATE= SET_DELAY1; 207 end

208

209 SET_DELAY1: 210 begin 211 NEXT_STATE= SET_DELAY2; 212 end

213

204 214 SET_DELAY2: 215 begin 216 NEXT_STATE=CALC_LSPHZ; 217 end

218

219 CALC_LSPHZ: 220 begin 221 NEXT_STATE=INCR_FOR_I; 222 end

223

224 INCR_FOR_I: 225 begin 226 NEXT_STATE=CHECK_FOR_I; 227 end

228

229 INIT_QUANT_FOR: 230 begin 231 NEXT_STATE=CHECK_QUANT_I; 232 end

233

234 CHECK_QUANT_I: 235 begin 236 if(quanti >= 4’d10) 237 begin 238 NEXT_STATE=RECORD_INDEX; 239 end 240 else 241 begin 242 NEXT_STATE=INIT_QUANTISE; 243 end 244 end

245

246 INIT_QUANTISE: 247 begin 248 NEXT_STATE=START_QUANTISE; 249 end

250

251 START_QUANTISE: 252 begin 253 NEXT_STATE=CALC_INDEX; 254 end

255

256 CALC_INDEX: 257 begin 258 if(doneq)

205 259 begin 260 NEXT_STATE=RECORD_BEST_I; 261 end 262 else 263 begin 264 NEXT_STATE=CALC_INDEX; 265 end 266 end

267

268 RECORD_BEST_I: 269 begin 270 NEXT_STATE=INCR_QUANT_I; 271 end

272

273 RECORD_INDEX: 274 begin 275 NEXT_STATE=DONE; 276 end

277

278

279 INCR_QUANT_I: 280 begin 281 NEXT_STATE=CHECK_QUANT_I; 282 end

283

284 DONE: 285 begin 286 NEXT_STATE=START; 287 end

288

289 default: 290 begin 291 NEXT_STATE=DONE; 292 end

293

294 endcase 295 end

296

297

298 always@(posedge clk or negedge rst)// Determine outputs 299 begin

300

301 if(rst == 1’b0) 302 begin 303 done_elsp <= 1’b0;

206 304 end

305

306 else 307 begin 308 case(STATE) 309 START: 310 begin 311 done_elsp <= 1’b0;

312

313

314 /* in_lsp0 <= 16’h11E6; 315 in_lsp1 <= 16’h5C1E; 316 in_lsp2 <= 16’hBC5E; 317 in_lsp3 <= 16’hF156; 318 in_lsp4 <= 32’h13E6A; 319 in_lsp5 <= 32’h1894E; 320 in_lsp6 <= 32’h1DE4A; 321 in_lsp7 <= 32’h2309A; 322 in_lsp8 <= 32’h281EE; 323 in_lsp9 <= 32’h2DB06;// Actual 324 */

325

326 /* in_lsp0 <= 16’h12A9; 327 in_lsp1 <= 16’h5779; 328 in_lsp2 <= 16’hB990; 329 in_lsp3 <= 16’hEEE2; 330 in_lsp4 <= 32’h13D57; 331 in_lsp5 <= 32’h186D6; 332 in_lsp6 <= 32’h1DD7C; 333 in_lsp7 <= 32’h22E76; 334 in_lsp8 <= 32’h2810C; 335 in_lsp9 <= 32’h2D02D;*/// Expectedc code base

336

337

338 /* in_lsp0 <= 16’h12E2; 339 in_lsp1 <= 16’h577E; 340 in_lsp2 <= 16’hB996; 341 in_lsp3 <= 16’hEEDE; 342 in_lsp4 <= 32’h13D82; 343 in_lsp5 <= 32’h186F2; 344 in_lsp6 <= 32’h1DD76; 345 in_lsp7 <= 32’h22E72; 346 in_lsp8 <= 32’h28126; 347 in_lsp9 <= 32’h2CFE2;// Actual Dec2

348

207 349

350 index <= 4’d9;*/ 351 end

352

353 INITVALUES: 354 begin 355 startq <= 1’b0; 356 end

357

358 INIT_FOR: 359 begin 360 i <= 4’d0; 361 end

362

363 CHECK_FOR_I: 364 begin

365

366 end

367

368 SET_ADDR: 369 begin 370 //addr_lsp <=i; 371 end

372

373 SET_DELAY1: 374 begin

375

376 end

377

378 SET_DELAY2: 379 begin

380

381 end

382

383 CALC_LSPHZ: 384 begin 385 /* case(i)

386

387 4’d0: in_lsp0 <= lsp_out; 388 4’d1: in_lsp1 <= lsp_out; 389 4’d2: in_lsp2 <= lsp_out; 390 4’d3: in_lsp3 <= lsp_out; 391 4’d4: in_lsp4 <= lsp_out; 392 4’d5: in_lsp5 <= lsp_out; 393 4’d6: in_lsp6 <= lsp_out;

208 394 4’d7: in_lsp7 <= lsp_out; 395 4’d8: in_lsp8 <= lsp_out; 396 4’d9: in_lsp9 <= lsp_out;

397

398 endcase

399

400 c_lsp <= lsp_out;*/ 401 end

402

403 INCR_FOR_I: 404 begin 405 i <=i + 4’d1; 406 end

407

408 INIT_QUANT_FOR: 409 begin 410 quanti <= 4’d0; 411 end

412

413 CHECK_QUANT_I: 414 begin

415

416 end

417

418 INIT_QUANTISE: 419 begin

420

421 case(quanti) 422 4’d0: 423 begin 424 in_lsp_hz <= lsp_hz0; 425 m <= m0; 426 orderi <= orderi0; 427 end 428 4’d1: 429 begin 430 in_lsp_hz <= lsp_hz1; 431 m <= m1; 432 orderi <= orderi1; 433 end 434 4’d2: 435 begin 436 in_lsp_hz <= lsp_hz2; 437 m <= m2; 438 orderi <= orderi2;

209 439 end 440 4’d3: 441 begin 442 in_lsp_hz <= lsp_hz3; 443 m <= m3; 444 orderi <= orderi3; 445 end 446 4’d4: 447 begin 448 in_lsp_hz <= lsp_hz4; 449 m <= m4; 450 orderi <= orderi4; 451 end 452 4’d5: 453 begin 454 in_lsp_hz <= lsp_hz5; 455 m <= m5; 456 orderi <= orderi5; 457 end 458 4’d6: 459 begin 460 in_lsp_hz <= lsp_hz6; 461 m <= m6; 462 orderi <= orderi6; 463 end 464 4’d7: 465 begin 466 in_lsp_hz <= lsp_hz7; 467 m <= m7; 468 orderi <= orderi7; 469 end 470 4’d8: 471 begin 472 in_lsp_hz <= lsp_hz8; 473 m <= m8; 474 orderi <= orderi8; 475 end 476 4’d9: 477 begin 478 in_lsp_hz <= lsp_hz9; 479 m <= m9; 480 orderi <= orderi9; 481 end

482

483 endcase

210 484

485 end

486

487 START_QUANTISE: 488 begin 489 startq <= 1’b1; 490 end

491

492 CALC_INDEX: 493 begin 494 //startq <= 1’b0; 495 end

496

497 RECORD_BEST_I: 498 begin 499 case(quanti)

500

501 4’d0: besti0 <= besti; 502 4’d1: besti1 <= besti; 503 4’d2: besti2 <= besti; 504 4’d3: besti3 <= besti; 505 4’d4: besti4 <= besti; 506 4’d5: besti5 <= besti; 507 4’d6: besti6 <= besti; 508 4’d7: besti7 <= besti; 509 4’d8: besti8 <= besti; 510 4’d9: besti9 <= besti;

511

512 endcase 513 end

514

515 RECORD_INDEX: 516 begin

517

518 /* indexes0 <= besti0; 519 indexes1 <= besti1; 520 indexes2 <= besti2; 521 indexes3 <= besti3; 522 indexes4 <= besti4; 523 indexes5 <= besti5; 524 indexes6 <= besti6; 525 indexes7 <= besti7; 526 indexes8 <= besti8; 527 indexes9 <= besti9; 528 //besti_check0 <= besti0;

211 529 //in_lsp_hz_check0 <= lsp_hz0;*/

530

531

532 case(index)

533

534 4’d0: out_index <= besti0; 535 4’d1: out_index <= besti1; 536 4’d2: out_index <= besti2; 537 4’d3: out_index <= besti3; 538 4’d4: out_index <= besti4; 539 4’d5: out_index <= besti5; 540 4’d6: out_index <= besti6; 541 4’d7: out_index <= besti7; 542 4’d8: out_index <= besti8; 543 4’d9: out_index <= besti9;

544

545 endcase 546 end

547

548 INCR_QUANT_I: 549 begin 550 quanti <= quanti +1’b1; 551 end

552

553 DONE: 554 begin 555 done_elsp <= 1’b1; 556 end

557

558 endcase 559 end

560

561 end

562

563

564

565

566 endmodule

B.6 encode WoE.v

1 /* 2 * Module- encode_WoE 3 * Top module- codec2_encode

212 4 * Project- CODEC2_ENCODE_2400 5 * Developer- SanthiyaS 6 * Date- Wed Feb 20 13:16:46 2019 7 * 8 * Description- 9 * Inputs- 10 * Simulation- Waveform36.vwf 11 *32 bits fixed point representation 12 S-E-M 13 1- 15- 16 14 */

17 module encode_WoE(startewoe,clk,rst,model_wo,in_e,xq0,xq1, 18 out_xq0,out_xq1,out_n1,doneewoe);

21 //------22 //-- Input/Output Declarations-- 23 //------

25 parameterN = 32; 26 parameterQ = 16;

28 input startewoe, clk, rst; 29 input[N-1:0] model_wo, in_e,xq0,xq1; 30 output reg[N-1:0] out_n1,out_xq0,out_xq1; 31 output reg doneewoe;

35 //------36 //-- State& Reg Declarations-- 37 //------

39 parameterSTART =5’d0, 40 CHECK_E =5’d1, 41 SET_E =5’d2, 42 PRECALC1_X0 =5’d3, 43 PRECALC2_X0 =5’d4, 44 PRE_CALC3_X0 =5’d5, 45 CALC_X0 =5’d6, 46 PRECALC_X1 =5’d7, 47 CALC_X1 =5’d8, 48 SET_CW =5’d9,

213 49 CALC_CW =5’d10, 50 PRECALC1_ERR =5’d11, 51 PRECALC2_ERR =5’d12, 52 CALC_ERR =5’d13, 53 SET_FNW =5’d14, 54 CALC_FNW =5’d15, 55 DONE =5’d16, 56 SET_XQ0 =5’d17, 57 XQ0_ADD =5’d18, 58 XQ0_MULT =5’d19;

61 reg [4:0]STATE,NEXT_STATE;

63 parameter[N-1:0] cb0 = 32’b00000000000000101011010111000010, 64 cb1 = 32’b00000000000011000000010010110101, 65 cb2 = 32’b00000000000000000000101111110111, 66 cb3 = 32’b10000000000000101011110100100010, 67 cb4 = 32’b00000000000000000001111011111001, 68 cb5 = 32’b00000000000010000110001110010010, 69 cb6 = 32’b10000000000000011001010010001101, 70 cb7 = 32’b10000000000000001110010001101110, 71 cb8 = 32’b00000000000000010011000101101101, 72 cb9 = 32’b10000000000000011110101001100101, 73 cb10 = 32’b00000000000000000010111111100101, 74 cb11 = 32’b10000000000000110100011011011011, 75 cb12 = 32’b00000000000000000101010100001110, 76 cb13 = 32’b10000000000001111010101000011111, 77 cb14 = 32’b10000000000000010111101010111100, 78 cb15 = 32’b00000000000111110011111100000000, 79 cb16 = 32’b00000000000000011000011100010001, 80 cb17 = 32’b00000000000110111011010110100001, 81 cb18 = 32’b10000000000000001000011000111101, 82 cb19 = 32’b00000000000001010100000000000111, 83 cb20 = 32’b00000000000000001000110110100111, 84 cb21 = 32’b00000000000001110111000001010101, 85 cb22 = 32’b10000000000000001101011111101100, 86 cb23 = 32’b10000000000000011111001111110111, 87 cb24 = 32’b00000000000000100100001110001110, 88 cb25 = 32’b00000000000010001001110000111011, 89 cb26 = 32’b00000000000000000010010010100101, 90 cb27 = 32’b00000000000000100101110110010000, 91 cb28 = 32’b00000000000000001001110111010011, 92 cb29 = 32’b00000000000000010100100011000101, 93 cb30 = 32’b10000000000000011011011000011001,

214 94 cb31 = 32’b00000000000101100001100011000001, 95 cb32 = 32’b00000000000000010000001000010100, 96 cb33 = 32’b00000000000100010110010110000001, 97 cb34 = 32’b10000000000000000001101101010001, 98 cb35 = 32’b00000000000000010110101100111101, 99 cb36 = 32’b10000000000000000010001011100001, 100 cb37 = 32’b00000000000011100100011000001010, 101 cb38 = 32’b10000000000000011011010110000110, 102 cb39 = 32’b10000000000101001000100000101010, 103 cb40 = 32’b00000000000000011010100001101010, 104 cb41 = 32’b10000000000000110110010000011101, 105 cb42 = 32’b00000000000000000010001101010111, 106 cb43 = 32’b10000000000001001111010100110101, 107 cb44 = 32’b00000000000000001000100101100111, 108 cb45 = 32’b10000000000000011111000110011001, 109 cb46 = 32’b00000000000000000011001001000001, 110 cb47 = 32’b00000000001001001101101000010110, 111 cb48 = 32’b00000000000000010100010111000001, 112 cb49 = 32’b00000000000101101000111001110110, 113 cb50 = 32’b10000000000000001010101110010011, 114 cb51 = 32’b10000000000000011110011111110010, 115 cb52 = 32’b00000000000000000110000111010000, 116 cb53 = 32’b00000000000001100110011010110000, 117 cb54 = 32’b10000000000000001100000111000100, 118 cb55 = 32’b10000000000001001110011010101001, 119 cb56 = 32’b00000000000000011101010001001101, 120 cb57 = 32’b00000000000001001001110100100001, 121 cb58 = 32’b00000000000000000101000110011100, 122 cb59 = 32’b00000000000000001011110010100000, 123 cb60 = 32’b00000000000000001001110011100001, 124 cb61 = 32’b10000000000000100001001100110110, 125 cb62 = 32’b10000000000000000110100011111111, 126 cb63 = 32’b00000000000110001100100101111111, 127 cb64 = 32’b00000000000000011100011010101001, 128 cb65 = 32’b00000000000011010011000011011110, 129 cb66 = 32’b00000000000000000001101101000000, 130 cb67 = 32’b10000000000000000001101010111111, 131 cb68 = 32’b00000000000000000011000100110100, 132 cb69 = 32’b00000000000010100010111100001101, 133 cb70 = 32’b10000000000000011101001100001101, 134 cb71 = 32’b10000000000001111011011100110100, 135 cb72 = 32’b00000000000000001110111001101100, 136 cb73 = 32’b00000000000001000101100100101101, 137 cb74 = 32’b00000000000000000100111100001110, 138 cb75 = 32’b10000000000001000001011000000100,

215 139 cb76 = 32’b00000000000000000110010110101011, 140 cb77 = 32’b10000000000010111100111100010100, 141 cb78 = 32’b10000000000000000000110001111000, 142 cb79 = 32’b00000000001010010011101000110000, 143 cb80 = 32’b00000000000000001110000010011001, 144 cb81 = 32’b00000000001000111101100110101101, 145 cb82 = 32’b10000000000000001100001010000001, 146 cb83 = 32’b00000000000000000111101000000100, 147 cb84 = 32’b00000000000000001111101010000101, 148 cb85 = 32’b00000000000001111010110010110111, 149 cb86 = 32’b10000000000000010011000111101111, 150 cb87 = 32’b00000000000000110000100111110000, 151 cb88 = 32’b00000000000000101010001111001111, 152 cb89 = 32’b10000000000000110110100100111011, 153 cb90 = 32’b00000000000000000011000011101101, 154 cb91 = 32’b00000000000000111001101001111111, 155 cb92 = 32’b00000000000000000110011100100110, 156 cb93 = 32’b00000000000000010001010110010100, 157 cb94 = 32’b10000000000000100010011011101010, 158 cb95 = 32’b00000000000100100001101110001011, 159 cb96 = 32’b00000000000000011000101111111011, 160 cb97 = 32’b00000000000010000101001010011101, 161 cb98 = 32’b10000000000000000010010010100001, 162 cb99 = 32’b10000000000001000001001101101111, 163 cb100 = 32’b10000000000000000010011001101111, 164 cb101 = 32’b00000000000001011101110111100010, 165 cb102 = 32’b10000000000000010110100010001111, 166 cb103 = 32’b10000000000000110100000000101101, 167 cb104 = 32’b00000000000000011001000011101111, 168 cb105 = 32’b10000000000010100110100111000111, 169 cb106 = 32’b00000000000000000010110110011100, 170 cb107 = 32’b10000000000010100011101000001001, 171 cb108 = 32’b00000000000000000101110010110110, 172 cb109 = 32’b10000000000000000000011101001111, 173 cb110 = 32’b10000000000000000001000111110011, 174 cb111 = 32’b00000000000110000110010000000100, 175 cb112 = 32’b00000000000000001001100001000001, 176 cb113 = 32’b00000000000100010111101110011000, 177 cb114 = 32’b10000000000000000100100101110111, 178 cb115 = 32’b10000000000001101110011101110001, 179 cb116 = 32’b00000000000000000111011011111110, 180 cb117 = 32’b00000000000010100011010010011011, 181 cb118 = 32’b10000000000000010000000111000000, 182 cb119 = 32’b10000000000011100101101101110001, 183 cb120 = 32’b00000000000000100101010001011110,

216 184 cb121 = 32’b10000000000000111011000100001101, 185 cb122 = 32’b00000000000000000101010111110011, 186 cb123 = 32’b00000000000000100110100000111010, 187 cb124 = 32’b00000000000000010000010100001000, 188 cb125 = 32’b10000000000000110010011111011000, 189 cb126 = 32’b10000000000000010100001001101011, 190 cb127 = 32’b00000000000001111111110111101101, 191 cb128 = 32’b00000000000000100110001000111001, 192 cb129 = 32’b00000000000100111010111000111011, 193 cb130 = 32’b10000000000000000001100001001110, 194 cb131 = 32’b10000000000000100110100111101010, 195 cb132 = 32’b00000000000000000011010110010110, 196 cb133 = 32’b00000000000001101010101000101110, 197 cb134 = 32’b10000000000000100011100010010101, 198 cb135 = 32’b00000000000000010110000100111110, 199 cb136 = 32’b00000000000000010100101011011010, 200 cb137 = 32’b00000000000000100000101111011100, 201 cb138 = 32’b00000000000000000011111001011110, 202 cb139 = 32’b10000000000000001110010000000111, 203 cb140 = 32’b00000000000000000110110111000100, 204 cb141 = 32’b10000000000001110011000110010011, 205 cb142 = 32’b10000000000000010001110100011110, 206 cb143 = 32’b00000000001010010101011101100101, 207 cb144 = 32’b00000000000000101001110000011011, 208 cb145 = 32’b00000000000111110010001111110111, 209 cb146 = 32’b10000000000000000111001001001011, 210 cb147 = 32’b00000000000000101000100011000000, 211 cb148 = 32’b00000000000000000111110101110111, 212 cb149 = 32’b00000000000001001010000010101000, 213 cb150 = 32’b10000000000000010001111000000010, 214 cb151 = 32’b10000000000000110011110111100010, 215 cb152 = 32’b00000000000000011100101010100011, 216 cb153 = 32’b00000000000010000110101000111000, 217 cb154 = 32’b00000000000000000010011111110000, 218 cb155 = 32’b00000000000000000010111011101111, 219 cb156 = 32’b00000000000000001000100001001110, 220 cb157 = 32’b00000000000000110010011110010000, 221 cb158 = 32’b10000000000000001100001110110101, 222 cb159 = 32’b00000000000100101000001110010101, 223 cb160 = 32’b00000000000000001111001111010000, 224 cb161 = 32’b00000000000010111100010101110011, 225 cb162 = 32’b10000000000000000101010100100011, 226 cb163 = 32’b00000000000000000101100011010100, 227 cb164 = 32’b00000000000000000011001111000001, 228 cb165 = 32’b00000000000011101011011110000000,

217 229 cb166 = 32’b10000000000000100010000100010101, 230 cb167 = 32’b10000000000011111000111100011010, 231 cb168 = 32’b00000000000000010101101010000100, 232 cb169 = 32’b10000000000000011110110101000010, 233 cb170 = 32’b10000000000000000000001011001110, 234 cb171 = 32’b10000000000100000101011000011110, 235 cb172 = 32’b00000000000000000110011000101000, 236 cb173 = 32’b10000000000000101100101001100010, 237 cb174 = 32’b00000000000000001100000000101011, 238 cb175 = 32’b00000000000111110010010111110110, 239 cb176 = 32’b00000000000000001010011111011110, 240 cb177 = 32’b00000000000110000111101101011101, 241 cb178 = 32’b10000000000000000111010000000101, 242 cb179 = 32’b10000000000000001011110001100010, 243 cb180 = 32’b00000000000000000100100101110010, 244 cb181 = 32’b00000000000001101000101111110100, 245 cb182 = 32’b10000000000000001011011100110110, 246 cb183 = 32’b10000000000011000101101110011000, 247 cb184 = 32’b00000000000000011000110001101001, 248 cb185 = 32’b00000000000000111101111101000110, 249 cb186 = 32’b00000000000000000100010110011001, 250 cb187 = 32’b00000000000000001100110101100110, 251 cb188 = 32’b00000000000000001000000010000111, 252 cb189 = 32’b10000000000001001101101011010111, 253 cb190 = 32’b10000000000000000111111100111101, 254 cb191 = 32’b00000000000100011100001100001011, 255 cb192 = 32’b00000000000000010011000011101111, 256 cb193 = 32’b00000000000011011111010001010011, 257 cb194 = 32’b00000000000000000000010000000000, 258 cb195 = 32’b00000000000000010101010011100001, 259 cb196 = 32’b00000000000000000101011110000100, 260 cb197 = 32’b00000000000010001110111101110100, 261 cb198 = 32’b10000000000000100101000011100110, 262 cb199 = 32’b10000000000001010110010100100010, 263 cb200 = 32’b00000000000000001100001000110100, 264 cb201 = 32’b00000000000000011111011011101001, 265 cb202 = 32’b00000000000000000011110111000111, 266 cb203 = 32’b10000000000000110011110011011001, 267 cb204 = 32’b00000000000000000100010001100100, 268 cb205 = 32’b10000000000010110011110000000001, 269 cb206 = 32’b10000000000000000100010111101011, 270 cb207 = 32’b00000000001000001001111111110010, 271 cb208 = 32’b00000000000000011100000011100110, 272 cb209 = 32’b00000000001010000110111010010111, 273 cb210 = 32’b10000000000000001100100010110100,

218 274 cb211 = 32’b00000000000000110000101110110110, 275 cb212 = 32’b00000000000000001011010010111011, 276 cb213 = 32’b00000000000001011010100101000011, 277 cb214 = 32’b10000000000000010110001011101011, 278 cb215 = 32’b00000000000000010101101010000010, 279 cb216 = 32’b00000000000000100110000001011111, 280 cb217 = 32’b00000000000000011010110011000010, 281 cb218 = 32’b00000000000000000011111000110011, 282 cb219 = 32’b00000000000001001011101101110000, 283 cb220 = 32’b00000000000000000111110111000001, 284 cb221 = 32’b00000000000000000101101010100011, 285 cb222 = 32’b10000000000000011001101101010100, 286 cb223 = 32’b00000000000010001010100010110000, 287 cb224 = 32’b00000000000000010010101011000111, 288 cb225 = 32’b00000000000001011111110010110010, 289 cb226 = 32’b10000000000000000010001100111001, 290 cb227 = 32’b10000000000011000000101010101100, 291 cb228 = 32’b10000000000000000100000001011010, 292 cb229 = 32’b00000000000010100110010110101110, 293 cb230 = 32’b10000000000000010110111001110111, 294 cb231 = 32’b10000000000010001110011101110011, 295 cb232 = 32’b00000000000000001111110011111111, 296 cb233 = 32’b10000000000011010011010110000001, 297 cb234 = 32’b00000000000000000100001011110000, 298 cb235 = 32’b10000000000001100101101011011111, 299 cb236 = 32’b00000000000000000110010101011011, 300 cb237 = 32’b10000000000000001011001111011000, 301 cb238 = 32’b00000000000000000100100010100000, 302 cb239 = 32’b00000000000110101110011001001100, 303 cb240 = 32’b00000000000000000110101111000011, 304 cb241 = 32’b00000000000011110111000100011001, 305 cb242 = 32’b10000000000000000101101100010101, 306 cb243 = 32’b10000000000011011011101001010001, 307 cb244 = 32’b00000000000000001000011100000001, 308 cb245 = 32’b00000000000011000110011000000100, 309 cb246 = 32’b10000000000000010010101101101000, 310 cb247 = 32’b10000000000011111111111110011101, 311 cb248 = 32’b00000000000000011110100000011100, 312 cb249 = 32’b10000000000001011101000011101000, 313 cb250 = 32’b00000000000000000101101010111111, 314 cb251 = 32’b00000000000000111101101000000000, 315 cb252 = 32’b00000000000000001101001101100101, 316 cb253 = 32’b10000000000001000010100110100010, 317 cb254 = 32’b10000000000000000111110101111101, 318 cb255 = 32’b00000000000011010000111010100100,

219 319 cb256 = 32’b00000000000000100100000101111010, 320 cb257 = 32’b00000000000011011000011011000010, 321 cb258 = 32’b10000000000000000000000101000100, 322 cb259 = 32’b10000000000000110011110010110100, 323 cb260 = 32’b00000000000000000000011011010110, 324 cb261 = 32’b00000000000001111101110111001111, 325 cb262 = 32’b10000000000000011100111101110100, 326 cb263 = 32’b10000000000000000111001110000000, 327 cb264 = 32’b00000000000000010001010101110101, 328 cb265 = 32’b10000000000000000010111100000001, 329 cb266 = 32’b00000000000000000010001011000110, 330 cb267 = 32’b10000000000000100100010000111110, 331 cb268 = 32’b00000000000000000110000000110101, 332 cb269 = 32’b10000000000001011000001100100010, 333 cb270 = 32’b10000000000000011111011101101000, 334 cb271 = 32’b00000000001001101010111011010010, 335 cb272 = 32’b00000000000000011111101001011101, 336 cb273 = 32’b00000000000110001001000011000100, 337 cb274 = 32’b10000000000000001011010001100100, 338 cb275 = 32’b00000000000001100101101111011010, 339 cb276 = 32’b00000000000000000111101100010100, 340 cb277 = 32’b00000000000001110000110100111111, 341 cb278 = 32’b10000000000000001111100111110110, 342 cb279 = 32’b10000000000000100110110000111000, 343 cb280 = 32’b00000000000000101000000010001100, 344 cb281 = 32’b00000000000001101100001001100100, 345 cb282 = 32’b00000000000000000001010101100110, 346 cb283 = 32’b00000000000000110100001001000000, 347 cb284 = 32’b00000000000000001000101100101011, 348 cb285 = 32’b00000000000000001110100011110110, 349 cb286 = 32’b10000000000000010011101101100001, 350 cb287 = 32’b00000000000101110001011101101100, 351 cb288 = 32’b00000000000000001100100100010110, 352 cb289 = 32’b00000000000011101100111010010111, 353 cb290 = 32’b10000000000000000011011010101011, 354 cb291 = 32’b00000000000000011011000000100000, 355 cb292 = 32’b00000000000000000000000100110111, 356 cb293 = 32’b00000000000100100010101111111011, 357 cb294 = 32’b10000000000000011000110000010100, 358 cb295 = 32’b10000000000100000001110111100110, 359 cb296 = 32’b00000000000000011000000001000100, 360 cb297 = 32’b10000000000000110100011111111000, 361 cb298 = 32’b00000000000000000001010010000011, 362 cb299 = 32’b10000000000001001010001001111101, 363 cb300 = 32’b00000000000000000111101000000001,

220 364 cb301 = 32’b10000000000000100010111001010001, 365 cb302 = 32’b00000000000000000111000101000101, 366 cb303 = 32’b00000000001010000100110111010010, 367 cb304 = 32’b00000000000000010001001010100001, 368 cb305 = 32’b00000000000110111001011110001101, 369 cb306 = 32’b10000000000000001001100001000000, 370 cb307 = 32’b10000000000001000010101010110100, 371 cb308 = 32’b00000000000000000110110000100111, 372 cb309 = 32’b00000000000001111001110110111000, 373 cb310 = 32’b10000000000000001110110101110010, 374 cb311 = 32’b10000000000001110100011000111111, 375 cb312 = 32’b00000000000000011111110111011010, 376 cb313 = 32’b00000000000000010100101111011110, 377 cb314 = 32’b00000000000000000100101010010011, 378 cb315 = 32’b00000000000000100110011000010110, 379 cb316 = 32’b00000000000000001011100010011000, 380 cb317 = 32’b10000000000000011111001101011011, 381 cb318 = 32’b10000000000000001100110111100011, 382 cb319 = 32’b00000000000110001110110111110011, 383 cb320 = 32’b00000000000000011010010111111100, 384 cb321 = 32’b00000000000100110001111010100100, 385 cb322 = 32’b00000000000000000000111110010011, 386 cb323 = 32’b10000000000000001001011100110100, 387 cb324 = 32’b00000000000000000100010000011110, 388 cb325 = 32’b00000000000010010001101001101110, 389 cb326 = 32’b10000000000000011111010100011000, 390 cb327 = 32’b10000000000000101110001001110101, 391 cb328 = 32’b00000000000000010001110111101111, 392 cb329 = 32’b00000000000000101010110000100010, 393 cb330 = 32’b00000000000000000101101011000101, 394 cb331 = 32’b10000000000000101011111110100000, 395 cb332 = 32’b00000000000000000101010010101010, 396 cb333 = 32’b10000000000011100010011111110110, 397 cb334 = 32’b10000000000000001000011100100001, 398 cb335 = 32’b00000000001001111001001101011010, 399 cb336 = 32’b00000000000000001111110110111100, 400 cb337 = 32’b00000000001010110011000111101011, 401 cb338 = 32’b10000000000000001001011011110001, 402 cb339 = 32’b00000000000000010100010011101001, 403 cb340 = 32’b00000000000000001100100110010011, 404 cb341 = 32’b00000000000010001011101100001111, 405 cb342 = 32’b10000000000000010000001110001000, 406 cb343 = 32’b00000000000000010000011001101010, 407 cb344 = 32’b00000000000000101101001101001101, 408 cb345 = 32’b00000000000000011110010100110111,

221 409 cb346 = 32’b00000000000000000011110110101010, 410 cb347 = 32’b00000000000000101011111011011101, 411 cb348 = 32’b00000000000000000110110101011100, 412 cb349 = 32’b00000000000000101000101101100001, 413 cb350 = 32’b10000000000000011111001111111111, 414 cb351 = 32’b00000000000011000011111001110110, 415 cb352 = 32’b00000000000000010111001011011000, 416 cb353 = 32’b00000000000011000000111110001010, 417 cb354 = 32’b10000000000000000011010111100010, 418 cb355 = 32’b10000000000000110110000100001010, 419 cb356 = 32’b10000000000000000000111010000100, 420 cb357 = 32’b00000000000010100011010000111001, 421 cb358 = 32’b10000000000000011010011100000001, 422 cb359 = 32’b10000000000001010001101001001101, 423 cb360 = 32’b00000000000000010100101101110100, 424 cb361 = 32’b10000000000011000100010101010011, 425 cb362 = 32’b00000000000000000001110010010010, 426 cb363 = 32’b10000000000010001010110100001001, 427 cb364 = 32’b00000000000000000101001110011110, 428 cb365 = 32’b10000000000000010010101011101001, 429 cb366 = 32’b00000000000000000000010110010011, 430 cb367 = 32’b00000000000111110010000000110100, 431 cb368 = 32’b00000000000000000111010010010000, 432 cb369 = 32’b00000000000101010111011111101001, 433 cb370 = 32’b10000000000000000110000000011100, 434 cb371 = 32’b10000000000000110101111100000111, 435 cb372 = 32’b00000000000000000110010011000100, 436 cb373 = 32’b00000000000010110100110101001111, 437 cb374 = 32’b10000000000000001101100111111001, 438 cb375 = 32’b10000000000100110110101000110110, 439 cb376 = 32’b00000000000000100001101101100110, 440 cb377 = 32’b10000000000000100011101010010110, 441 cb378 = 32’b00000000000000000101111110001100, 442 cb379 = 32’b00000000000000011110110010001111, 443 cb380 = 32’b00000000000000001110001001101010, 444 cb381 = 32’b10000000000000011011100001110111, 445 cb382 = 32’b10000000000000001111100110100001, 446 cb383 = 32’b00000000000010011101011100010010, 447 cb384 = 32’b00000000000000100000000011011000, 448 cb385 = 32’b00000000000100010110010100111000, 449 cb386 = 32’b10000000000000000000100101110011, 450 cb387 = 32’b10000000000000010001110010000010, 451 cb388 = 32’b00000000000000000010011000000001, 452 cb389 = 32’b00000000000001010110011001100100, 453 cb390 = 32’b10000000000000011110101000010110,

222 454 cb391 = 32’b00000000000001001100011000011001, 455 cb392 = 32’b00000000000000010111001010101010, 456 cb393 = 32’b00000000000000001000100110000000, 457 cb394 = 32’b00000000000000000011000111101010, 458 cb395 = 32’b10000000000000010000100111000110, 459 cb396 = 32’b00000000000000000111111011101010, 460 cb397 = 32’b10000000000010011111010001111100, 461 cb398 = 32’b10000000000000010000111100011001, 462 cb399 = 32’b00000000001000001111001001110101, 463 cb400 = 32’b00000000000000100000001011011111, 464 cb401 = 32’b00000000001000000111010001010011, 465 cb402 = 32’b10000000000000000100111101000101, 466 cb403 = 32’b00000000000001001011100000010111, 467 cb404 = 32’b00000000000000000110111110100011, 468 cb405 = 32’b00000000000001001010001010110001, 469 cb406 = 32’b10000000000000010011110010110011, 470 cb407 = 32’b10000000000000010100000100011000, 471 cb408 = 32’b00000000000000100000010111010010, 472 cb409 = 32’b00000000000010010110110110100111, 473 cb410 = 32’b00000000000000000011000010111010, 474 cb411 = 32’b00000000000000010111010111110101, 475 cb412 = 32’b00000000000000000111101010100000, 476 cb413 = 32’b00000000000000100111110000011011, 477 cb414 = 32’b10000000000000010001010000010111, 478 cb415 = 32’b00000000000100000011100011000001, 479 cb416 = 32’b00000000000000010011010100100111, 480 cb417 = 32’b00000000000010011010011101111010, 481 cb418 = 32’b10000000000000000100001000010001, 482 cb419 = 32’b10000000000000011010110000011111, 483 cb420 = 32’b00000000000000000001001001100100, 484 cb421 = 32’b00000000000011010110101001111110, 485 cb422 = 32’b10000000000000011110000010010010, 486 cb423 = 32’b10000000000100000001001001101110, 487 cb424 = 32’b00000000000000010100101000100001, 488 cb425 = 32’b10000000000001001101111100000101, 489 cb426 = 32’b00000000000000000001000101010101, 490 cb427 = 32’b10000000000011010111000101010100, 491 cb428 = 32’b00000000000000000110111110000000, 492 cb429 = 32’b10000000000001000010101001011110, 493 cb430 = 32’b00000000000000000111011101010100, 494 cb431 = 32’b00000000000111101001011011101001, 495 cb432 = 32’b00000000000000001110011110100111, 496 cb433 = 32’b00000000000101011001100100010110, 497 cb434 = 32’b10000000000000001000010010110011, 498 cb435 = 32’b10000000000000101000100000110100,

223 499 cb436 = 32’b00000000000000000101011001011101, 500 cb437 = 32’b00000000000001011010001100100011, 501 cb438 = 32’b10000000000000001000111000010010, 502 cb439 = 32’b10000000000100010110011010000111, 503 cb440 = 32’b00000000000000011011000100011111, 504 cb441 = 32’b00000000000000010010010101001111, 505 cb442 = 32’b00000000000000000011101001011001, 506 cb443 = 32’b00000000000000001110001110101000, 507 cb444 = 32’b00000000000000001001011001011001, 508 cb445 = 32’b10000000000001011011101011001111, 509 cb446 = 32’b10000000000000000100001100011011, 510 cb447 = 32’b00000000000100101010101010100110, 511 cb448 = 32’b00000000000000010110010100100001, 512 cb449 = 32’b00000000000100010000000010111110, 513 cb450 = 32’b10000000000000000000010011100011, 514 cb451 = 32’b00000000000001000100111011110001, 515 cb452 = 32’b00000000000000000100110111100010, 516 cb453 = 32’b00000000000011001010101101111110, 517 cb454 = 32’b10000000000000100001001011110101, 518 cb455 = 32’b10000000000001100111010111111001, 519 cb456 = 32’b00000000000000001110101110101000, 520 cb457 = 32’b00000000000000010011011010000100, 521 cb458 = 32’b00000000000000000100100011110000, 522 cb459 = 32’b10000000000000011100100100010100, 523 cb460 = 32’b00000000000000000011010110110000, 524 cb461 = 32’b10000000000100000000011000100100, 525 cb462 = 32’b10000000000000001010001011010101, 526 cb463 = 32’b00000000000111111001001110101001, 527 cb464 = 32’b00000000000000010101100110010010, 528 cb465 = 32’b00000000001000101010110101110000, 529 cb466 = 32’b10000000000000001111100010111100, 530 cb467 = 32’b00000000000001010100110100000101, 531 cb468 = 32’b00000000000000001001011100011010, 532 cb469 = 32’b00000000000001000111001100100000, 533 cb470 = 32’b10000000000000011001000101011111, 534 cb471 = 32’b00000000000000111001101000110110, 535 cb472 = 32’b00000000000000100010010100111111, 536 cb473 = 32’b00000000000001001000010001000011, 537 cb474 = 32’b00000000000000000100101111001000, 538 cb475 = 32’b00000000000001000001111011000011, 539 cb476 = 32’b00000000000000000111000111111111, 540 cb477 = 32’b00000000000000001101111001100111, 541 cb478 = 32’b10000000000000010111000100100010, 542 cb479 = 32’b00000000000011100010000011011110, 543 cb480 = 32’b00000000000000010101101100010010,

224 544 cb481 = 32’b00000000000001100000000111100100, 545 cb482 = 32’b10000000000000000000001101000111, 546 cb483 = 32’b10000000000001110111111100011111, 547 cb484 = 32’b10000000000000000110111000010100, 548 cb485 = 32’b00000000000010001000000000000111, 549 cb486 = 32’b10000000000000010011010001100110, 550 cb487 = 32’b10000000000001110001110011111110, 551 cb488 = 32’b00000000000000010001100111011100, 552 cb489 = 32’b10000000000001101101011000111001, 553 cb490 = 32’b00000000000000000011001001001011, 554 cb491 = 32’b10000000000001100011101111100111, 555 cb492 = 32’b00000000000000000110111111001110, 556 cb493 = 32’b10000000000000010010000100111001, 557 cb494 = 32’b00000000000000000010010000011011, 558 cb495 = 32’b00000000000101101101101011011010, 559 cb496 = 32’b00000000000000000100101001110011, 560 cb497 = 32’b00000000000100101100111110110111, 561 cb498 = 32’b10000000000000001000011110001111, 562 cb499 = 32’b10000000000001111011101110000101, 563 cb500 = 32’b00000000000000001010001001100000, 564 cb501 = 32’b00000000000010101100101000110000, 565 cb502 = 32’b10000000000000010101010110110000, 566 cb503 = 32’b10000000000101000101001101100111, 567 cb504 = 32’b00000000000000011101000011001101, 568 cb505 = 32’b10000000000000011110011100111111, 569 cb506 = 32’b00000000000000000110010100010000, 570 cb507 = 32’b00000000000000111100110000101110, 571 cb508 = 32’b00000000000000001011101110010001, 572 cb509 = 32’b10000000000010000010111100001110, 573 cb510 = 32’b10000000000000001011110111000010, 574 cb511 = 32’b00000000000010111100010010101111;

575

576

577

578 //------579 //-- Module Instantiations-- 580 //------581 parameter[N-1:0] ge_coeff0 = 32’b00000000000000001100110011001100; 582 parameter[N-1:0] ge_coeff1 = 32’b00000000000000001110011001100110;

583

584 reg[N-1:0] w0,w1; 585 reg[N-1:0] x0,x1,in_lt1,in_lt2,add1,add2,add3,add4,mult1,mult2,mult3, 586 mult4,in_logx1,in_logx2;

587

588 reg[N-1:0]e;

225 589

590 wire lt1; 591 wire[N-1:0] out_add1,out_add2,out_mult1,out_mult2,out_logx1,out_logx2;

592

593 reg[N-1:0] err0,err1,fn_err0,fn_err1,fn_w0,fn_w1,cw_x0,cw_x1,cw_xq0, 594 cw_xq1,in_x; 595 wire[N-1:0] nearest; 596 wire[N-1:0] cw_w0,cw_w1;

597

598 reg startcw,startfnw,startlog1,startlog2; 599 wire donecw,donefnw,donelog1,donelog2;

600

601 fplessthan#(Q,N) fplt1(in_lt1,in_lt2,lt1); 602 qadd#(Q,N) adder1(add1,add2,out_add1); 603 qadd#(Q,N) adder2(add3,add4,out_add2);

604

605 qmult#(Q,N) multiplier1(mult1,mult2,out_mult1); 606 qmult#(Q,N) multiplier2(mult3,mult4,out_mult2);

607

608 //log10#(Q,N) calc_log10(in_logx,out_logx); 609 compute_weights_opt cw(startcw,clk,rst,cw_x0,cw_x1,cw_xq0,cw_xq1, 610 cw_w0,cw_w1,donecw); 611 find_nearest_weighted fnw(startfnw,clk,rst,fn_err0,fn_err1,fn_w0, 612 fn_w1,nearest,donefnw); 613 fp_log10 fplog1(startlog1,clk,rst,in_logx1,out_logx1,donelog1); 614 fp_log10 fplog2(startlog2,clk,rst,in_logx2,out_logx2,donelog2); 615 //------616 //-- Begin Declarations& Coding-- 617 //------

618

619 always@(posedge clk or negedge rst)// DetermineSTATE 620 begin

621

622 if(rst == 1’b0) 623 STATE <=START; 624 else 625 STATE <=NEXT_STATE;

626

627 end

628

629

630 always@(*)// DetermineNEXT_STATE 631 begin 632 case(STATE)

633

226 634 START: 635 begin 636 if(startewoe == 1’b1) 637 begin 638 NEXT_STATE=CHECK_E; 639 end 640 else 641 begin 642 NEXT_STATE=START; 643 end 644 end

645

646 CHECK_E: 647 begin 648 NEXT_STATE=SET_E; 649 end

650

651 SET_E: 652 begin 653 NEXT_STATE= PRECALC1_X0; 654 end

655

656 PRECALC1_X0: 657 begin 658 NEXT_STATE= PRECALC2_X0; 659 end

660

661 PRECALC2_X0: 662 begin 663 if(donelog1) 664 begin 665 NEXT_STATE= PRE_CALC3_X0; 666 end 667 else 668 begin 669 NEXT_STATE= PRECALC2_X0; 670 end 671 end

672

673 PRE_CALC3_X0: 674 begin 675 NEXT_STATE= CALC_X0; 676 end

677

678 CALC_X0:

227 679 begin 680 if(donelog2) 681 begin 682 NEXT_STATE= PRECALC_X1; 683 end 684 else 685 begin 686 NEXT_STATE= CALC_X0; 687 end 688 end

689

690 PRECALC_X1: 691 begin 692 NEXT_STATE= CALC_X1; 693 end

694

695 CALC_X1: 696 begin 697 NEXT_STATE=SET_CW; 698 end

699

700 SET_CW: 701 begin 702 if(donecw) 703 begin 704 NEXT_STATE=CALC_CW; 705 end 706 else 707 begin 708 NEXT_STATE=SET_CW; 709 end 710 end

711

712 CALC_CW: 713 begin 714 NEXT_STATE= PRECALC1_ERR; 715 end

716

717 PRECALC1_ERR: 718 begin 719 NEXT_STATE= PRECALC2_ERR; 720 end

721

722 PRECALC2_ERR: 723 begin

228 724 NEXT_STATE=CALC_ERR; 725 end

726

727 CALC_ERR: 728 begin 729 NEXT_STATE=SET_FNW; 730 end

731

732 SET_FNW: 733 begin 734 if(donefnw) 735 begin 736 NEXT_STATE=CALC_FNW; 737 end 738 else 739 begin 740 NEXT_STATE=SET_FNW; 741 end 742 end

743

744 CALC_FNW: 745 begin 746 NEXT_STATE= XQ0_MULT; 747 end

748

749 XQ0_MULT: 750 begin 751 NEXT_STATE= XQ0_ADD; 752 end

753

754 XQ0_ADD: 755 begin 756 NEXT_STATE= SET_XQ0; 757 end

758

759 SET_XQ0: 760 begin 761 NEXT_STATE=DONE; 762 end

763

764 DONE: 765 begin 766 NEXT_STATE=START; 767 end

768

229 769 endcase 770 end

771

772

773 always@(posedge clk or negedge rst)// Determine outputs 774 begin

775

776 if(rst == 1’b0) 777 begin 778 e <= 32’b0; 779 doneewoe <= 1’b0;

780

781 end

782

783 else 784 begin 785 case(STATE)

786

787 START: 788 begin 789 startfnw <= 1’b0; 790 startcw <= 1’b0; 791 startlog1 <= 1’b0; 792 startlog2 <= 1’b0; 793 doneewoe <= 1’b0; 794 end

795

796 CHECK_E: 797 begin 798 in_lt1 <= in_e; 799 in_lt2 <= 32’b0; 800 end

801

802 SET_E: 803 begin 804 if(lt1) 805 begin 806 e <= 32’b0; 807 end 808 else 809 begin 810 e <= in_e; 811 end 812 end

813

230 814 PRECALC1_X0: 815 begin 816 mult1 <= model_wo; 817 mult2 <= 32’b00000000000110010111011011111100;

818

819 //check_e <=e; 820 add1 <=e; 821 add2 <= 32’b00000000000000000000000000000110; 822 end

823

824 PRECALC2_X0: 825 begin 826 //check_mult <= out_mult1; 827 in_logx1 <= out_mult1; 828 startlog1 <= 1’b1; 829 end

830

831 PRE_CALC3_X0: 832 begin 833 mult1 <= out_logx1; 834 mult2 <= 32’b00000000000000110101001001101001; 835 startlog1 <= 1’b0; 836 end

837

838 CALC_X0: 839 begin 840 x0 <= out_mult1; 841 in_logx2 <= out_add1; 842 startlog2 <= 1’b1; 843 end

844

845 PRECALC_X1: 846 begin 847 mult1 <= 32’b00000000000010100000000000000000; 848 mult2 <= out_logx2; 849 startlog2 <= 1’b0; 850 end

851

852 CALC_X1: 853 begin 854 x1 <= out_mult1; 855 startcw <= 1’b1; 856 end

857

858 SET_CW:

231 859 begin 860 cw_x0 <= x0; 861 cw_x1 <= x1; 862 cw_xq0 <= xq0; 863 cw_xq1 <= xq1; 864 startcw <= 1’b0; 865 end

866

867 CALC_CW: 868 begin 869 w0 <= cw_w0; 870 w1 <= cw_w1; 871 end

872

873 PRECALC1_ERR: 874 begin 875 mult1 <= ge_coeff0; 876 mult2 <= xq0; 877 mult3 <= ge_coeff1; 878 mult4 <= xq1; 879 end

880

881 PRECALC2_ERR: 882 begin 883 add1 <= x0; 884 add2 <= {(out_mult1[N-1] == 0)?1’b1:1’b0,out_mult1[N-2:0]}; 885 add3 <= x1; 886 add4 <= {(out_mult2[N-1] == 0)?1’b1:1’b0,out_mult2[N-2:0]}; 887 end

888

889 CALC_ERR: 890 begin 891 err0 <= out_add1; 892 err1 <= out_add2; 893 startfnw <= 1’b1; 894 end

895

896 SET_FNW: 897 begin 898 fn_err0 <= err0; 899 fn_err1 <= err1; 900 fn_w0 <= w0; 901 fn_w1 <= w1; 902 startfnw <= 1’b0; 903 end

232 904

905 CALC_FNW: 906 begin 907 out_n1 <= nearest; 908 end

909

910 XQ0_MULT: 911 begin 912 mult1 <= ge_coeff0; 913 mult2 <= xq0;

914

915 mult3 <= ge_coeff1; 916 mult4 <= xq1; 917 end

918

919 XQ0_ADD: 920 begin 921 add1 <= out_mult1; 922 add3 <= out_mult2; 923 case(2* out_n1) 924 10’d0: add2 <= cb0; 925 10’d2: add2 <= cb2; 926 10’d4: add2 <= cb4; 927 10’d6: add2 <= cb6; 928 10’d8: add2 <= cb8; 929 10’d10: add2 <= cb10; 930 10’d12: add2 <= cb12; 931 10’d14: add2 <= cb14; 932 10’d16: add2 <= cb16; 933 10’d18: add2 <= cb18; 934 10’d20: add2 <= cb20; 935 10’d22: add2 <= cb22; 936 10’d24: add2 <= cb24; 937 10’d26: add2 <= cb26; 938 10’d28: add2 <= cb28; 939 10’d30: add2 <= cb30; 940 10’d32: add2 <= cb32; 941 10’d34: add2 <= cb34; 942 10’d36: add2 <= cb36; 943 10’d38: add2 <= cb38; 944 10’d40: add2 <= cb40; 945 10’d42: add2 <= cb42; 946 10’d44: add2 <= cb44; 947 10’d46: add2 <= cb46; 948 10’d48: add2 <= cb48;

233 949 10’d50: add2 <= cb50; 950 10’d52: add2 <= cb52; 951 10’d54: add2 <= cb54; 952 10’d56: add2 <= cb56; 953 10’d58: add2 <= cb58; 954 10’d60: add2 <= cb60; 955 10’d62: add2 <= cb62; 956 10’d64: add2 <= cb64; 957 10’d66: add2 <= cb66; 958 10’d68: add2 <= cb68; 959 10’d70: add2 <= cb70; 960 10’d72: add2 <= cb72; 961 10’d74: add2 <= cb74; 962 10’d76: add2 <= cb76; 963 10’d78: add2 <= cb78; 964 10’d80: add2 <= cb80; 965 10’d82: add2 <= cb82; 966 10’d84: add2 <= cb84; 967 10’d86: add2 <= cb86; 968 10’d88: add2 <= cb88; 969 10’d90: add2 <= cb90; 970 10’d92: add2 <= cb92; 971 10’d94: add2 <= cb94; 972 10’d96: add2 <= cb96; 973 10’d98: add2 <= cb98; 974 10’d100: add2 <= cb100; 975 10’d102: add2 <= cb102; 976 10’d104: add2 <= cb104; 977 10’d106: add2 <= cb106; 978 10’d108: add2 <= cb108; 979 10’d110: add2 <= cb110; 980 10’d112: add2 <= cb112; 981 10’d114: add2 <= cb114; 982 10’d116: add2 <= cb116; 983 10’d118: add2 <= cb118; 984 10’d120: add2 <= cb120; 985 10’d122: add2 <= cb122; 986 10’d124: add2 <= cb124; 987 10’d126: add2 <= cb126; 988 10’d128: add2 <= cb128; 989 10’d130: add2 <= cb130; 990 10’d132: add2 <= cb132; 991 10’d134: add2 <= cb134; 992 10’d136: add2 <= cb136; 993 10’d138: add2 <= cb138;

234 994 10’d140: add2 <= cb140; 995 10’d142: add2 <= cb142; 996 10’d144: add2 <= cb144; 997 10’d146: add2 <= cb146; 998 10’d148: add2 <= cb148; 999 10’d150: add2 <= cb150; 1000 10’d152: add2 <= cb152; 1001 10’d154: add2 <= cb154; 1002 10’d156: add2 <= cb156; 1003 10’d158: add2 <= cb158; 1004 10’d160: add2 <= cb160; 1005 10’d162: add2 <= cb162; 1006 10’d164: add2 <= cb164; 1007 10’d166: add2 <= cb166; 1008 10’d168: add2 <= cb168; 1009 10’d170: add2 <= cb170; 1010 10’d172: add2 <= cb172; 1011 10’d174: add2 <= cb174; 1012 10’d176: add2 <= cb176; 1013 10’d178: add2 <= cb178; 1014 10’d180: add2 <= cb180; 1015 10’d182: add2 <= cb182; 1016 10’d184: add2 <= cb184; 1017 10’d186: add2 <= cb186; 1018 10’d188: add2 <= cb188; 1019 10’d190: add2 <= cb190; 1020 10’d192: add2 <= cb192; 1021 10’d194: add2 <= cb194; 1022 10’d196: add2 <= cb196; 1023 10’d198: add2 <= cb198; 1024 10’d200: add2 <= cb200; 1025 10’d202: add2 <= cb202; 1026 10’d204: add2 <= cb204; 1027 10’d206: add2 <= cb206; 1028 10’d208: add2 <= cb208; 1029 10’d210: add2 <= cb210; 1030 10’d212: add2 <= cb212; 1031 10’d214: add2 <= cb214; 1032 10’d216: add2 <= cb216; 1033 10’d218: add2 <= cb218; 1034 10’d220: add2 <= cb220; 1035 10’d222: add2 <= cb222; 1036 10’d224: add2 <= cb224; 1037 10’d226: add2 <= cb226; 1038 10’d228: add2 <= cb228;

235 1039 10’d230: add2 <= cb230; 1040 10’d232: add2 <= cb232; 1041 10’d234: add2 <= cb234; 1042 10’d236: add2 <= cb236; 1043 10’d238: add2 <= cb238; 1044 10’d240: add2 <= cb240; 1045 10’d242: add2 <= cb242; 1046 10’d244: add2 <= cb244; 1047 10’d246: add2 <= cb246; 1048 10’d248: add2 <= cb248; 1049 10’d250: add2 <= cb250; 1050 10’d252: add2 <= cb252; 1051 10’d254: add2 <= cb254; 1052 10’d256: add2 <= cb256; 1053 10’d258: add2 <= cb258; 1054 10’d260: add2 <= cb260; 1055 10’d262: add2 <= cb262; 1056 10’d264: add2 <= cb264; 1057 10’d266: add2 <= cb266; 1058 10’d268: add2 <= cb268; 1059 10’d270: add2 <= cb270; 1060 10’d272: add2 <= cb272; 1061 10’d274: add2 <= cb274; 1062 10’d276: add2 <= cb276; 1063 10’d278: add2 <= cb278; 1064 10’d280: add2 <= cb280; 1065 10’d282: add2 <= cb282; 1066 10’d284: add2 <= cb284; 1067 10’d286: add2 <= cb286; 1068 10’d288: add2 <= cb288; 1069 10’d290: add2 <= cb290; 1070 10’d292: add2 <= cb292; 1071 10’d294: add2 <= cb294; 1072 10’d296: add2 <= cb296; 1073 10’d298: add2 <= cb298; 1074 10’d300: add2 <= cb300; 1075 10’d302: add2 <= cb302; 1076 10’d304: add2 <= cb304; 1077 10’d306: add2 <= cb306; 1078 10’d308: add2 <= cb308; 1079 10’d310: add2 <= cb310; 1080 10’d312: add2 <= cb312; 1081 10’d314: add2 <= cb314; 1082 10’d316: add2 <= cb316; 1083 10’d318: add2 <= cb318;

236 1084 10’d320: add2 <= cb320; 1085 10’d322: add2 <= cb322; 1086 10’d324: add2 <= cb324; 1087 10’d326: add2 <= cb326; 1088 10’d328: add2 <= cb328; 1089 10’d330: add2 <= cb330; 1090 10’d332: add2 <= cb332; 1091 10’d334: add2 <= cb334; 1092 10’d336: add2 <= cb336; 1093 10’d338: add2 <= cb338; 1094 10’d340: add2 <= cb340; 1095 10’d342: add2 <= cb342; 1096 10’d344: add2 <= cb344; 1097 10’d346: add2 <= cb346; 1098 10’d348: add2 <= cb348; 1099 10’d350: add2 <= cb350; 1100 10’d352: add2 <= cb352; 1101 10’d354: add2 <= cb354; 1102 10’d356: add2 <= cb356; 1103 10’d358: add2 <= cb358; 1104 10’d360: add2 <= cb360; 1105 10’d362: add2 <= cb362; 1106 10’d364: add2 <= cb364; 1107 10’d366: add2 <= cb366; 1108 10’d368: add2 <= cb368; 1109 10’d370: add2 <= cb370; 1110 10’d372: add2 <= cb372; 1111 10’d374: add2 <= cb374; 1112 10’d376: add2 <= cb376; 1113 10’d378: add2 <= cb378; 1114 10’d380: add2 <= cb380; 1115 10’d382: add2 <= cb382; 1116 10’d384: add2 <= cb384; 1117 10’d386: add2 <= cb386; 1118 10’d388: add2 <= cb388; 1119 10’d390: add2 <= cb390; 1120 10’d392: add2 <= cb392; 1121 10’d394: add2 <= cb394; 1122 10’d396: add2 <= cb396; 1123 10’d398: add2 <= cb398; 1124 10’d400: add2 <= cb400; 1125 10’d402: add2 <= cb402; 1126 10’d404: add2 <= cb404; 1127 10’d406: add2 <= cb406; 1128 10’d408: add2 <= cb408;

237 1129 10’d410: add2 <= cb410; 1130 10’d412: add2 <= cb412; 1131 10’d414: add2 <= cb414; 1132 10’d416: add2 <= cb416; 1133 10’d418: add2 <= cb418; 1134 10’d420: add2 <= cb420; 1135 10’d422: add2 <= cb422; 1136 10’d424: add2 <= cb424; 1137 10’d426: add2 <= cb426; 1138 10’d428: add2 <= cb428; 1139 10’d430: add2 <= cb430; 1140 10’d432: add2 <= cb432; 1141 10’d434: add2 <= cb434; 1142 10’d436: add2 <= cb436; 1143 10’d438: add2 <= cb438; 1144 10’d440: add2 <= cb440; 1145 10’d442: add2 <= cb442; 1146 10’d444: add2 <= cb444; 1147 10’d446: add2 <= cb446; 1148 10’d448: add2 <= cb448; 1149 10’d450: add2 <= cb450; 1150 10’d452: add2 <= cb452; 1151 10’d454: add2 <= cb454; 1152 10’d456: add2 <= cb456; 1153 10’d458: add2 <= cb458; 1154 10’d460: add2 <= cb460; 1155 10’d462: add2 <= cb462; 1156 10’d464: add2 <= cb464; 1157 10’d466: add2 <= cb466; 1158 10’d468: add2 <= cb468; 1159 10’d470: add2 <= cb470; 1160 10’d472: add2 <= cb472; 1161 10’d474: add2 <= cb474; 1162 10’d476: add2 <= cb476; 1163 10’d478: add2 <= cb478; 1164 10’d480: add2 <= cb480; 1165 10’d482: add2 <= cb482; 1166 10’d484: add2 <= cb484; 1167 10’d486: add2 <= cb486; 1168 10’d488: add2 <= cb488; 1169 10’d490: add2 <= cb490; 1170 10’d492: add2 <= cb492; 1171 10’d494: add2 <= cb494; 1172 10’d496: add2 <= cb496; 1173 10’d498: add2 <= cb498;

238 1174 10’d500: add2 <= cb500; 1175 10’d502: add2 <= cb502; 1176 10’d504: add2 <= cb504; 1177 10’d506: add2 <= cb506; 1178 10’d508: add2 <= cb508; 1179 10’d510: add2 <= cb510;

1180

1181 endcase

1182

1183 case( (2 * out_n1)+1) 1184 10’d1: add4 <= cb1; 1185 10’d3: add4 <= cb3; 1186 10’d5: add4 <= cb5; 1187 10’d7: add4 <= cb7; 1188 10’d9: add4 <= cb9; 1189 10’d11: add4 <= cb11; 1190 10’d13: add4 <= cb13; 1191 10’d15: add4 <= cb15; 1192 10’d17: add4 <= cb17; 1193 10’d19: add4 <= cb19; 1194 10’d21: add4 <= cb21; 1195 10’d23: add4 <= cb23; 1196 10’d25: add4 <= cb25; 1197 10’d27: add4 <= cb27; 1198 10’d29: add4 <= cb29; 1199 10’d31: add4 <= cb31; 1200 10’d33: add4 <= cb33; 1201 10’d35: add4 <= cb35; 1202 10’d37: add4 <= cb37; 1203 10’d39: add4 <= cb39; 1204 10’d41: add4 <= cb41; 1205 10’d43: add4 <= cb43; 1206 10’d45: add4 <= cb45; 1207 10’d47: add4 <= cb47; 1208 10’d49: add4 <= cb49; 1209 10’d51: add4 <= cb51; 1210 10’d53: add4 <= cb53; 1211 10’d55: add4 <= cb55; 1212 10’d57: add4 <= cb57; 1213 10’d59: add4 <= cb59; 1214 10’d61: add4 <= cb61; 1215 10’d63: add4 <= cb63; 1216 10’d65: add4 <= cb65; 1217 10’d67: add4 <= cb67; 1218 10’d69: add4 <= cb69;

239 1219 10’d71: add4 <= cb71; 1220 10’d73: add4 <= cb73; 1221 10’d75: add4 <= cb75; 1222 10’d77: add4 <= cb77; 1223 10’d79: add4 <= cb79; 1224 10’d81: add4 <= cb81; 1225 10’d83: add4 <= cb83; 1226 10’d85: add4 <= cb85; 1227 10’d87: add4 <= cb87; 1228 10’d89: add4 <= cb89; 1229 10’d91: add4 <= cb91; 1230 10’d93: add4 <= cb93; 1231 10’d95: add4 <= cb95; 1232 10’d97: add4 <= cb97; 1233 10’d99: add4 <= cb99; 1234 10’d101: add4 <= cb101; 1235 10’d103: add4 <= cb103; 1236 10’d105: add4 <= cb105; 1237 10’d107: add4 <= cb107; 1238 10’d109: add4 <= cb109; 1239 10’d111: add4 <= cb111; 1240 10’d113: add4 <= cb113; 1241 10’d115: add4 <= cb115; 1242 10’d117: add4 <= cb117; 1243 10’d119: add4 <= cb119; 1244 10’d121: add4 <= cb121; 1245 10’d123: add4 <= cb123; 1246 10’d125: add4 <= cb125; 1247 10’d127: add4 <= cb127; 1248 10’d129: add4 <= cb129; 1249 10’d131: add4 <= cb131; 1250 10’d133: add4 <= cb133; 1251 10’d135: add4 <= cb135; 1252 10’d137: add4 <= cb137; 1253 10’d139: add4 <= cb139; 1254 10’d141: add4 <= cb141; 1255 10’d143: add4 <= cb143; 1256 10’d145: add4 <= cb145; 1257 10’d147: add4 <= cb147; 1258 10’d149: add4 <= cb149; 1259 10’d151: add4 <= cb151; 1260 10’d153: add4 <= cb153; 1261 10’d155: add4 <= cb155; 1262 10’d157: add4 <= cb157; 1263 10’d159: add4 <= cb159;

240 1264 10’d161: add4 <= cb161; 1265 10’d163: add4 <= cb163; 1266 10’d165: add4 <= cb165; 1267 10’d167: add4 <= cb167; 1268 10’d169: add4 <= cb169; 1269 10’d171: add4 <= cb171; 1270 10’d173: add4 <= cb173; 1271 10’d175: add4 <= cb175; 1272 10’d177: add4 <= cb177; 1273 10’d179: add4 <= cb179; 1274 10’d181: add4 <= cb181; 1275 10’d183: add4 <= cb183; 1276 10’d185: add4 <= cb185; 1277 10’d187: add4 <= cb187; 1278 10’d189: add4 <= cb189; 1279 10’d191: add4 <= cb191; 1280 10’d193: add4 <= cb193; 1281 10’d195: add4 <= cb195; 1282 10’d197: add4 <= cb197; 1283 10’d199: add4 <= cb199; 1284 10’d201: add4 <= cb201; 1285 10’d203: add4 <= cb203; 1286 10’d205: add4 <= cb205; 1287 10’d207: add4 <= cb207; 1288 10’d209: add4 <= cb209; 1289 10’d211: add4 <= cb211; 1290 10’d213: add4 <= cb213; 1291 10’d215: add4 <= cb215; 1292 10’d217: add4 <= cb217; 1293 10’d219: add4 <= cb219; 1294 10’d221: add4 <= cb221; 1295 10’d223: add4 <= cb223; 1296 10’d225: add4 <= cb225; 1297 10’d227: add4 <= cb227; 1298 10’d229: add4 <= cb229; 1299 10’d231: add4 <= cb231; 1300 10’d233: add4 <= cb233; 1301 10’d235: add4 <= cb235; 1302 10’d237: add4 <= cb237; 1303 10’d239: add4 <= cb239; 1304 10’d241: add4 <= cb241; 1305 10’d243: add4 <= cb243; 1306 10’d245: add4 <= cb245; 1307 10’d247: add4 <= cb247; 1308 10’d249: add4 <= cb249;

241 1309 10’d251: add4 <= cb251; 1310 10’d253: add4 <= cb253; 1311 10’d255: add4 <= cb255; 1312 10’d257: add4 <= cb257; 1313 10’d259: add4 <= cb259; 1314 10’d261: add4 <= cb261; 1315 10’d263: add4 <= cb263; 1316 10’d265: add4 <= cb265; 1317 10’d267: add4 <= cb267; 1318 10’d269: add4 <= cb269; 1319 10’d271: add4 <= cb271; 1320 10’d273: add4 <= cb273; 1321 10’d275: add4 <= cb275; 1322 10’d277: add4 <= cb277; 1323 10’d279: add4 <= cb279; 1324 10’d281: add4 <= cb281; 1325 10’d283: add4 <= cb283; 1326 10’d285: add4 <= cb285; 1327 10’d287: add4 <= cb287; 1328 10’d289: add4 <= cb289; 1329 10’d291: add4 <= cb291; 1330 10’d293: add4 <= cb293; 1331 10’d295: add4 <= cb295; 1332 10’d297: add4 <= cb297; 1333 10’d299: add4 <= cb299; 1334 10’d301: add4 <= cb301; 1335 10’d303: add4 <= cb303; 1336 10’d305: add4 <= cb305; 1337 10’d307: add4 <= cb307; 1338 10’d309: add4 <= cb309; 1339 10’d311: add4 <= cb311; 1340 10’d313: add4 <= cb313; 1341 10’d315: add4 <= cb315; 1342 10’d317: add4 <= cb317; 1343 10’d319: add4 <= cb319; 1344 10’d321: add4 <= cb321; 1345 10’d323: add4 <= cb323; 1346 10’d325: add4 <= cb325; 1347 10’d327: add4 <= cb327; 1348 10’d329: add4 <= cb329; 1349 10’d331: add4 <= cb331; 1350 10’d333: add4 <= cb333; 1351 10’d335: add4 <= cb335; 1352 10’d337: add4 <= cb337; 1353 10’d339: add4 <= cb339;

242 1354 10’d341: add4 <= cb341; 1355 10’d343: add4 <= cb343; 1356 10’d345: add4 <= cb345; 1357 10’d347: add4 <= cb347; 1358 10’d349: add4 <= cb349; 1359 10’d351: add4 <= cb351; 1360 10’d353: add4 <= cb353; 1361 10’d355: add4 <= cb355; 1362 10’d357: add4 <= cb357; 1363 10’d359: add4 <= cb359; 1364 10’d361: add4 <= cb361; 1365 10’d363: add4 <= cb363; 1366 10’d365: add4 <= cb365; 1367 10’d367: add4 <= cb367; 1368 10’d369: add4 <= cb369; 1369 10’d371: add4 <= cb371; 1370 10’d373: add4 <= cb373; 1371 10’d375: add4 <= cb375; 1372 10’d377: add4 <= cb377; 1373 10’d379: add4 <= cb379; 1374 10’d381: add4 <= cb381; 1375 10’d383: add4 <= cb383; 1376 10’d385: add4 <= cb385; 1377 10’d387: add4 <= cb387; 1378 10’d389: add4 <= cb389; 1379 10’d391: add4 <= cb391; 1380 10’d393: add4 <= cb393; 1381 10’d395: add4 <= cb395; 1382 10’d397: add4 <= cb397; 1383 10’d399: add4 <= cb399; 1384 10’d401: add4 <= cb401; 1385 10’d403: add4 <= cb403; 1386 10’d405: add4 <= cb405; 1387 10’d407: add4 <= cb407; 1388 10’d409: add4 <= cb409; 1389 10’d411: add4 <= cb411; 1390 10’d413: add4 <= cb413; 1391 10’d415: add4 <= cb415; 1392 10’d417: add4 <= cb417; 1393 10’d419: add4 <= cb419; 1394 10’d421: add4 <= cb421; 1395 10’d423: add4 <= cb423; 1396 10’d425: add4 <= cb425; 1397 10’d427: add4 <= cb427; 1398 10’d429: add4 <= cb429;

243 1399 10’d431: add4 <= cb431; 1400 10’d433: add4 <= cb433; 1401 10’d435: add4 <= cb435; 1402 10’d437: add4 <= cb437; 1403 10’d439: add4 <= cb439; 1404 10’d441: add4 <= cb441; 1405 10’d443: add4 <= cb443; 1406 10’d445: add4 <= cb445; 1407 10’d447: add4 <= cb447; 1408 10’d449: add4 <= cb449; 1409 10’d451: add4 <= cb451; 1410 10’d453: add4 <= cb453; 1411 10’d455: add4 <= cb455; 1412 10’d457: add4 <= cb457; 1413 10’d459: add4 <= cb459; 1414 10’d461: add4 <= cb461; 1415 10’d463: add4 <= cb463; 1416 10’d465: add4 <= cb465; 1417 10’d467: add4 <= cb467; 1418 10’d469: add4 <= cb469; 1419 10’d471: add4 <= cb471; 1420 10’d473: add4 <= cb473; 1421 10’d475: add4 <= cb475; 1422 10’d477: add4 <= cb477; 1423 10’d479: add4 <= cb479; 1424 10’d481: add4 <= cb481; 1425 10’d483: add4 <= cb483; 1426 10’d485: add4 <= cb485; 1427 10’d487: add4 <= cb487; 1428 10’d489: add4 <= cb489; 1429 10’d491: add4 <= cb491; 1430 10’d493: add4 <= cb493; 1431 10’d495: add4 <= cb495; 1432 10’d497: add4 <= cb497; 1433 10’d499: add4 <= cb499; 1434 10’d501: add4 <= cb501; 1435 10’d503: add4 <= cb503; 1436 10’d505: add4 <= cb505; 1437 10’d507: add4 <= cb507; 1438 10’d509: add4 <= cb509; 1439 10’d511: add4 <= cb511;

1440

1441 endcase 1442 end

1443

244 1444 SET_XQ0: 1445 begin 1446 out_xq0 <= out_add1; 1447 out_xq1 <= out_add2; 1448 end

1449

1450 DONE: 1451 begin 1452 doneewoe <= 1’b1; 1453 end

1454

1455 endcase 1456 end

1457

1458 end

1459

1460

1461 endmodule

245