C-BASED HARDWARE DESIGN OF IMDCT ACCELERATOR FOR OGG VORBIS DECODER Shinichi Maeta1, Atsushi Kosaka1, Akihisa Yamada1, 2, Takao Onoye1, Tohru Chiba1, 2, and Isao Shirakawa1 1Department of Information Systems Engineering, 2Sharp Corporation Graduate School of Information Science and Technology, 2613-1 Ichinomoto, Tenri, Nara, 632-8567 Japan Osaka University phone: +81 743 65 2531, fax: +81 743 65 3963, 2-1 Yamada-oka, Suita, Osaka, 565-0871 Japan email:
[email protected], phone: +81 6 6879 7808, fax: +81 6 6875 5902,
[email protected] email: {maeta, kosaka, onoye, sirakawa}@ist.osaka-u.ac.jp ABSTRACT ARM7TDMI is used as the embedded processor since it has This paper presents hardware design of an IMDCT accelera- come into wide use recently. tor for an Ogg Vorbis decoder using a C-based design sys- tem. Low power implementation of audio codec is important 2. OGG VORBIS CODEC in order to achieve long battery life of portable audio de- 2.1 Ogg Vorbis Overview vices. Through the computational cost analysis of the whole decoding process, it is found that Ogg Vorbis requires higher Figure 1 shows a block diagram of the Ogg Vorbis codec operation frequency of an embedded processor than MPEG processes outlined below. Audio. In order to reduce the CPU load, an accelerator is designed as specific hardware for IMDCT, which is detected MDCT Psycho Audio Remove Channel Acoustic VQ as the most computation-intensive functional block. Real- Signal Floor Coupling time decoding of Ogg Vorbis is achieved with the accelera- FFT Model Ogg Vorbis tor and an embedded processor both run at 36MHz.