ABSTRACT IMPLEMENTATION OF LOW-BIT RATE AUDIO CODEC, CODEC2, IN VERILOG ON MODERN FPGAS by Santhiya Sampath Kumar Audio compression codecs are an important application in the Internet of Things (IoT) where small sensing devices will gather voice signals, but then need to transmit the information to aggregating servers at low cost. In this work, we implement and evaluate a hardware implementation of the Codec2, a lossy speech compression codec in Verilog and map it to an Intel CycloneIV FPGA. We describe the details of our implementation approach, including how we converted the C code of Codec2, how we represent data inside the hardware implementation and the associated cost of this implementation on a real FPGA. We then analyze our implementation compared to a microprocessor implementation to observe what performance we get on an FPGA versus a microprocessor. Our hardware implementation of Codec2 is qualitatively the same in terms of hearing the spoken transmission and has an error rate of 6.55 bits per frame (48 bits) and is 1.73 times faster than the microprocessor implementation. IMPLEMENTATION OF LOW-BIT RATE AUDIO CODEC, CODEC2, IN VERILOG ON MODERN FPGAS A Thesis Submitted to the Faculty of Miami University in partial fulfillment of the requirements for the degree of Master of Science by Santhiya Sampath Kumar Miami University Oxford, Ohio 2020 Advisor: Dr. Peter Jamieson Reader: Dr. Chi-Hao Cheng Reader: Dr. Sahin Gokhan ©2020 Santhiya Sampath Kumar This Thesis titled IMPLEMENTATION OF LOW-BIT RATE AUDIO CODEC, CODEC2, IN VERILOG ON MODERN FPGAS by Santhiya Sampath Kumar has been approved for publication by The College of Engineering and Computing and Department of Electrical and Computer Engineering ____________________________________________________ Dr. Peter Jamieson ______________________________________________________ Dr. Chi-Hao Cheng _______________________________________________________ Dr. Sahin Gokhan Table of Contents List of Tables v List of Figures vi Acknowledgements vii 1 Chapter 1 : Introduction 1 2 Chapter 2 : Background 3 2.1 Audio Compression ...................................................................................................... 3 2.2 Codec2 ......................................................................................................................... 3 2.3 Hardware Implementations of Lossy Audio Compression Codec ................................... 5 3 Chapter 3 : Implementation Details 7 3.1 Number Representation ................................................................................................. 7 3.2 C code to FSM .............................................................................................................. 8 3.3 External and Internal IP Cores for Base Operations ....................................................... 9 3.4 Memory model implementation of the C code in Verilog................................................. 10 3.5 Codec2 Modules ......................................................................................................... 12 4 Chapter 4 : Results 16 4.1 FPGA Utilization ........................................................................................................ 16 4.2 Quality of Implementation .......................................................................................... 17 4.3 Performance Results ................................................................................................... 20 5 Chapter 5 : Discussion on Converting Other Codec2 Configurations 23 6 Chapter 6 : Conclusion 24 References 25 A Finite State Machines of the Top Verilog Modules 27 A.1 codec2 encoder mode2400.v ...................................................................................... 27 A.2 codec2 encoder one frame mode2400.v ..................................................................... 28 A.3 analyse one frame.v .................................................................................................... 30 A.4 speech to uq lsps.v ..................................................................................................... 31 A.5 encode lsp scalar.v ..................................................................................................... 33 A.6 encode WoE.v...................................................................................................................... 34 B Verilog Implementation 35 B.1 codec2 encoder mode2400.v ...................................................................................... 35 B.2 CODEC2 encoder one frame mode2400.v ................................................................. 77 iii B.3 analyse one frame.v.................................................................................................. 116 B.4 speech to uq lsps.v ................................................................................................... 172 B.5 encode lsp scalar.v ................................................................................................... 200 B.6 encode WoE.v.................................................................................................................... 212 iv List of Tables 2.1 Allocation of bits per FRAME ................................................................................ 6 3.1 Cyclone IV EP4CE115F29C7 resource utilization of 32-bit multipliers ......................... 7 3.2 Encoder blocks and states.............................................................................................. 9 3.3 List of IP cores for Base Operations in our 32-bit representation used in the imple- mentation. ..................................................................................................................... 9 3.4 Verilog modules implemented for Codec2 Encoder ..................................................... 12 3.5 Resource utilization of the encoder blocks ................................................................... 14 4.1 Cyclone IV EP4CE115F29C7 resource utilization of Codec2 encoder to process one FRAME ........................................................................................................ 17 4.2 Cyclone IV EP4CE115F29C7 resource utilization of Codec2 encoder to process 150 FRAMES ..................................................................................................... 17 4.3 Cyclone IV EP4CGX150DF31I7AD resource utilization of Codec2 encoder to pro- cess one FRAME ................................................................................................. 17 4.4 Cyclone IV EP4CGX150DF31I7AD resource utilization of Codec2 encoder to pro- cess 150 FRAMES............................................................................................... 18 4.5 Timing Analysis of FPGA C2 Vs RaspberryPi’s ARM processor ................................ 21 v List of Figures 2.1 Digital Voice Radio System ........................................................................................... 4 2.2 Codec2 Encoder Block Diagram ................................................................................... 5 3.1 32-bit Fixed-point representation .................................................................................. 7 3.2 FSM model of the Codec2 encoder for one FRAME (20 ms) ........................................ 8 3.3 FSM model with parallel states ................................................................................... 10 3.4 An example of RAM implementation .......................................................................... 11 3.5 C to FSM conversion .................................................................................................. 13 3.6 Codec2 Verilog module names overlaid in the block diagram ...................................... 15 4.1 Codec2 output of the hts1a.raw processed in C ............................................................ 18 4.2 Codec2 output of the hts1a.raw processed in Verilog ....................................................... 19 4.3 Codec2 output of the hts2a.raw processed in C ............................................................ 19 4.4 Codec2 output of the hts2a.raw processed in Verilog ....................................................... 20 A.1 FSM of codec2 encoder mode2400.v.......................................................................... 27 A.2 FSM of codec2 encoder one frame mode2400.v ........................................................ 28 A.3 FSM of CODEC2 encoder one frame mode2400.v (continued).................................. 29 A.4 FSM of analyse one frame.v ....................................................................................... 30 A.5 FSM of speech to uq lsps.v ........................................................................................ 31 A.6 FSM of speech to uq lsps.v (continued) ..................................................................... 32 A.7 FSM of encode lsp scalar.v ........................................................................................ 33 A.8 FSM of encode WoE.v ........................................................................................................ 34 vi Acknowledgements This thesis is a major milestone in my journey of research and therefore, I am feeling very happy to thank all who have supported me for reaching it. In the first place, I would like to express my heartfelt gratitude to my thesis advisor, Dr. Peter Jamieson for his supervision, advice, guidance from the very early stage of this research and for providing