FALL 2016 Meptec.Org Meptec.Org FALL 2016 NEW ELECTRONICS 12 MEPTEC REPORT MEPTEC REPORT 13 Jim Walker Gartner

2016 FALL

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 20, Number 3

2016 SEMICONDUCTOR PACKAGING ROADMAP SYMPOSIUM MEPTEC INITIATES COLLABORATION WITH HETEROGENEOUS INTEGRATION ROADMAP Monday, November 14, 2016 San2030 Jose, California 2040 page 1911 Customizable Silicone Materials+ for Advanced MEMS Performance page 24

MEPTEC MEMBER COMPANY PROFILE SMART MICROSYSTEMS LTD. was launched in 2011 and moved into a brand new facility in 2013, where SMART occupies over 15,000 square feet of space including 5,000 square feet of ISO 6 (class 1000) and ISO 5 (class 100) cleanrooms. page 14

-Corp. INSIDE THIS ISSUE

Could we be Tremendous cost ad- Die-attach materials Next-generation seeing the ‘end vantages, make plasma serve a critical role in devices will be of scaling’ within dicing very attractive facilitating semicon- brought to you by the next ten for small and thin ductor assembly and advanced packag- years? device manufacturers. ongoing performance. ing technologies 12 18 20 SPRING 201126 MEPTEC Report 3 Wear Sense Move it. it. it.

Innovative IC, System-in-Package, and MEMS packaging portfolio for today’s miniaturization, mobility, and IoT needs.

Wire Flip 2.5D WLP Fanout SiP Bond Chip & 3D

Package it. Visit: aseglobal.com The MEPTEC Report is a Publication of the 2016 Microelectronics Packaging & Test Engineering Council 315 Savannah River Dr., Summerville, SC 29485 Tel: (650) 714-1570 Email: [email protected] FALL A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 20, Number 3 Publisher MEPCOM LLC Editor Bette Cooper Art Director/Designer Gary Brown Sales Manager Gina Edwards 2016

FALL ON THE COVER A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 20, Number 3

2016 SEMICONDUCTOR PACKAGING ROADMAP SYMPOSIUM The MEPTEC 2016 Semiconductor Packaging Roadmap Symposium - MEPTEC Advisory Board MEPTEC INITIATES COLLABORATION WITH HETEROGENEOUS INTEGRATION ROADMAP MEPTEC Initiates Collaboration with Heterogeneous Integration Roadmap, will Monday, November 14, 2016 San2030 Jose, California 2040 page 19 be held on Monday, November 14, 2016 at the Holiday Inn - Silicon Valley Board Members Customizable Silicone Materials+ for Advanced MEMS Performance page 24 in San Jose, California. Sessions include Strategic Directions in Heteroge-

Ivor Barber Xilinx, Inc. MEPTEC MEMBER COMPANY PROFILE SMART MICROSYSTEMS LTD. was launched in neous Integration and Innovations in SiP and Integration, as well as a Panel 2011 and moved into a brand new facility in 2013, where SMART occupies over 15,000 square feet of space including 5,000 square feet of ISO 6 (class 1000) and ISO 5 (class 100) cleanrooms. Joel Camarda Semiops page 14 Discussion: Packaging Solutions to Meet Needs of the Heterogeneous In- -Corp. INSIDE THIS ISSUE

Could we be Tremendous cost ad- Die-attach materials Next-generation seeing the ‘end vantages, make plasma serve a critical role in devices will be tegration Roadmap. of scaling’ within dicing very attractive facilitating semicon- brought to you by the next ten for small and thin ductor assembly and advanced packag- Booz Allen Hamilton years? device manufacturers. ongoing performance. ing technologies Jeff Demmin 12 18 20 SPRING 201126 MEPTEC Report 3

Douglass Dixon Henkel Corporation

Exar Corporation ANALYSIS Nikhil Kelkar Steegen went on to suggest that while designers like heavy scaling, where devices shrink with a doubling the num- ANALYSIS – It is thought that within a few years, en- ber of transistors, over the past 10 years or so, the industry has not followed that Scaling – Continuity and Disruption: path. “Instead,” she said, “we have been confronted with dark periods – dark sili- Is the Semiconductor Industry Entering a New Phase con – where both voltage and transistor When it Comes to Scaling? scaling have not gone hand in hand. In fact, we are having to look at turning off certain cores in order to meet power den- Neil Tyler, Editor sity targets. TechDirect Consulting New Electronics Nick Leonardi gineers will have reached the physical limits of feature “So, from a technical perspective, how can we include the necessary fea- An Steegen, imec’s senior VP for Process tures to support future technology road- 12 Technology. Photo courtesy of imec maps?” IT IS THOUGHT THAT WITHIN A Solutions exist, including such novel few years, engineers will have reached widths, for example. approaches as stacking multiple front end the physical limits of feature sizes that Another option has been stack- layers, new materials and circuit level will enable them to build working CMOS ing multiple front end layers, although innovations. sizes that will enable them to build working CMOS systems. systems. In fact, Gordon Moore, the enabling more devices to be stacked in However, within a few years, it is creator of Moore’s Law, has admitted it the same space comes with more com- likely that we will have reached the lim- is likely that the road towards smaller plex fabrication and expense. its as to how small critical features can transistors has come to an end. These techniques have helped keep be made while still retaining working PPM Associates According to Moore: “Making the the gap between true Moore scaling and CMOS transistors. Phil Marcoux steps from one technology node to the the actual gains to an acceptable level, Traditionally scaling has been focused next is becoming increasingly difficult but that is becoming harder to achieve. on transistors. “In the future,” Steegens and more expensive. I don’t know how So is Moore’s Law is dead? contended, “there will be a need for more much longer it can continue.” “Traditional scaling is ‘morphing’ intense co-design of systems and tech- In fact, Gordon Moore, the creator of Moore’s Law, has ad- Could we be seeing the ‘end of scal- to allow for growing complexity and nology and a move towards specialised ing’ within the next ten years? several technology options are avail- high level functions or building blocks. At this year’s imec Technology able to engineers,” according to van den We will need to develop speciality tech- Forum, which awarded Moore its ‘Life- Hove. “We will evolve from FinFETS nologies for devices like mobiles, cam- time of Innovation Award’, the focus towards horizontal and even vertical eras and sensors.” was on how the semiconductor industry nanowires, which will bring us down to To that end research institutes like should respond to the end of traditional the 3nm generation, if not a few genera- imec are looking beyond traditional Dow Chemical Corp. scaling. tions more. To achieve this we will need CMOS transistors and at spinwave devic- Bhavesh Muni For more than 50 years, scaling has imec’s president Luc van der Hove, left, presents Gordon Moore with the Lifetime of effective lithography and I believe EUV es, for example, that exploit an electron’s mitted it is likely that the road towards smaller transistors addressed issues such as cost, area, Innovation Award. Photo courtesy of imec is the only effective lithography going spin. With these approaches, it may be power and performance. Until recently, forward.” possible to create devices that are both Moore’s Law held firm; new systems Roawen Chen said that pursuing Moore’s transition. We saw a switch to CMOS as According to An Steegen, imec’s more compact and energy efficient, as built from smaller chips delivered more Law was no longer unconditional. “We we looked to scale technology in terms senior VP for process technology: “Why which use fewer components. functionality and performance. no longer have to move to the latest of performance and power and we’ve would Moore’s Law be dead? While Going forward, scaling is expected Consensus was that scaling had node; that decision is more dependent on changed the properties of silicon, which there may not be the application drivers to be more of a system level concept, become far harder beyond the 28nm the company’s business model. The move has carried us on a few more years.” of the past, just look at the explosion in according to Steegens. The more abstrac- node and that chip manufacturing was to smaller nodes is slowing, but it is not According to Chen: “5G is going to data traffic enabled by the IoT. tion levels you cross, the higher the not only becoming more expensive, over. EUV and material innovations will be as disruptive as data was to the mobile “This will require CPU power and potential wins. has come to an end. but scaling was, itself, also becoming be key drivers.” phone. It offers an explosion of connec- storage capacity; even IoT devices will There needs to be a move away STATS ChipPAC increasingly difficult. As a result, there Luc van den Hove, imec’s president, tivity and will fuel growth going forward. need a degree of CPU capacity. So I from a ‘one size fits all’ concept and as Raj Pendse has been a focus on the use of new warned that, should semiconductor inno- In the first quarter of 2016, the demand think there will be more than enough applications are upgraded, so the focus is materials, of double and quadrupling vation slow significantly, the impact on for wearable devices has doubled. drivers for the more advanced nodes, likely to change. Some systems will ben- patterning and the development of new the electronics industry would be pro- Whether it’s high performance image especially in the server and mobile efit from lower power, others from more architectures, such as FinFETS. found. processing or real time decision making, domains. memory or higher I/O throughput. “The semiconductor industry is “We are living through an era of there are a lot of people out there looking “From the application driver perspec- Developing these technologies will mature and research and development profound digital disruption driven in for a different value proposition.” tive, Moore’s Law remains very much depend on it being done cost effectively spending is under pressure,” suggested no small part by the Internet of Things. Engineers have to work harder to get alive. I think the problem is the technolo- and will require new business models. Gary Patton, GlobalFoundries’ CTO and Scaling will have to continue if we want additional gains out of new nodes and gy itself. Are the expectations for power, The growth in specialised blocks could senior VP of worldwide R&D. “Scaling to deliver the enormous computing have developed ‘scaling boosters’, which performance and area now becoming result in a whole new ecosystem. ◆ has slowed dramatically as the cost of power the IoT calls for,” he said. “Tradi- take into account the requirements of unobtainable with current technology and design has gone up, but our customers tional growth drivers are no longer work- design units such as standard cell and does this mean there is not enough incen- This article first appeared in the June ASE (US) Inc. continue to scale at the leading edge.” ing. But if we as an industry take a step memory bit cells, as well as developing tive, from a design perspective, to move 28, 2016 issue of New Electronics and is Rich Rice NEIL TYLER Qualcomm’s VP of global operations back, we’ve witnessed many periods of different combinations of fin heights and to the next node? Is that the problem?” reproduced with the publisher’s permission. FALL 2016 meptec.org meptec.org FALL 2016 NEW ELECTRONICS 12 MEPTEC REPORT MEPTEC REPORT 13 Jim Walker Gartner

John Xie Intel Corporation PROFILE PROFILE – Located in Northeast Ohio, SMART Microsys- SMART MICROSYSTEMS Your Microelectronic Package Assembly Solution tems Ltd. provides microelectronic package assembly ser- for MEMS Sensors PROTOTYPE DEVELOPMENT SMART Microsystems Ltd. lectual property and proprietary Special Advisors 14 provides microelectronic pack- processes are protected through THE SMART ADVANTAGE age assembly services for MEMS SMART Microsystems client MEMS sensors are a platform technology that sensors. Its customers are pro- agreements, making SMART measure common types of modalities (eg., pres- ducers, manufacturers, and sup- a secure solution for industry, sure, chemical, temperature, motion, etc.) and pliers who need microelectronic academic, federal laboratory, or can be used in a variety of different application vices for MEMS sensors. Their customers are producers, manu- sub-assemblies for sensor prod- military R&D activity. areas. MEMS sensors are attractive because they ucts in high-value, low-volume The management team at deliver higher performance at lower cost plus market applications. These cus- SMART Microsystems is com- they are smaller, have less weight, and use less tomers are developing products mitted to helping their custom- power than conventional sensors. Additionally, – such as pressure, chemical, ers meet their goals by creating raw materials and components (eg., MEMS die, N-Able Group International and optical sensors – for a wide immediate and long term value. IC die, substrates, adhesives, etc.) have a lot of Ron Jones variety of markets. SMART Mi- With over 65 years of collective similarities, but the “new” advantages men- crosystems has an experienced experience in semiconductors, tioned above can only be realized with custom technical team, state-of-the-art microelectronics, and sensors, microelectronic process development in order facturers, and suppliers who need microelectronic sub-assemblies equipment, and brand new this team’s leadership has cre- ENVIRONMENTAL LIFE TESTING to ensure the performance requirements, the facilities that provide contract ated a comprehensive set of mi- manufacturability, and the cost targets for the services for prototype develop- croelectronic package assembly specific application. ment, environmental life testing, services for developing products SMART Microsystems has a significant com- and manufacturing. that leverage the advantages of petitive advantage by having key expertise Located in Northeast Ohio, MEMS sensor technology. This related to MEMS sensor product development SMART Microsystems has world- team has a proven track record and manufacturing. First, the team specializes class cleanroom facilities provid- in new product development in microelectronic package assembly process ing microelectronic packaging, where they have been respon- for sensor products in high-value, low-volume market applications. Gary Smith EDA development and test with customer-provided Mary Olsson assembly, and test capabilities. sible for product launches in designs. Second, microelectronic package as- SMART Microsystems is ISO 9001: a variety of industry sectors, sembly solutions, also known as System in Pack- 2008 certified, reflecting its com- including aerospace, automo- age (SiP) have more flexibility and can be more mitment to high quality and tive, biomedical, and industrial highly leveraged by the customer than System continuous improvement. Its controls. Their leadership has on Chip (SoC). Third, SiP solutions tend to have quality management system successfully built an organiza- shorter development cycles and therefore real- emphasizes service and support, tion that is focused on supreme ize a faster path to the market for the customer. and represents its commitment technical merit, commitment to Fourth, there are very few outsourced low vol- to continuously improving per- the highest quality, and ultimate ume microelectronic package assembly sup- formance for customers. Intel- customer satisfaction and value. MANUFACTURING SERVICES pliers in North America; furthermore, the ones that exist lack expertise in MEMS sensors. SMART MARKETS SMART MICROSYSTEMS LTD. Honorary Advisors

AEROSPACE AUTOMOTIVE DEFENSE DEVICE ENERGY ENVIRONMENTAL FOOD & INDUSTRIAL INSTRUMENTS MEDICAL NETWORKING & OPTICAL MEMBER COMPANY PROFILE MANUFACTURERS AGRICULTURE MANUFACTURING & CONTROLS COMMUNICATIONS NETWORKING & FOUNDRIES

14 MEPTEC REPORT FALL 2016 meptec.org meptec.org FALL 2016 MEPTEC REPORT 15 Seth Alavi Sunsil

Gary Catlin TECHNOLOGY – Plasma dicing is a chemical-etching TECHNOLOGY metal areas such as pads or bumps. Plasma Dicing for MEMS – 100% Plasma dicing employs a Bosch etch Rob Cole 90% process to dice vertically through the No More Chipping! 80% Die Spacing wafer. As a byproduct of the Bosch etch 70% 5µm process, the polymer deposition to con- Christopher Johnston 60% 10µm trol the etch profile may need to stripped 20µm after the silicon etching to prepare the Business Development Manager for Advanced Packaging 50% 30µm device for downstream processes. In Plasma-Therm 40% 40µm process that does not chip or crack the silicon. The 50µm most plasma dicing solutions, the poly- 30% 60µm mer stripping may be done in the same 70µm 20% chamber used for the silicon etch. The 10.0 Improvement Wafer Die Per 80µm 18 10% 90µm latest plasma dicing solution, by Plasma- PLASMA DICING TECHNOLOGY 0% 100µm Therm, dices the wafer on tape-frame 8% 2 2 2 2 2 2 2 2 2 2 employs the Bosch etch process to 7.5 employing a polymer-free, dicing process 9mm 4mm 1mm 6% 25mm 16mm control the vertical, anisotropic profile 0.25mm0.09mm0.04mm0.01mm that does not require additional polymer Skip Fehr 0.025mm to dice through the wafer. The etch 3x 4% stripping as shown in Figure 6. process delivers superior dicing qual- 5.0 9x 2% Die Size 0% gentle dicing process can be controlled to deliver extremely 2 2 2 2 2 ity versus blade or laser dicing, without 9mm 4mm 1mm the mechanical and thermal stress that 25mm 16mm impacts device reliability. Addition- 2.5

Normalized Fracture Strength (a.u.) Strength Fracture Normalized Figure 3. Yield Impact of Die Spacing Reduction. ally, plasma dicing eliminates the space

and shape constraints for more efficient 0 wafer layouts design, new devices and stops or seal rings) and straight lines or on yield and cost per die, including die Saw Laser Plasma packaging. The leading plasma dicing orthogonal. larger than 25mm². solutions, integrate easily into existing 120µm Thick Si Die As the more die per wafer are enabled dicing process flows, have compatibility Figure 1. Die Strength Comparison. the requirement for wafers starts is Dice Any Shape Elle Technology smooth sidewalls and has been proven to yield the highest Kerf with existing materials and do not require reduced. As less wafers starts are needed Dicing anything, anywhere, perfectly Figure 6. Polymer-free Dicing Process. Anna Gualtieri Width additional, expensive, sacrificial masking to make the same output of die, the without constraints is how powerful and lithography. equipment utilization is reduced and the the plasma dicing technology is. It is a Conclusion capacity is improved. When capacity is paradigm shift for industry. As device Plasma is capable of dicing the entire Superior Dicing Quality Die Die increased, less equipment is required. designers adopt the technology, more wafer at once, delivering superior die The quality results of a dicing process Kerf Figure 3 shows the yield impact of die efficient die layouts, die shapes and new strength, sidewall control, near perfect are measured by the size of the exterior Blade Seal Ring Seal Ring spacing reduction to die per wafer. Plas- devices will be enabled. Squares and accuracy and more die per wafer. Unlike damage (chipping) done to the edge Dicing Tape ma dicing can have a significant impact rectangles with 90 degree corners will be mechanical dicing methods, the plasma die strength from all dicing methods. device [1] and the die strength which is Street Width a thing of the past. The ability to make dicing process is faster as the wafer impacted by the internal damage (micro- multiple/combination products on the thickness is reduced and is not sensitive cracking) to the device. Die Spacing same wafer without sacrificing any die is to the die size. The capability of dicing ICINTEK The induced damage by the mechani- now a reality (Figure 4). with street widths below 5µm, without cal dicing process may cause premature the need for micro-cracking protection, Marc Papageorge Plasma Dicing Integration device failures through interaction with enables significant yield improvements, downstream packaging processes or The plasma dicing on tape (PDOT), which reduce cost per die and wafer- failures during reliability testing. Plasma Die Die Figure 5, process fits exactly where blade start requirements. These tremendous Seal Ring dicing is a chemical-etching process that Stealth Seal Ring or laser dicing is done and employs the cost advantages, make plasma dicing does not chip or crack the silicon. The Tape same wafer support media of dicing very attractive for small and thin device Dicing [2] ◆ gentle dicing process can be controlled Street Width frames and tapes . PDOT does not have manufacturers. a negative effect on the dicing tapes or to deliver extremely smooth sidewalls References and has been proven to yield the highest temperature sensitive materials on the Die Spacing Figure 4. Dicing Any Shape, Process 1. Lan Weisshaus, Dianne Shi, Udi Efrat, Wafer die strength from all dicing methods as Flexibility. devices and does not affect exposed Dicing (2000), electroiq.com CHRISTOPHER JOHNSTON shown in Figure 1. 2. Christopher Johnston, Plasma Dicing Methods For Thin Wafers, May-June 2016, Chip Scale More Die Per Wafer More More Review Die Die FAB Assembly / Packaging Current wafer layouts waste a signifi- Plasma Die Die Acknowledgements cate amount of wafer area which could The author gratefully acknowledges the team at be used to produce more devices. The Dicing Tape Wafer Wafer Wafer Plasma Die ON Semiconductor for permission to use the die spacing between die is greatly influence Preparation Thinning Mounting Dicing Picking photographs and die analysis data. Additionally, the author sincerely appreciates the contributions from by the limitations of the dicing process, Street Width = Kerf Width Seal Rings Eliminated Thierry Lazerand, Yannick Pilloux and Dr. David In Memoriam kerf width (Figure 2), process variation, Lishan at Plasma-Therm for the technical support PLASMA-THERM throughout the course of this work. damage area, damage controls (crack- Figure 2. Plasma Dicing Enables Die Spacing Reduction. Figure 5. PDOT Process Flow.

18 MEPTEC REPORT FALL 2016 meptec.org meptec.org FALL 2016 MEPTEC REPORT 19 Bance Hom

ASSEMBLY PACKAGING – Among the diverse types of adhesives, the process and the characteristics of the Die-attach Epoxies Enhance Product adhesive, the substrate might be heated during this placement process to partial Quality Beyond Manufacturing cure the die attach material. In the final step, the die/substrate assemblies will typically be subjected to a final curing Contributors Venkat Nandivada, Manager of Technical Support process using heat or UV treatment. For Master Bond Inc. heat-sensitive circuits, dual curing UV epoxies could be used, which offer a epoxies are particularly effective in enhancing product fast alignment and reduce the chances of substrate warping or shrinkage. Specialty dual curing UV epoxies can be fully 20 DIE-ATTACH ADHESIVES SERVE A cured at temperatures as low as 80 C, critical role in semiconductor assembly after an initial UV tack. and throughout the product lifecycle. Successful semiconductor assembly Beyond their ability to form a tight bond depends critically on the nature of the between die and various substrates, these die-attach adhesive itself. The adhesive adhesives help minimize the impact of must be able to form a tight, uniform reliability with their ability to provide high strength bonds Feldman Engineering Corp. mechanical and thermal stress, enhanc- bond between die and substrate. Still, Ira Feldman ing long-term product reliability. Among an adhesive’s cohesive strength is only available die-attach materials, epoxy one of many necessary characteristics. adhesives in particular offer a broad For example, an adhesive must exhibit range of characteristics designed to meet appropriate viscosity (resistance to flow) the unique requirements of even the most and thixotropic index (ability to hold Figure 2. One part epoxy system delivered pre-mixed in syringe, simplifies handling while specialized application. its shape) to ensure proper formation of eliminating potential problems such as mixing errors. Source: Master Bond Inc. In the semiconductor industry, the bonds. Adhesives must be able to flow while reducing effects of thermal cycling and mechanical stress. continued trend toward greater function- smoothly over irregularities in die and mately in long-term product reliability. which can erode IC reliability. Special- ality packed into smaller die translates substrate surfaces. Despite the precision Indeed, the thermal characteristics of ized epoxies designed for very humid into correspondingly greater challenges of the semiconductor fabrication process, the die-attach material directly impact environments resist absorption of mois- for efficient assembly and continued life- die can nonetheless exhibit micrometer- long-term reliability. In fact, manufactur- ture that can lead to fractures in the bond Plasma-Therm cycle reliability. During manufacturing, size peaks and valleys. Incomplete fillers can find die-attach adhesives with or weakening at the bonded interfaces Christopher Johnston these tiny die must be reliably assembled ing of valleys or flow around peaks can CTE characteristics designed to accom- and eventual delamination and failure. into integrated circuit (IC) packages, die- heat curing epoxies as well as two part precisely control the volume of material lead to voids that weaken the bond, even modate specific types of substrates. Temperature stability is important on-board systems, or complex stacked epoxies, have the ability to form a bond placed on the substrate, typically using resulting in delamination and eventual for any die-attach application but par- die-on-die assemblies. In the field, these that is mechanically robust and thermally vision control systems to ensure proper separation of the die from the substrate. Meeting Unique Requirements ticularly so for devices targeted for high packages, systems and assemblies must stable. Epoxies are among the strongest placement. As the die bonder places the Every die-attach application faces temperature applications. Adhesives are remain resistant to mechanical and ther- and most durable adhesives, offering die on the adhesive, it adds a slight and Enhancing Product Lifecycle common requirements for bond strength, available across a very wide temperature, mal conditions that can degrade perfor- mechanical strength, superior dimen- carefully controlled amount of pressure The adhesive’s ability to provide a heat dissipation and CTE matching -- supporting requirements ranging from mance and, ultimately, lead to product sional stability and excellent adhesion to to mate the die to the adhesive-treated uniform but very thin bond becomes and epoxy die-attach adhesives are well- cyrogenic applications to those operating failure. similar and dissimilar substrates. Manu- substrate (Figure 1). important throughout the product life- suited for meeting these requirements. at hundreds of degrees. VENKAT NANDIVADA Adhesives have emerged as the facturers can find highly specialized In this process, the application of cycle. Minimum thickness means fewer Beyond their fundamental characteristics Of course, manufacturers face a very preferred solution for meeting these epoxy adhesives designed to address the the adhesive is critical. Too much adhe- chances of air voids that can lead to for strength and thermal performance, wide range of requirements beyond ther- N-Able Group International demands with their ability to support unique demands of individual applica- sive, and the resulting fillet can flow up eventual bond failure. Minimum thick- however, these adhesives offer unique mal stability both during assembly and Ron Jones broadly diverse requirements for assem- tions for thermal and electrical conduc- the sides of the die and contaminate the ness is also important in ensuring maxi- advantages for meeting the more special- throughout the IC’s lifecycle. During bly, manufacturing, and product life- tivity, temperature range, outgassing, and circuits etched on the die. Too little and mum heat transfer from the die. ized requirements found in every applica- assembly, the ability to minimize curing cycle. Along with their ability to tightly many additional requirements. the die could lift from the substrate or Along with its responsibility for tion. temperature can be vital for achieving bind die to different materials, adhesives even crack. Depending on the nature of tightly bonding the die to the substrate, Different epoxy die-attach adhesives acceptable manufacturing yield. Simi- are able to meet complex combinations Facilitating Assembly die attach material typically serves as can provide electrically insulated bonds larly, the ability to meet very specific of requirements for electrical and thermal Die attach adhesives serve an inte- a primary path for die heat dissipation. or electrically conductive bonds such as requirements for bond strength, thermal MASTER BOND INC. conductivity as well as a host of other gral role in semiconductor assembly The efficiency of that heat-transfer path those required for exposed pad devices, conductivity, and avoiding CTE mis- physical characteristics including viscos- and manufacturing. After semiconduc- depends on the thickness of the die- for example. For applications targeted matches can spell the difference between ity, thermal stability, and more. tor wafer fabrication, individual die are attach layer, the thermal conductivity of for outer space, high vacuum or opti- early failure and extended lifetime of Among the diverse types of adhe- separated from the wafer by a precision the die-attach material, and the thermal cal applications, manufacturers can find semiconductor products. Indeed, each sives, epoxies are particularly effective in dicing saw or laser. High-speed die bond- resistance between the die-attach material epoxies with low outgassing characteris- application brings a unique combination Master Bond Inc. enhancing product reliability with their ers are used to lift each die and place it Figure 1. Die-attach adhesives are designed and the two surfaces it bonds. By provid- tics. of requirements, requiring an equally Venkat Nandivada ability to provide high strength bonds on a layer of die-attach material spread to provide tight bonds of uniform thick- ing an efficient path for heat dissipation, Most applications must deal with diverse complement of available die- while reducing effects of thermal cycling onto the substrate itself by specialized ness with minimal extruded fillet. the die-attach adhesive plays a central more mundane environmental factors attach materials that are well-matched to and mechanical stress. Many one part material dispensers. These dispensers Source: Master Bond Inc. role in thermal management -- and ulti- such as high temperature and humidity, those specific requirements.

20 MEPTEC REPORT FALL 2016 meptec.org meptec.org FALL 2016 MEPTEC REPORT 21 Raj Peddi Henkel Adhesive Electronics

Neil Tyler New Electronics 4 Member News 10 Industry Insights Column 26 Opinion Françoise von Trapp 3D InCites DEPARTMENTS 8 Coupling & Crosstalk Column 24 Henkel News Dr. Wei Yao Henkel Adhesive Electronics

MEPTEC Report Vol. 20, No. 3. Published quarterly by MEPCOM LLC, 315 Savannah River Dr., Summerville, SC 29485. Copyright 2016 by MEPCOM LLC. All rights reserved. Materials may not be reproduced in whole or in part without written permission. MEPTEC Report is sent without charge to members of MEPTEC. For non-members, yearly subscriptions are available for $75 in the United States, $80US in Canada and Mexico, and $95US elsewhere. For advertising rates and information contact Gina Edwards at 408-858-5493, Fax Toll Free 1-866-424-0130.  MEMBER NEWS

 UNISEM TO CON- ASE to Ramp Up Capacity Amid TINUE INVESTING IN FAST GROWING Surge in Demand MEMS MARKET ADVANCED SEMICONDUCTOR its integrated fan-out technol- profit rose 12 percent from Unisem recently shipped Engineering Inc. (ASE), the ogy to Apple Inc’s iPhones. NT$4.16 billion (US$130 their one billionth packaged world’s largest chip packager The company said it million) in the first quarter MEMS device and they and tester, yesterday said expects strong demand from to NT$4.68 billion. On an continue to invest capex equipment loading improved all segments and its system- annual basis, net profit surged in both MEMS assembly last quarter and that the in-a-package business – 28 percent from NT$3.65 bil- equipment and the devel- increase is expected to con- mainly for wearable devices lion. opment of additional fac- tinue this quarter. – is expected to start picking Last quarter’s figure is tory floor space for this However, to solve persis- up this quarter. slightly higher than NT$4.5 expanding market. With tent capacity constraint issues Factory utilization is fore- billion estimated by CIMB MEMS device revenues since last quarter, ASE plans cast to climb 5 percent this Securities Ltd. and NT$4.43 forecasted to grow from to add 5 percent more capac- quarter from last quarter to billion projected by Capital 11.9 Billion USD in 2015 ity this quarter, chief operat- about 85 percent for its pack- Investment Management to 20 Billion USD by 2021 ing officer Tien Wu told an aging equipment and to 80 Corp. (Yole), Unisem sees MEMS investors’ conference. percent for its testing equip- ASE said it and Silicon- as a strategic part of their ASE is expanding capaci- ment, the company said. ware Precision Industries Co. technology and growth ties for technologies including Gross margin for its core (SPIL) submitted an applica- plans moving forward. With leading-edge fan-out capacity, business is expected to rise to tion yesterday with the Fair over 9 years of experience given a drastic increase in 26 percent this quarter from Trade Commission to seek developing MEMS packag- demand, Wu said. 24.8 percent last quarter, ASE a regulatory approval for its ing solutions, Unisem esti- Fan-out packaging tech- projected. NT$128.7 billion takeover bid mates that their MEMS unit nology is becoming a focus Overall, Wu said revenue of SPIL. volumes will grow by over of chip packagers and equity would grow quarter-to-quar- The companies are also 50 percent over the next investors such as Taiwan ter growth in the second half preparing similar applications 12 months. Semiconductor Manufactur- of this year. in countries such as China www.unisemgroup.com ing Co. is expected to supply Last quarter, ASE’s net and the US, he said. ◆  UTAC RECEIVES ATO SUPPLIER OF THE YEAR AWARD Amkor Opens MEMS Packaging Line in China UTAC has been awarded DRIVEN BY THE INCREASE IN GLOBAL customers in Greater China and internationally.” the “ATO Supplier of the demand for sensors from the smartphone and The sensor content of smartphones, Internet Year 2015” for excellence automotive markets, Amkor Technology, Inc., of Things devices, and smart automobiles is in IC assembly and test a leading provider of semiconductor packaging increasing rapidly. According to Yole Dével- services by ON Semicon- and test services, has announced it is ramping oppement, this has spurred unit growth in the ductor at its inaugural Sup- up a new MEMS and sensor packaging line at MEMS market to an expected 13% compound plier Executive Conference its facility in Shanghai. This new, state-of-the- annual growth rate through 2021. Addition- in Phoenix, Arizona. UTAC art line will build on the expertise developed at ally, miniaturization and the need for advanced was one of four suppliers Amkor’s MEMS packaging line in the Philip- MEMS and sensors are driving the need for to be recognized by ON pines, which has produced more than 2.1 billion “sensor fusion,” which integrates more function- Semiconductor for out- units of MEMS and sensors since 2011. ality into a single package. standing performance and “Because the package influences device The new MEMS and sensor line in Shanghai supplier of the year honors. performance, MEMS and sensor development uses Amkor’s standard strip-based processes, UTAC has grown as a requires close collaboration between device and offers leading-edge test protocols to speed major supplier of assembly technologists and packaging engineers,” said time-to-market. and test services to ON John Donaghey, Amkor’s corporate vice presi- For additional information on Amkor’s Semiconductor since the dent, Mainstream Products business unit. “Our MEMS & Sensor Technology, please visit: relationship started more Shanghai expansion allows us to better serve www.amkor.com/go/mems. ◆ than a decade ago. The award recognizes UTAC’s performance in manufac- MEPTEC 2016 turing excellence, quality, high level of responsive- SEMICONDUCTOR PACKAGING 20302040 ness and customer service in 2015. ROADMAP SYMPOSIUM 11.14.2016 www.utacgroup.com  MONDAY, NOVEMBER 14, 2016 - SAN JOSE, CALIFORNIA

4 MEPTEC REPORT FALL 2016 meptec.org Cypress Semiconductor Names T.J. Rodgers’ CEO Successor

acquisition of Sunnyvale chipmaker Spansion at the ACCREDITED end of 2014 and the $550 mil- CERT # 3558* lion purchase of Broadcom’s Internet of Things operations this year. “Cypress is at an inflection point,” El-Khoury said in the announcement of his new role. “We’ve architected our company to become more valuable to our embedded- systems customers, signifi- CYPRESS SEMICONDUC- cantly expanding our portfo- TOR has named Hassane lio of high-value solutions in El-Khoury to succeed CEO growth markets such as auto- T.J. Rodgers at the San Jose motive, industrial, consumer company he founded more electronics and the IoT.” than 30 years ago. Cypress Chairman Ray Rodgers, 68, announced Bingham, who is becoming Surface mounted device with he was stepping aside at the executive chairman, said this delamination (red) along the entire length of several leads. This part 7,000-person company in of El-Khoury: “He has dem- would fail per J-STD-020 criteria. April, saying, “I have always onstrated strong leadership planned not to be spending and judgment over the past most of my time in the last nine years as a senior execu- decade of my career immers- tive at Cypress, heading up ed in the details of the opera- some of the company’s most ® tions.” innovative and successful SonoLab is Your Lab El-Khoury has been with businesses. He is an agent Cypress since 2007, work- of change who brings to this An ISO/IEC 17025:2005 Certifi ed Testing Lab* ing his way up from a job position an extensive knowl- SonoLab, a division of Sonoscan®, is the world’s largest as an application engineer edge of our target markets inspection service specializing in Acoustic Micro Imaging to becoming executive vice and a mindset focused on (AMI). Through SonoLab, you’ll have access to the superior president of its programmable customer value and profitable image quality and reliable data accuracy of Sonoscan ® systems division. He played growth.” ◆ C-SAM acoustic microscopes, plus the capabilities and careful analysis of the world’s leading AMI experts. key roles in the $1.4 billion With worldwide locations, SonoLab® Services unmatched capabilities, • Component Qualifi cation GE and SHINKO to Commercialize extensive experience to Industry Standards and the best equipment • Materials Characterization Advanced Electronics Packaging Solution available, SonoLab gives and Evaluation you the ability, fl exibility • High-Capacity Screening GE VENTURES AND SHINKO ELECTRIC INDUSTRIES CO., and capacity you need and Lot Reclamation LTD. have announced that SHINKO has been granted a patent license to meet all your AMI • Failure Analysis and and technology transfer of an advanced embedded packaging solution requirements. Constructional Analysis for power electronics called Power Overlay (POL).This patent license • Inspection and Audit Services and technology transfer deal, signed in early 2015, is a strategic col- • Custom Training laboration between GE and SHINKO in both technology and business development. To learn more visit sonoscan.com/sonolab Developed by GE Global Research as part of a major GE focus *For U.S. Locations Only in power electronics research over the last decade, POL has been licensed to SHINKO to industrialize the packaging platform to transition POL for manufacturing efforts to be utilized by GE and others. The platform enables higher efficiency and power density with reduced parasitics, and greatly impacting the power, telecommunica- 847-437-6400 • sonoscan.com tions and consumer electronics industries. Power modules designed with POL have proven to have power densities up to 50% higher and Elk Grove Village, IL • Silicon Valley, CA • Phoenix, AZ • England efficiency improved up to 10%. ◆ Philippines • Singapore • Shanghai • Taiwan meptec.org FALL 2016 MEPTEC REPORT 5  MEMBER NEWS

 INVENSAS AND Amkor Technology Receives “Device of the Year” JABIL COLLABORATE Award for SWIFT Semiconductor Package TO QUALIFY BVA TECHNOLOGY packaging expertise and Tessera Technologies, contributing to the commer- Inc. has announced that its cialization of game-changing wholly owned subsidiary technologies such as: Fan- Invensas Corporation and Out Wafer Level Packaging Jabil, one of the world’s (FOWLP), interposer-based leading design and manu- packages, 3D stacks and 3D facturing product solution System-in-Package (SiP). providers, have completed Amkor’s SWIFT ™ prod- the first phase of qualifica- uct was uniquely developed tion of Invensas Bond-Via- to deliver a high yielding, ™ ® Array (BVA ) interconnect high-performance package technology. with the thinnest profile in Invensas BVA technol- the industry. This package ogy provides the industry can deliver 2 µm line/space with a scalable package lithography with up to 4 lay- stacking platform that Jon Woodyard, Amkor’s VP of Technical Programs accepts ers of RDL and a very dense leverages existing manu- the 3D InCites award for “Device of the Year” from Francoise network of memory interface facturing infrastructure von Trapp and Stephen Hiebert, KLA-Tencor. vias from bottom package while delivering unmatched to the top package at a very tolerance to process AMKOR TECHNOLOGY, semiconductor package. cost competitive price. variations; this translates Inc. recently received the The awards were a result of For more information on into improved yield and 3D InCites “Device of the industry voting for individu- Amkor’s new SWIFT™ pack- cost efficiencies. The Year” award during SEMI- als, companies and products age visit: www.amkor.com/ technology can be used CON West for its’ SWIFT™ exhibiting excellence in 3D go/technology/swift. ◆ to provide cost effective 3D interconnect solutions for Package-on-Package A*STAR’s IME (PoP), System-in-Package Launches Chip-on- Promex accelerates time to market (SiP) and a range of other Wafer Consortium II packaging applications. from concept to prototype to production www.invensas.com to Advance Chip www.tessera.com Packaging Solutions

 SHINKO ELECTRIC A*STAR’S INSTITUTE OF INDUSTRIES CO., Microelectronics (IME) has LTD. TO CONSTRUCT partnered leading semicon- NEW FACILITIES ductor companies to develop cost-effective solutions in SHINKO has announced 2.5D and 3D wafer-level Mixed Assembly with SMT & Chip-wire that it will construct new integrated circuit (IC) packag- facilities at SHINKO’s Arai • Medical devices (implantable, wearable, medtech equipment) ing. The newly formed Chip- • Redundant continuous flow SMT assembly plant, in Niigata prefecture, on-Wafer Consortium II and lines >/= 01005 component placement to boost production capac- the Cost-Effective Interposer • RoHS compliant and leaded solder systems ity of ceramic electrostatic • IPC-A-610 Class 3 assembly Consortium will leverage chucks for semiconductor IME’s expertise in 3D and manufacturing equipment. IC Packaging 2.5D IC integration; bond- The total floor area of the ing technologies; as well as • Hermetic, plastic, air-cavity, COB new facility will be 6,000 • Multiple interconnect types the design and packaging of m2 and will contain a two- • Custom engineered flows (commercial, medical, military) semiconductor dies to develop story and a single-story • Fast-track prototypes to production volumes advanced chip packaging building. Construction was • Class 100 and Class 1000 clean rooms solutions. All these capabili- scheduled to begin in July ties will lead to cost savings of this year with an esti- and high-volume manufactur- mated completion date of The difference is in the engineering ing. March 2017. ISO 13485:2003 ● ISO 9001:2008 ● ITAR Registered For more information on www.shinko.com ◆ IME, please visit www.ime.a- www.promex-ind.com | 408-496-0222 star.edu.sg. ◆

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journey and not just the destination – just echo chamber for many by reinforc- COUPLING & one of the many reasons parents dislike ing their existing political views. Since hearing “Are we there yet?” from their friends typically share similar views and CROSSTALK children. values, there is definitely self-selection By Ira Feldman This change in routine, along with bias. The echo and bias are clearly rein- being “disconnected”, provided me with forcing people’s choice of candidate. If Electronic coupling is the transfer of ener- the perspective to directly observe the rut Facebook is your only “news” source, you gy from one circuit or medium to another. of being addicted to our digital “smart” are woefully under informed. Sometimes it is intentional and sometimes devices. Throughout our trip, I saw plenty Similar to group think and self-rein- not (crosstalk). I hope that this column, by of people paying more attention to their forcing opinions in our personal lives, the mixing technology and general observa- screens than the people or nature that same challenges can be present in the cor- tions, is thought-provoking and “couples” surrounded them. The remoteness of our porate world. One of the biggest dangers with your thinking. Most of the time I will destinations provided many places without is when employees are blinded to reality stick to technology but occasional cross- any connectivity which thankfully reduced by their organization’s own marketing and talk diversions may deliver a message this trend. However, it was all the more positioning. closer to home. pronounced – or at least glaringly obvious So, have you spotted some ruts that - when we returned to “civilization” for you would like to avoid? These can be dinner at the end of the day… eliminated through honest conscious Avoiding Ruts Within many cities we saw youths and change. However, one needs to be cau- adults feeding a brand new digital addic- tious of constant change which can be a and Nuts! tion: Pokémon Go. Since Pokémon Go is “rut” itself. I am reminded of the stories played outside in public it is hard to tell if of my spouse’s “fiddle-footed” Canadian  WE JUST COMPLETED A FANTASTIC the magnitude of the addiction is greater ancestors who were prone to relocating trans-Canadian family road trip! The or simply more visible. It was astonish- themselves. They moved multiple times highlights included Glacier National Park ing to see the number of people so deeply at the drop of a hat sometimes leaving in Montana along with Banff & Jasper engaged to the point of being oblivious in immediate family members behind. I National Parks in the Canadian Rocky something just released a month ago. like to think that their movements were Mountains. The trip provided the right Another change was in our news to improve their situation and not simply amount of “disconnecting” both physi- sources. During this trip, our news came change for change’s sake. cally, (or should I say wirelessly?), and from what our friends shared on Facebook Sometimes business change is driven mentally. During this time I observed and the occasional access to local media. by the lack of focus or the desire to avoid a number of ruts of the repetitious, not Did you know that Canada has an Olym- accountability. And some leaders, under the sexual or pothole, variety, and was pic team? And there are many talented pressure to produce results, fail to allow reminded how easy it is to become “stuck athletes that we Americans have never changes to “settle in” and take root, pre- in a rut”. Understanding how to identify heard of? We saw many more heats on venting the desired improvement. Organi- ruts can help make meaningful personal Canadian television with athletes perform- zations that have constant change also run and professional improvements. ing at their peak but unlikely to end up on the risk of employees dismissing the latest Coaches and consultants provide a the podium than we normally do. change as the “initiative du jour”. Just fresh set of eyes to look at processes and Even the tone of the Presidential like the proper perspective and experi- procedures at home or work. Sometimes election coverage shifted somewhat as ence to identify ruts, a fresh set of eyes staff is consumed with activities “just we moved away from the “deep blue” can set the pace for successful change. because” or enforcing rules since “that Democratic bubble of Silicon Valley to This is what I learned on our road is how we’ve always done something.” Republican leaning Montana. The Cana- trip! Even though we did not see any It is the fresh or outsider perspective that dian press is “having a field day” mixed huckleberry-addicted Canadian Moose allows one to see a rut for what it is really with shocked disbelief as they report on rutting, we hope that our teenagers gained is – repetition that is not productive or the circus this election has become. This a greater appreciation for the grandeur of useful. These “ruts” creep into everything reminded us of the danger of assuming nature during their summer break. including personal habits, government that everyone shares the same values For more of my thoughts, please procedures, and business processes. And and thought processes as we do. see my blog http://hightechbizdev.com. business process ruts occur at all levels At the other extreme, there is a “herd As always, I look forward to hearing from the simplest transaction to corporate mentality” occurring on Facebook. Politi- your comments directly. Please contact planning and governance. Do you really cal items posted on Facebook are having me to discuss your thoughts or if I can be need to collect and analyze that data every zero impact on changing the opinions of of any assistance. ◆ month if no one will act upon it? others who have decided on a candidate I find traveling with my family forces let alone those of undecided voters. In IRA FELDMAN is the Principal Consultant of Feldman Engineering Corp. which guides high me to step out of my daily routines. Not fact, several friends have declared a mora- technology products and services from concept only are the logistics of a family road trip torium on posting political items on their to high volume manufacturing. He engages different than my typical business trip - timelines and others have actively de- on a wide range of projects including techni- especially when traveling by car versus friended or blocked those with opposing cal marketing, product-generation processes, air - the style of travel is different since views. supply-chain management, and business devel- our priorities are different. It is about the Facebook is currently serving as an opment. ([email protected])

8 MEPTEC REPORT FALL 2016 meptec.org

COLUMN

duced in the supply chain. conflict free product. The supply chain (IC INDUSTRY China has also introduced conflict companies, foundries and OSATs ) react mineral regulations that are similar but to these squeaky wheels and do whatever INSIGHTS different from the US and EU. China is necessary to provide conflict free prod- By Ron Jones adopted a draft CM policy at an OECD uct. Some smaller customers or lower vol- meeting on December 2, 2015. The China ume parts are receiving lower priority on policy follows the OECD guidelines, but conflict free deliveries. Granted, things are Conflict Minerals compliance is voluntary. The initial focus improving with time, but some companies is on 3TG and applies to all Chinese com- have had to make changes to their supply Year Three – The panies that extract or use minerals and chain in order to get compliant product. their related products. It is hoped that this It is of little consequence to a customer Squeaky Wheels effort will help identify country of origin whether their supplier files as conflict free for the output of many smelters. with the SEC as it is an annual snapshot  SEMICONDUCTOR AND OTHER It is generally acknowledged that in time. What is important is whether the companies that use tin, tantalum, tungsten Apple is enforcing “conflict free only” IC’s that are being shipped day in and day or gold (also known as 3TG or Conflict product deliveries on their suppliers. In out are conflict free. ◆ Minerals) in their products continue to face the table below, we see 15 companies that challenges in supplying products that can are delivering 27 different chips for the RON JONES is CEO of N-Able Group be shown to be conflict free. For a product iPhone 6. Only two IC suppliers (TI and International; a semiconductor focused to be conflict free, it must demonstrate that Skyworks) have declared that any, or in consulting and recruiting company. each component or part in the bill of mate- this case all, of their products are conflict N-Able Group provides Conflict Mineral rial is conflict free. Proof must reach down free in their CY 2015 SEC filing. Compliance support services to compa- to the level of where the mineral or ele- This points up what we have been say- nies throughout the semiconductor supply ment was extracted from the earth. ing for some time. The “squeaky wheels” chain. Visit www.n-ablegroup.com or The challenge exhibits itself in two are customers with high volume/high email [email protected] for arenas: governmental reporting at the profile parts that insist on receiving only more information. company level and product level compliance for an individual physical item. We have now completed the third year Company iPhone 6 ICs 2015 SEC CM filing of public company reporting to the SEC on Conflict Minerals. The most recent was Skyworks 2 chips All IC products declared CF for the compliance year from January 1, Avago 2 chips No products declared CF to December 31, 2015 and was due to be filed on or before May 31, 2016. Gener- RF Micro Devices 2 chips No products declared CF ally the quality and completeness of indi- TriQuint 1 chip No products declared CF vidual company filings has improved with time. The number of public companies Qualcomm 5 chips No products declared CF filing a Form SD has stayed consistent at around 1200. The number of companies Bosch Sensotec 2 chips No products declared CF that have declared all or some of their InvenSense 1 chip No products declared CF products to be conflict free has grown from 4 to 12, but is still small compared Apple 3 chips to the total number of filers. Though only Micron 1 chip No products declared CF public companies must file with the SEC, private companies must report compliance NXP 2 chips No products declared CF information up the supply chain for public Texas Instruments 1 chip All IC products declared CF companies to be able to accurately report their product status. The semiconductor SK Hynix 1 chip No products declared CF SIC code (3674) accounts for 12% of SEC Broadcom 1 chip No products declared CF conflict mineral filers. There have not been any substantive Murata 2 chips No products declared CF changes to the US conflict mineral regulations; though there has been some laxation AKM 1 chip No products declared CF of the reporting requirements with regards TOTAL 27 chips to whether a company must declare non- compliant products to be “not conflict free.” The European Union has recently TSMC Foundry No reason to believe, no IPSA issued guidance on their conflict minerals program. It is similar to the US in the ASE OSAT All IC products materials covered, 3TG, but is worldwide SPIL OSAT All IC products in scope as to where conflict can be intro-

10 MEPTEC REPORT FALL 2016 meptec.org 2016 SEMICONDUCTOR PACKAGING ROADMAP SYMPOSIUM 20302040 11.14.2016

MEPTEC INITIATES COLLABORATION WITH HETEROGENEOUS INTEGRATION ROADMAP MONDAY, NOVEMBER 14, 2016 | SAN JOSE, CALIFORNIA SYMPOSIUM 8:00AM - 5:00PM | EXHIBITS 9:30AM - 6:30PM | RECEPTION 5:00PM - 6:30PM

n this post ITRS era, there is great need for the industry to col- MORNING SESSION: laborate in charting a direction into the future. In 2015, the Strategic Directions in Heterogeneous Integration ISIA announced their decision to bring ITRS to a close, with the The morning session will address the strategic directions in 2015 edition being the final edition. The IEEE CPMT Society took heterogeneous integration that address the market inflection the initiative to establish a technology roadmap focused on het- points and technology fault lines. What will be the crucial roles erogeneous integration, to be modeled after the ITRS in purpose, for integrated phonics for data to the cloud, and for sensing? structure, and governance. This initiative quickly found resonance What technologies will be developed and implemented for the with SEMI, and the IEEE Electron Devices Society (EDS) joined self driven cars be introduced into our cities and byways? How the effort, resulting in the launch of the Heterogeneous Integra- embedded sensing will enable the transition from IoT to IoE tion Roadmap (HIR). MEPTEC has moved to participate in this around the world. roadmap collaboration. AFTERNOON SESSION: MORNING KEYNOTE SPEAKER Innovations in SiP and Integration This session will address the major developments in heteroge- Wilmer R. Bottoms, Ph.D. neous components – power devices, analog, MEMS sensors, Chairman, Third Millennium Test Solutions photonics, and in SiP integration – fan out, 2.5D, embedded, Co-chair, Heterogeneous Integration and co-design technologies. How will the momentum of these Roadmap (HIR) technology developments move forward to address road blocks moving ahead? What research areas and ecosystem collaboration will be needed for continued progress? These and more AFTERNOON KEYNOTE SPEAKER questions will be addressed. William (Bill) Chen, Ph.D. ASE Fellow and Senior Technical Advisor, PREMIER SPONSOR GOLD SPONSOR GOLD SPONSOR ASE Group Co-chair, Heterogeneous Integration Roadmap (HIR)

Sponsorship Opportunities and Exhibit Spaces Available

Scaling – Continuity and Disruption: Is the Semiconductor Industry Entering a New Phase When it Comes to Scaling?

Neil Tyler, Editor New Electronics

IT IS THOUGHT THAT WITHIN A few years, engineers will have reached the physical limits of feature sizes that will enable them to build working CMOS systems. In fact, Gordon Moore, the creator of Moore’s Law, has admitted it is likely that the road towards smaller transistors has come to an end. According to Moore: “Making the steps from one technology node to the next is becoming increasingly difficult and more expensive. I don’t know how much longer it can continue.” Could we be seeing the ‘end of scaling’ within the next ten years? At this year’s imec Technology Forum, which awarded Moore its ‘Lifetime of Inno- vation Award’, the focus was on how the semiconductor industry should respond to imec’s president Luc van der Hove, left, presents Gordon Moore with the Lifetime of the end of traditional scaling. Innovation Award. Photo courtesy of imec For more than 50 years, scaling has addressed issues such as cost, area, power longer have to move to the latest node; that and will fuel growth going forward. In the and performance. Until recently, Moore’s decision is more dependent on the com- first quarter of 2016, the demand for wear- Law held firm; new systems built from pany’s business model. The move to smaller able devices has doubled. Whether it’s high smaller chips delivered more functionality nodes is slowing, but it is not over. EUV and performance image processing or real time and performance. material innovations will be key drivers.” decision making, there are a lot of people Consensus was that scaling had become Luc van den Hove, imec’s president, out there looking for a different value propo- far harder beyond the 28nm node and that warned that, should semiconductor innova- sition.” chip manufacturing was not only becoming tion slow significantly, the impact on the Engineers have to work harder to get more expensive, but scaling was, itself, also electronics industry would be profound. additional gains out of new nodes and have becoming increasingly difficult. As a result, “We are living through an era of pro- developed ‘scaling boosters’, which take there has been a focus on the use of new found digital disruption driven in no small into account the requirements of design units materials, of double and quadrupling pat- part by the Internet of Things. Scaling will such as standard cell and memory bit cells, terning and the development of new archi- have to continue if we want to deliver the as well as developing different combinations tectures, such as FinFETS. enormous computing power the IoT calls of fin heights and widths, for example. “The semiconductor industry is mature for,” he said. “Traditional growth drivers are Another option has been stacking multi- and research and development spending is no longer working. But if we as an industry ple front end layers, although enabling more under pressure,” suggested Gary Patton, take a step back, we’ve witnessed many devices to be stacked in the same space GlobalFoundries’ CTO and senior VP of periods of transition. We saw a switch to comes with more complex fabrication and worldwide R&D. “Scaling has slowed dra- CMOS as we looked to scale technology in expense. matically as the cost of design has gone up, terms of performance and power and we’ve These techniques have helped keep but our customers continue to scale at the changed the properties of silicon, which has the gap between true Moore scaling and leading edge.” carried us on a few more years.” the actual gains to an acceptable level, but Qualcomm’s VP of global operations According to Chen: “5G is going to that is becoming harder to achieve. So is Roawen Chen said that pursuing Moore’s be as disruptive as data was to the mobile Moore’s Law is dead? Law was no longer unconditional. “We no phone. It offers an explosion of connectivity “Traditional scaling is ‘morphing’ to

12 MEPTEC REPORT FALL 2016 meptec.org allow for growing complexity and several the problem?” need to develop speciality technologies for technology options are available to engi- Steegen went on to suggest that while devices like mobiles, cameras and sensors.” neers,” according to van den Hove. “We designers like heavy scaling, where devices To that end research institutes like imec will evolve from FinFETS towards horizon- shrink with a doubling the number of are looking beyond traditional CMOS tal and even vertical nanowires, which will transistors, over the past 10 years or so, transistors and at spinwave devices, for bring us down to the 3nm generation, if not the industry has not followed that path. example, that exploit an electron’s spin. a few generations more. To achieve this we “Instead,” she said, “we have been confront- With these approaches, it may be possible to will need effective lithography and I believe ed with dark periods – dark silicon – where create devices that are both more compact EUV is the only effective lithography going both voltage and transistor scaling have not and energy efficient, as which use fewer forward.” gone hand in hand. In fact, we are having to components. According to An Steegen, imec’s senior look at turning off certain cores in order to Going forward, scaling is expected to be VP for process technology: “Why would meet power density targets. more of a system level concept, according Moore’s Law be dead? While there may not “So, from a technical perspective, how to Steegens. The more abstraction levels you be the application drivers of the past, just can we include the necessary features to cross, the higher the potential wins. look at the explosion in data traffic enabled support future technology roadmaps?” There needs to be a move away from by the IoT. Solutions exist, including such novel a ‘one size fits all’ concept and as applica- “This will require CPU power and stor- approaches as stacking multiple front end tions are upgraded, so the focus is likely age capacity; even IoT devices will need layers, new materials and circuit level inno- to change. Some systems will benefit from a degree of CPU capacity. So I think there vations. lower power, others from more memory or will be more than enough drivers for the However, within a few years, it is likely higher I/O throughput. more advanced nodes, especially in the that we will have reached the limits as to Developing these technologies will server and mobile domains. how small critical features can be made depend on it being done cost effectively “From the application driver perspective, while still retaining working CMOS transis- and will require new business models. The Moore’s Law remains very much alive. I tors. growth in specialised blocks could result in think the problem is the technology itself. Traditionally scaling has been focused a whole new ecosystem. ◆ Are the expectations for power, performance on transistors. “In the future,” Steegens and area now becoming unobtainable with contended, “there will be a need for more This article first appeared in the June current technology and does this mean there intense co-design of systems and technol- 28, 2016 issue of New Electronics and is is not enough incentive, from a design per- ogy and a move towards specialised high reproduced with the publisher’s permission. spective, to move to the next node? Is that level functions or building blocks. We will

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SMART MICROSYSTEMS Your Microelectronic Package Assembly Solution for MEMS Sensors PROTOTYPE DEVELOPMENT SMART Microsystems Ltd. and represents its commitment provides microelectronic pack- to continuously improving per- age assembly services for MEMS formance for customers. sensors. Its customers are pro- The management team at ducers, manufacturers, and sup- SMART Microsystems is com- pliers who need microelectronic mitted to helping their custom- sub-assemblies for sensor prod- ers meet their goals by creating ucts in high-value, low-volume immediate and long term value. market applications. These cus- With over 65 years of collective tomers are developing products experience in semiconductors, – such as pressure, chemical, microelectronics, and sensors, and optical sensors – for a wide this team’s leadership has cre- variety of markets. SMART Mi- ated a comprehensive set of microsystems has an experienced croelectronic package assembly technical team, state-of-the-art services for developing products ENVIRONMENTAL LIFE TESTING equipment, and brand new that leverage the advantages of facilities that provide contract MEMS sensor technology. This services for prototype develop- team has a proven track record ment, environmental life testing, in new product development and manufacturing. where they have been respon- Located in Northeast Ohio, sible for product launches in SMART Microsystems has world- a variety of industry sectors, class cleanroom facilities provid- including aerospace, automo- ing microelectronic packaging, tive, defense, biomedical, and assembly, and test capabilities. industrial controls. Their lead- SMART Microsystems is ISO 9001: ership has successfully built an 2008 certified, reflecting its com- organization that is focused on mitment to high quality and supreme technical merit, com- continuous improvement. Its mitment to the highest quality, quality management system and ultimate customer satisfac- emphasizes service and support, tion and value. MANUFACTURING SERVICES SMART MARKETS

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14 MEPTEC REPORT FALL 2016 meptec.org THE SMART ADVANTAGE MEMS sensors are a platform technology that measure common types of modalities (eg., pressure, chemical, temperature, motion, etc.) and can be used in a variety of different application areas. MEMS sensors are attractive because they deliver higher performance at lower cost plus they are smaller, have less weight, and use less power than conventional sensors. Additionally, raw materials and components (eg., MEMS die, IC die, substrates, adhesives, etc.) have a lot of similarities, but the “new” advantages men- tioned above can only be realized with custom microelectronic process development in order to ensure the performance requirements, the manufacturability, and the cost targets for the specific application. SMART Microsystems has a significant competitive advantage by having key expertise related to MEMS sensor product development and manufacturing. First, the team specializes in microelectronic package assembly process development and test with customer-provided designs. Second, microelectronic package assembly solutions, also known as System in Pack- age (SiP) have more flexibility and can be more highly leveraged by the customer than System on Chip (SoC). Third, SiP solutions tend to have shorter development cycles and therefore realize a faster path to the market for the customer. Fourth, there are very few outsourced low volume microelectronic package assembly suppliers in North America; furthermore, the ones that exist lack expertise in MEMS sensors.

FOOD & INDUSTRIAL INSTRUMENTS MEDICAL NETWORKING & OPTICAL AGRICULTURE MANUFACTURING & CONTROLS COMMUNICATIONS NETWORKING meptec.org FALL 2016 MEPTEC REPORT 15 PROFILE

SMART MICROELECTRONIC PACKAGING CAPABILITIES

SMART MICROSYSTEMS creates turn-key solutions for microelec- Microelectronic package assembly is a key part of the manufactur- tronic package assembly challenges to move its clients MEMS sensor ing process for MEMS sensor products. SMART’s core capabilities technology from development to production. With an engineering and expertise support development, testing, and manufacturing of team experienced in manufacturing and state-of-the-art facilities, designs provided by their customers. Package assembly solutions SMART Microsystems accelerates the transition of new MEMS sensor offer more flexibility, faster lead times, and lower cost for niche ap- products to the market. plications.

■ TEST AND INSPECTION capabilities at SMART Microsystems play an important role in the development of processes and testing of micro- system package assemblies for our customers. By using Environmental Life Testing and Test and Inspection in conjunction with a Test Early-Test Often approach in the product development cycle, weaknesses in the design are found early, before too much value is added to the part.

■ DICING is the process in which semiconductor wafers such as MEMS and IC’s are singulated into individual die before package assembly. This is an automated process to ensure precision and accuracy. SMART Micro- systems has experience cutting a wide range of materials for customers. These include silicon, glass, alumina, sapphire, and ceramic. Additionally, we offer wafer inspection and die sorting services if required.

■ DIE ATTACH is a critical step in the packaging of microsystems and MEMS sensors that can impact other packaging and assembly processes. The capabilities consist of epoxy die attach, flip chip, sintering, eutectic attach, multi-chip module, and solder reflow. The die attach processes and expertise at SMART Microsystems support the development, testing, and manufacturing of sub-assemblies designed by our customers.

■ WIRE BONDING is a key manufacturing process for microelectronics and MEMS sensor products. SMART Microsystems provides extensive wire bonding capabilities: fine gauge wire gold ball bonding, fine gauge wire/ribbon gold wedge bonding, fine gauge wire/ribbon aluminum wedge bonding, and heavy gauge wire/ribbon aluminum wedge bonding. Wire bonding processes are flexible and robust, allowing our customers to quickly realize a microelectronic package assembly solution.

■ ENCAPSULATION of microsystems is a sophisticated process requiring understanding of the encapsulant materials and their interac- tions with die surfaces, package substrates and their related processes, as well as the physical environment in which the packaged device will be exposed. The SMART Microsystems encapsulation capabilities are adhesive dispense-dam and fill, glob top, potting, and underfill-hermetic and non-hermetic lid sealing, and parylene coating.

■ ENVIRONMENTAL LIFE TESTING at SMART Microsystems identifies reliability issues early in your product development. Our contract testing laboratory works directly with you to provide testing solutions that help ensure product quality and reliability. As part of your turn-key product solution, reliability study, or on an as-needed basis for overflow/ bandwidth, SMART Microsystems can solve your issues before they become a problem in the field.

16 MEPTEC REPORT FALL 2016 meptec.org SMART ENGINEERING WITH THE END IN MIND

SMART Microsystems uses two ment addresses the flaws of the and the overall cycle of iterative the process and the process en- strategies – Test Early Test traditional product develop- changes is shortened. gineer to consider the design. Often and Concurrent Engi- ment cycle (PDC). This strategy Another strategy to address When the design and process neering – in order to success- shortens the overall PDC by em- the pitfalls of the traditional development is conducted fully develop new products that ploying targeted testing early in PDC is the Concurrent Engi- concurrently, and early test- meet market demands. These the development process. The neering approach to product ing is performed, learning is product development strate- Test Early Test Often approach development. Concurrent En- quicker and the design cycles gies create quicker learning and uncovers weaknesses in designs gineering promotes manufac- become much shorter. Imple- shorter design cycles. By imple- by testing fundamental design turable design and reduces mentation of Concurrent En- menting these two strategies, and process assumptions be- overall product development gineering hand-in-hand with product development teams fore too much value is added cost by creating synergies be- the Test Early Test Often strategy can lower overall development to the part. In this strategy, re- tween design and process adds real, measurable value. time and cost for the MEMS sen- quirements for new science are engineering groups. By begin- These combined engineering sor market. highlighted, potential issues are ning with the end in mind, strategies significantly lower The Test Early Test Often addressed before they become this strategy encourages the overall development time and approach to product develop- integrated into the process, design engineer to consider cost.

SMART Microsystems Ltd. Telephone: 440-366-4203 141 Innovation Drive [email protected] Elyria, Ohio 44035 www.smartmicrosystems.com meptec.org FALL 2016 MEPTEC REPORT 17 TECHNOLOGY

Plasma Dicing for MEMS – No More Chipping! Christopher Johnston Business Development Manager for Advanced Packaging Plasma-Therm

10.0

PLASMA DICING TECHNOLOGY employs the Bosch etch process to 7.5 control the vertical, anisotropic profile to dice through the wafer. The etch 3x process delivers superior dicing qual- 5.0 9x ity versus blade or laser dicing, without the mechanical and thermal stress that impacts device reliability. Addition- 2.5 ally, plasma dicing eliminates the space (a.u.) Strength Fracture Normalized and shape constraints for more efficient 0 wafer layouts design, new devices and Saw Laser Plasma packaging. The leading plasma dicing solutions, integrate easily into existing 120µm Thick Si Die dicing process flows, have compatibility Figure 1. Die Strength Comparison. with existing materials and do not require Kerf Width additional, expensive, sacrificial masking and lithography. Superior Dicing Quality Die Die The quality results of a dicing process Kerf are measured by the size of the exterior Blade Seal Ring Seal Ring damage (chipping) done to the edge Dicing Tape device [1] and the die strength which is Street Width impacted by the internal damage (micro- cracking) to the device. Die Spacing The induced damage by the mechanical dicing process may cause premature device failures through interaction with downstream packaging processes or failures during reliability testing. Plasma Die Die Seal Ring dicing is a chemical-etching process that Stealth Seal Ring does not chip or crack the silicon. The Dicing Tape gentle dicing process can be controlled Street Width to deliver extremely smooth sidewalls and has been proven to yield the highest Die Spacing die strength from all dicing methods as shown in Figure 1.

More Die Per Wafer More More Die Die Current wafer layouts waste a signifi- Die Die cate amount of wafer area which could Plasma be used to produce more devices. The Dicing Tape spacing between die is greatly influence by the limitations of the dicing process, Street Width = Kerf Width kerf width (Figure 2), process variation, Seal Rings Eliminated damage area, damage controls (crack- Figure 2. Plasma Dicing Enables Die Spacing Reduction.

18 MEPTEC REPORT FALL 2016 meptec.org metal areas such as pads or bumps. 100% Plasma dicing employs a Bosch etch 90% process to dice vertically through the 80% Die Spacing wafer. As a byproduct of the Bosch etch 70% 5µm process, the polymer deposition to con- 60% 10µm trol the etch profile may need to stripped 20µm after the silicon etching to prepare the 50% 30µm device for downstream processes. In 40% 40µm 50µm most plasma dicing solutions, the poly- 30% 60µm mer stripping may be done in the same 70µm 20% chamber used for the silicon etch. The Die Per Wafer Improvement Wafer Die Per 80µm 10% 90µm latest plasma dicing solution, by Plasma- 0% 100µm Therm, dices the wafer on tape-frame 8% 2 2 2 2 2 2 2 2 2 2 employing a polymer-free, dicing process 9mm 4mm 1mm 6% 25mm 16mm 0.25mm0.09mm0.04mm0.01mm that does not require additional polymer 0.025mm 4% stripping as shown in Figure 6. 2% Die Size 0% 2 2 2 2 2

9mm 4mm 1mm 25mm 16mm

Figure 3. Yield Impact of Die Spacing Reduction. stops or seal rings) and straight lines or on yield and cost per die, including die orthogonal. larger than 25mm². As the more die per wafer are enabled the requirement for wafers starts is Dice Any Shape reduced. As less wafers starts are needed Dicing anything, anywhere, perfectly Figure 6. Polymer-free Dicing Process. to make the same output of die, the without constraints is how powerful equipment utilization is reduced and the the plasma dicing technology is. It is a Conclusion capacity is improved. When capacity is paradigm shift for industry. As device Plasma is capable of dicing the entire increased, less equipment is required. designers adopt the technology, more wafer at once, delivering superior die Figure 3 shows the yield impact of die efficient die layouts, die shapes and new strength, sidewall control, near perfect spacing reduction to die per wafer. Plas- devices will be enabled. Squares and accuracy and more die per wafer. Unlike ma dicing can have a significant impact rectangles with 90 degree corners will be mechanical dicing methods, the plasma a thing of the past. The ability to make dicing process is faster as the wafer multiple/combination products on the thickness is reduced and is not sensitive same wafer without sacrificing any die is to the die size. The capability of dicing now a reality (Figure 4). with street widths below 5µm, without the need for micro-cracking protection, Plasma Dicing Integration enables significant yield improvements, The plasma dicing on tape (PDOT), which reduce cost per die and wafer- Figure 5, process fits exactly where blade start requirements. These tremendous or laser dicing is done and employs the cost advantages, make plasma dicing same wafer support media of dicing very attractive for small and thin device frames and tapes [2]. PDOT does not have manufacturers. ◆ a negative effect on the dicing tapes or References temperature sensitive materials on the Figure 4. Dicing Any Shape, Process 1. Lan Weisshaus, Dianne Shi, Udi Efrat, Wafer Flexibility. devices and does not affect exposed Dicing (2000), electroiq.com 2. Christopher Johnston, Plasma Dicing Methods For Thin Wafers, May-June 2016, Chip Scale Review FAB Assembly / Packaging Acknowledgements The author gratefully acknowledges the team at Wafer Wafer Wafer Plasma Die ON Semiconductor for permission to use the die Preparation Thinning Mounting Dicing Picking photographs and die analysis data. Additionally, the author sincerely appreciates the contributions from Thierry Lazerand, Yannick Pilloux and Dr. David Lishan at Plasma-Therm for the technical support Figure 5. PDOT Process Flow. throughout the course of this work. meptec.org FALL 2016 MEPTEC REPORT 19 ASSEMBLY

Die-attach Epoxies Enhance Product Quality Beyond Manufacturing

Venkat Nandivada, Manager of Technical Support Master Bond Inc.

DIE-ATTACH ADHESIVES SERVE A critical role in semiconductor assembly and throughout the product lifecycle. Beyond their ability to form a tight bond between die and various substrates, these adhesives help minimize the impact of mechanical and thermal stress, enhancing long-term product reliability. Among available die-attach materials, epoxy adhesives in particular offer a broad range of characteristics designed to meet the unique requirements of even the most specialized application. In the semiconductor industry, the continued trend toward greater functionality packed into smaller die translates into correspondingly greater challenges for efficient assembly and continued lifecycle reliability. During manufacturing, these tiny die must be reliably assembled into integrated circuit (IC) packages, die- heat curing epoxies as well as two part precisely control the volume of material on-board systems, or complex stacked epoxies, have the ability to form a bond placed on the substrate, typically using die-on-die assemblies. In the field, these that is mechanically robust and thermally vision control systems to ensure proper packages, systems and assemblies must stable. Epoxies are among the strongest placement. As the die bonder places the remain resistant to mechanical and ther- and most durable adhesives, offering die on the adhesive, it adds a slight and mal conditions that can degrade perfor- mechanical strength, superior dimen- carefully controlled amount of pressure mance and, ultimately, lead to product sional stability and excellent adhesion to to mate the die to the adhesive-treated failure. similar and dissimilar substrates. Manu- substrate (Figure 1). Adhesives have emerged as the facturers can find highly specialized In this process, the application of preferred solution for meeting these epoxy adhesives designed to address the the adhesive is critical. Too much adhe- demands with their ability to support unique demands of individual applica- sive, and the resulting fillet can flow up broadly diverse requirements for assem- tions for thermal and electrical conduc- the sides of the die and contaminate the bly, manufacturing, and product life- tivity, temperature range, outgassing, and circuits etched on the die. Too little and cycle. Along with their ability to tightly many additional requirements. the die could lift from the substrate or bind die to different materials, adhesives even crack. Depending on the nature of are able to meet complex combinations Facilitating Assembly of requirements for electrical and thermal Die attach adhesives serve an inte- conductivity as well as a host of other gral role in semiconductor assembly physical characteristics including viscos- and manufacturing. After semiconduc- ity, thermal stability, and more. tor wafer fabrication, individual die are Among the diverse types of adhe- separated from the wafer by a precision sives, epoxies are particularly effective in dicing saw or laser. High-speed die bond- enhancing product reliability with their ers are used to lift each die and place it Figure 1. Die-attach adhesives are designed ability to provide high strength bonds on a layer of die-attach material spread to provide tight bonds of uniform thick- while reducing effects of thermal cycling onto the substrate itself by specialized ness with minimal extruded fillet. and mechanical stress. Many one part material dispensers. These dispensers Source: Master Bond Inc.

20 MEPTEC REPORT FALL 2016 meptec.org the process and the characteristics of the adhesive, the substrate might be heated during this placement process to partial cure the die attach material. In the final step, the die/substrate assemblies will typically be subjected to a final curing process using heat or UV treatment. For heat-sensitive circuits, dual curing UV epoxies could be used, which offer a fast alignment and reduce the chances of substrate warping or shrinkage. Specialty dual curing UV epoxies can be fully cured at temperatures as low as 80˚ C, after an initial UV tack. Successful semiconductor assembly depends critically on the nature of the die-attach adhesive itself. The adhesive must be able to form a tight, uniform bond between die and substrate. Still, an adhesive’s cohesive strength is only one of many necessary characteristics. For example, an adhesive must exhibit appropriate viscosity (resistance to flow) and thixotropic index (ability to hold Figure 2. One part epoxy system delivered pre-mixed in syringe, simplifies handling while its shape) to ensure proper formation of eliminating potential problems such as mixing errors. Source: Master Bond Inc. bonds. Adhesives must be able to flow smoothly over irregularities in die and mately in long-term product reliability. which can erode IC reliability. Special- substrate surfaces. Despite the precision Indeed, the thermal characteristics of ized epoxies designed for very humid of the semiconductor fabrication process, the die-attach material directly impact environments resist absorption of mois- die can nonetheless exhibit micrometer- long-term reliability. In fact, manufactur- ture that can lead to fractures in the bond size peaks and valleys. Incomplete fillers can find die-attach adhesives with or weakening at the bonded interfaces ing of valleys or flow around peaks can CTE characteristics designed to accom- and eventual delamination and failure. lead to voids that weaken the bond, even modate specific types of substrates. Temperature stability is important resulting in delamination and eventual for any die-attach application but par- separation of the die from the substrate. Meeting Unique Requirements ticularly so for devices targeted for high Every die-attach application faces temperature applications. Adhesives are Enhancing Product Lifecycle common requirements for bond strength, available across a very wide temperature, The adhesive’s ability to provide a heat dissipation and CTE matching -- supporting requirements ranging from uniform but very thin bond becomes and epoxy die-attach adhesives are well- cyrogenic applications to those operating important throughout the product life- suited for meeting these requirements. at hundreds of degrees. cycle. Minimum thickness means fewer Beyond their fundamental characteristics Of course, manufacturers face a very chances of air voids that can lead to for strength and thermal performance, wide range of requirements beyond ther- eventual bond failure. Minimum thick- however, these adhesives offer unique mal stability both during assembly and ness is also important in ensuring maxi- advantages for meeting the more special- throughout the IC’s lifecycle. During mum heat transfer from the die. ized requirements found in every applica- assembly, the ability to minimize curing Along with its responsibility for tion. temperature can be vital for achieving tightly bonding the die to the substrate, Different epoxy die-attach adhesives acceptable manufacturing yield. Simi- die attach material typically serves as can provide electrically insulated bonds larly, the ability to meet very specific a primary path for die heat dissipation. or electrically conductive bonds such as requirements for bond strength, thermal The efficiency of that heat-transfer path those required for exposed pad devices, conductivity, and avoiding CTE mis- depends on the thickness of the die- for example. For applications targeted matches can spell the difference between attach layer, the thermal conductivity of for outer space, high vacuum or opti- early failure and extended lifetime of the die-attach material, and the thermal cal applications, manufacturers can find semiconductor products. Indeed, each resistance between the die-attach material epoxies with low outgassing characteris- application brings a unique combination and the two surfaces it bonds. By provid- tics. of requirements, requiring an equally ing an efficient path for heat dissipation, Most applications must deal with diverse complement of available die- the die-attach adhesive plays a central more mundane environmental factors attach materials that are well-matched to role in thermal management -- and ulti- such as high temperature and humidity, those specific requirements. meptec.org FALL 2016 MEPTEC REPORT 21 ASSEMBLY

Diverse Solutions cific handling times as well as different Conclusions Manufacturers can find die-attach curing times and temperatures. One-part Die-attach materials serve a critical role epoxies designed to meet a very wide systems further simplify the assembly in facilitating semiconductor assembly Industrial Controls range of specialized requirements for process. Some one-part systems may be and ongoing performance throughout assembly and lifecycle performance. delivered as non-premixed and frozen, the product lifecycle. Along with funda- Die-attach epoxy systems offer character- which help eliminate potential problems mental requirements for bond strength, istics suited to a wide range of lifecycle such as air entrapment during preparation conductivity and stability, each applica- requirements for strength, thermal and or concerns about limited potting time. tion adds its unique set of additional electrical conductivity, thermal stability, (Figure 2). performance demands. Epoxy die-attach and more. Specialized epoxies can meet Along with their inherent strength adhesives meet these requirements with demands as varied as low outgassing and durability, epoxies offer an additional a broad array of performance characteris- performance for space applications to advantage. Epoxies can be combined tics designed not only to support efficient biocompatibility for medical applications with specialized filler materials to meet manufacturing but also to help ensure as well as continued reliability in appli- specific requirements. For example, long-term product reliability. ◆ cations exposed to mechanical vibration, epoxy vendors can add glass microbeads Venkat Nandivada has been the Manager of Techni- impact, and shock. to enhance uniformity of bond thickness; cal Support at Master Bond Inc. since 2010. He To meet different assembly require- silver fillers to dramatically enhance has a Masters in Chemical Engineering from Carn- ments, epoxies are available with a electrical conductivity; special thermally egie Mellon University. He analyzes application wide range of delivery options. Today’s conductive fillers to enhance thermal oriented issues and provides product solutions for two-part epoxies go beyond traditional conductivity; and other filler materials to companies in the aerospace, electronics, medical, epoxy systems with a range of resin and optimize individual characteristics such optical, OEM and oil/chemical industries. hardener combinations designed for spe- as CTE.

22 MEPTEC REPORT FALL 2016 meptec.org Industrial Controls Medical Applications Aerospace Systems

The SMART Advantage. Lowest Overall Development Time and Cost

SMART PROTOTYPE DEVELOPMENT As a turn-key solution, SMART Microsystems builds early proof-of-concept samples as well as feasibility studies to help you avoid challenges that appear early in process development. SMART Microsystems engineering team’s expertise in MEMS sensor products has solved many of these challenges.

SMART ENVIRONMENTAL LIFE TEST SMART Microsystems’ environmental life testing identifies reliability issues early in your MEMS sensor product development. As part of a turn-key solution, reliability study, or on an as-needed basis for overflow/bandwidth, SMART Microsystems can solve your issues before they become a problem in the field.

SMART MANUFACTURING SERVICES With the SMART Microsystems investment in state-of-the-art facilities and an experienced team, we are able to scale-up manufacturing quickly, support low-volume production, and meet your quality assurance requirements.

SMART Microsystems creates turn-key solutions for microelectronic package assembly challenges to move your MEMS sensor technology from development to production. With an engineering team experienced in manufacturing and state-of-the-art facilities, SMART Microsystems accelerates the transition of your new MEMS sensor product to the market.

Call us today at 440-366-4203 or visit our website at www.smartmicrosystems.com for more information about SMART Microsystems capabilities and services.

Your Microelectronic Package Assembly Solution for MEMS Sensors 141 Innovation Drive, Elyria, Ohio 44035 • [email protected] www.smartmicrosystems.com Customizable Silicone Materials for Advanced MEMS Performance

Raj Peddi and Dr. Wei Yao Henkel Adhesive Electronics

THE APPLICATION OF MICRO- handheld MEMS reliability. The modulus range of Henkel’s electromechanical systems (MEMS) in devices, the new silicone platform can be customized today’s electronics products – from hand- ability to from 0.1 to 200 MPa, delivering the ability held to medical to automotive devices – is control die to optimize stress control and response sen- enabling unprecedented functionality. In stress is essen- sitivity across various die thicknesses and smartphones, the ability to scroll faster, tial. If too much force is applied during dimensions. In addition, the moduli and talk on microphones with noise canceling die bonding, the die can crack. When the expansion coefficients of these products are capability and leverage location navigation bonding adhesive’s modulus is high, the die stable and predictable across a wide tem- via position sensors is all based on MEMS may bend due to stress and this deforma- perature range. Henkel’s Loctite Ablestik technology – and this barely scratches tion can cause the moving components of ABP SIL materials have exceptional ther- the surface of the wealth of applications the MEMS device to go out of calibration, mal stability, maintaining a low and stable associated with MEMS. Overall, consumer compromising its performance. In the case modulus from far below room temperature mobile applications are driving more than of automotive sensors, the response sensi- to temperatures as high as 300°C. The 50% of the total volume for MEMS. In tivity of the sensor is key to control of its thixotropic properties – or the material’s fact, MEMS microphones alone are fore- function. When material properties change ability to hold its shape – can also be modi- cast to grow at a compound annual growth over time and experience shrinkage, for fied based on requirements. A thixotropic rate (CAGR) of greater than 11% between example, the calibration can be altered and index range of 1 to 10 has been successful- 2015 and 2019, according to research firm the device output may be sub-standard. If ly achieved with this new silicone system IHS Inc. the package planarity is slightly off, per- and, for applications that require specific Automotive integration formance of the MEMS device may suffer. colors to accommodate light transmittance of MEMS is also in For critical applications such as air bag requirements, Loctite Ablestik ABP SIL the fast lane. Pres- deployment or braking systems, inferior materials can be custom-formulated in a sure sensors, speed calibration could be catastrophic. Tempera- range of colors. sensors, air flow ture stability of the die attach material is As compared to conventional epoxy- sensors, magnetometers, and accelerom- also vital; both to withstand the heat gener- based materials, Henkel’s new silicone eters – all are based on MEMS and are ated by die function and the environmental platform provides numerous advantages, critical elements to proper automobile func- temperatures to which the device may ulti- delivering customizable properties to tion and efficiency. And, while handhelds, mately be subjected. ensure robust function and better long-term automotive and even medical devices are Tackling these demands, reliability. As the use of MEMS applica- similar in their requirement for MEMS Henkel has devel- tions proliferates both within specific end and sensor capability, the application and oped a customizable products and across market sectors, the design considerations are vastly differ- silicone platform need for modifiable materials platforms to ent. For handheld devices, space is at a that allows for modifi- address unique performance requirements premium and dictates exceptionally small cation of key properties such as rheology, will be immense. Henkel is leading the dimensions with MEMS devices that con- modulus and color, with a wide process market in this formulation approach with tain thin, fragile features. With automotive window during material application such its new Loctite ABP SIL series of materials MEMS devices and other sensor technolo- as dispensing and cure. The formulation for advanced MEMS and sensor produc- gies, sensitivity level and high temperature innovation of the Loctite® Ablestik® ABP tion. compatibility are key considerations. SIL series of die attach materials takes into For more information, visit www. Because of the variations in device consideration the varying properties that henkel-adheisves.com/electronics or call function and manufacturing considerations, are necessary for a particular application +1-888-943-6535 in the Americas, +32 selecting the proper materials is critical for and allows for their modification to help 1457 5611 in Europe or +86 21 3898 4800 end use reliability and performance. With ensure better performance and long-term in Asia. ◆

24 MEPTEC REPORT FALL 2016 meptec.org TThehe smaller smaller the the device device - -the the more more solutions solutions

NoNo matter matter where where you you are are or orwhat what your your process process requires, requires, you you can can count count on on Henkel‘s Henkel‘s expertise. expertise. OurOur unmatched unmatched portfolio portfolio of ofadvanced advanced materials materials for for the the semiconductor semiconductor and and assembly assembly markets markets all all backedbacked by by the the innovation, innovation, knowledge knowledge and and support support of ofHenkel‘s Henkel‘s world-class world-class global global team team ensures ensures youryour success success and and guarantees guarantees a low-riska low-risk partnership partnership proposition. proposition. OPINION

Next-Generation Devices, Brought to You by Advanced Packaging Technologies

Françoise von Trapp 3D InCites

TRUE BELIEVERS HAVE BEEN ing, nobody else was going to either. gies to bring disparate functions together. predicting it for years. In 2007, the Janu- And then just like that, it happened. Ear- Subu Iyer , Distinguished Chancel- ary cover of Advanced Packaging magazine lier this year, at the International Solid-State lor’s Professor, UCLA, said it best when he declared boldly, “Packaging Saves the Circuits Conference in San Francisco, Jan. declared, “If you can’t scale the chip, scale World!” The ensuing annual roundup article 31 - Feb. 5, 2016, William Holt, Intel execu- something else.” So much effort has gone into was a collection of predictions by advanced tive VP, spoke about Intel’s shift in focus scaling silicon while the package and board packaging experts who already understood away from traditional CMOS scaling and its features have scaled modestly. This will be what it took the front-end guys another nine 51-year-old quest for doubling performance the focus of his work at UCLA, where he has years to figure out (or at least come to terms and speed every two years by doubling the launched the CHIPS Project. with): that Moore’s law would reach its limits, number of transistors on a chip. Rather, focus And while imec continues its dedication and a system-on-chip approach would only is shifting to lower power consumption, even to extending Moore’s law, Luc Van den hove make sense for so long before it would not if that means sacrificing performance. Not did say that it would use a different approach be the optimal approach for heterogeneous long after, Babak Sabi, Intel corporate vice that draws on all the technologies in its arse- integration. president and director of assembly and test nal, including 3D heterogeneous integration, Those who saw the writing on the wall technology development, said that Intel would Si photonics, quantum computing, and cell invested in development of advanced wafer- begin integrating 2.5D and 3D packaging stacking approaches. level packaging technologies, and we wit- technologies this year. This is how it will be To top it all off, in July at SEMICON nessed the emergence of system-in-package able to improve performance and speed. Not West, it was announced that the Hetero- (SiP), interposer integration (aka 2.5D); 3D only that, the semiconductor giant is aggres- geneous Integration Roadmap, enabled by integration technologies like through silicon sively going after IoT applications, which FOWLP, system-in-package, interposer vias (TSVs) and die stacking; and fan-out calls for integration of disparate technologies integration, and yes, even die stacking using wafer-level packaging (FOWLP). These tech- in a small space, and that requires low power, TSVs, has replaced the International Technol- nologies are now all mature, and those that and not spectacularly high performance. ogy Roadmap for Semiconductors, which just aren’t already in volume manufacturing have Since then, advanced packaging tech- released its final edition. been ready and waiting for the rest of the nologies have become the rock stars of the In his SEMICON West keynote, Cisco’s industry to realize the value and opportunity industry as the focus shifts from die shrink John Kern talked about the importance of they provide. to system scaling. It seems every conference innovation. “We fundamentally do not believe We started to gain traction in the past I’ve attended since has pointed to packaging that commoditization is a good path for the 12 months, thanks in part to the launch of as the next rising star; and into the foreseeable semiconductor industry,” he stated. Rather, AMD’s Fiji processor for its Radeon Fury future, advanced packaging technologies – not he said Cisco is willing to pay for the added graphics processor unit, which uses silicon scaling – are critical to reaching the capacity, value realized by innovation, and would con- interposers with 65,000 TSVs and a logic die power, and performance for the next genera- tinue to invest in the industry. Finally. in the center of four HBM stacks with four tion of devices. Need more proof that advanced and 3D DRAM each. Additionally, the news that At ECTC 2016 in June, a panel of experts packaging are the new “it” technologies? TSMC’s integrated fan-out technology (InFO) addressed the topic of life after Moore’s At SEMICON West, TSMC’s Doug Yu would be in the iPhone 7 caused market law, and featured senior executives from the announced that the company’s new goal is to analysts to adjust their numbers for FOWLP world’s leading microelectronics research grow from the world’s leading IC foundry to upward. institutes, all of whom declared that efforts the industry’s first SiP foundry, recognizing So why has it been such a long road? will focus on packaging. Both CEA-Leti and that to survive and grow, the company needs While there are many mitigating factors, UCLA are working on approaches that cre- to offer more than just foundry services. one general reality is that the semiconductor ate hard libraries of chiplets, also known as “Achieving micron scale is easy when industry is characteristically slow to change. dielets, and integrating them using 3D tech- you’re used to doing nanometer-scale pro- It is also understandably cost-sensitive, and nologies. cessing,” he said. The company has achieved the belief that packaging is a cost-adder Leti has demonstrated a working 3D two industry firsts already: It was the first rather than a value-add has been a long-held network-on-chip, based on the chiplet archi- to deliver Si interposer chip-on-wafer-on- perception that we in the advanced packaging tecture using a VLSI approach. Instead of substrate for high-performance computing; sector have been trying to change for years. large chips with aggressive technology nodes and the first to propose and realize InFO PoP Incumbent technologies rule until they simply that are complex and low yielding, the idea is for mobile SiP applications. don’t live up to requirements. And let’s face to divide the chip into smaller, repetitive chips My friends in advanced packaging, I it: Until Intel was ready to cry “uncle” to scal- and use interposer and packaging technolo- believe we have arrived. ◆

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