Design for Electromagnetic Compatibility (EMC) - ECE

455/655

Benjamin D. Braaten

North Dakota State University Department of Electrical and Computer Engineering

Fargo, ND, USA.

Last updated: 1/28/2014

1 TABLE OF CONTENTS

CHAPTER 1. INTRODUCTION TO ELECROMAGNETIC COMPATIBILITY (EMC) 6

1.1. Introduction ...... 6

1.2. Review of Decibel (dB) and Phasors ...... 7

1.2.1. Decibels ...... 7

1.2.2. Phasors ...... 8

1.2.3. Example 1 ...... 9

1.2.4. Example 2 ...... 9

1.2.5. Measurements using decibels ...... 9

1.3. Capacitance and Inductance of Certain Structures ...... 11

1.3.1. Parallel plate capacitor ...... 11

1.3.2. Two parallel wires ...... 11

1.3.3. Coaxial-cable ...... 12

1.3.4. Mutual inductance ...... 12

1.3.5. Example 3 ...... 13

1.3.6. Internal inductance ...... 14

CHAPTER 2. TRANSMISSION LINES AND COUPLING ...... 16

2.1. Lossless Propagation ...... 18

2.1.1. Wave velocity and characteristic impedance ...... 18

2.1.2. Phase constant, phase velocity and wavelength ...... 19

2.1.3. Voltage and current along the transmission line ...... 20

2.2. Examples: Transmission Lines ...... 23

2 2.2.1. Example 1 ...... 23

2.2.2. Example 2 ...... 23

2.3. Wave Reflections ...... 24

2.3.1. Reflection coefficient and transmission coefficient ...... 24

2.3.2. Reflected power...... 25

2.4. Coupling Between Transmission Lines ...... 26

2.4.1. General Problem ...... 26

2.4.2. Capacitive coupling (low frequencies) ...... 27

2.4.3. Inductive coupling (low frequencies) ...... 29

2.4.4. Equations for both inductive and capacitive coupling ...... 31

2.5. Shielding ...... 33

2.5.1. Reducing capacitive coupling ...... 33

2.5.2. Reducing inductive coupling ...... 35

2.5.3. Summary of transmission line coupling equations ...... 38

2.6. Twisted pair ...... 40

2.6.1. Inductive coupling - unbalanced ...... 41

2.6.2. Capacitive coupling - unbalanced ...... 42

2.6.3. Balanced case ...... 43

CHAPTER 3. DESIGNING FOR EMC ...... 45

3.1. Components ...... 45

3.1.1. Conductors ...... 45

3.1.2. Skin depth ...... 45

3.1.3. AC parameters ...... 46

3 3.1.4. Non-ideal capacitors ...... 47

3.1.5. Non-ideal resistors ...... 48

3.1.6. Non-ideal inductors ...... 49

3.2. Ferrite Beads ...... 50

3.3. Grounding ...... 51

3.3.1. 3-types of (signal) ground systems...... 52

3.3.2. EMC grounding philosophy ...... 54

3.3.3. Examples of cable grounding ...... 54

3.3.4. The 2-types of current in EMC ...... 55

3.3.5. Common-mode choke ...... 55

3.3.6. Balanced circuits ...... 56

3.4. Filtering ...... 57

3.4.1. Introduction to insertion loss ...... 57

3.4.2. Insertion loss example of a capacitor ...... 57

3.4.3. Differential- and common-mode filters ...... 58

3.4.4. Designing maximally flat Butterworth filters ...... 60

3.4.5. Low-pass filter design...... 60

3.4.6. LP Butterworth filter example ...... 63

3.4.7. High-pass filter design ...... 63

3.4.8. HP Butterworth filter example ...... 64

3.4.9. Band-pass filter design...... 65

3.4.10. BP Butterworth filter example one ...... 68

4 3.4.11. BP Butterworth filter example two ...... 70

3.4.12. Band-stop filter design ...... 70

CHAPTER 4. DIGITAL CIRCUITS ...... 73

4.1. Noise ...... 73

4.2. Decoupling Capacitors ...... 74

5 CHAPTER 1. INTRODUCTION TO ELECROMAGNETIC COMPATIBILITY (EMC)

1.1. Introduction Electromagnetic Compatibility (EMC) is the study of how electrical devices interact electromagnet- ically. When a unit under test (UUT) is susceptible to other devices radiating in the region we call this electromagnetic interference (EMI). When a UUT is radiating significantly into the surrounding region, we call this radiated emissions (i.e., the UUT is the source of the noise). Overall EMC has two major aspects (Fig. 1): 1) Emissions (source of noise)

-radiated

-conducted

2) Susceptibility -radiated

-conducted

Radiated emissions

Radiated susceptibility Unit Under Test (Equipment Under Test) UUT (EUT) Conducted emissions

Table Cable

Conducted susceptibility

Figure 1. Diagram of UUT.

A definition of EMC (Henry Ott): “The ability of an electronic system to 1) functions properly in its intended EM environment; and 2) not be a source of pollution to that environment. For EMI to exist we must have the system illustrated in Fig. 2. When considering the channel coupling we have the following types of coupling:

6 1) Radiation -capacitive coupling (E-field dominant).

-inductive coupling (H-field dominant).

-EM radiation.

2) Common impedance coupling

-currents from two circuits flow through the same impedance. 3) Conductively coupled noise

-noise is conductively coupled from a “noisy” to a “quiet” environment.

Noise Coupling “Victim” source channel

Figure 2. Diagram of EMI.

1.2. Review of Decibel (dB) and Phasors

1.2.1. Decibels In this section we review the use of decibels. The number of decibels is the logarithmic ratio of the powers of interest or:

( ) P P ower = 10 log 2 . (1.1) P1

The units of the ratio are (2.1) is dB and referred to as decibels. Equation (2.1) can be used to express the power gain of a circuit. For example, if P1 = 10W and P2 = 5W in Fig. 3 then the power gain = 10 log(P2/P1) = −3.01dB.

I1 I2 + +

V1 Z1 Z2 V2

- -

Figure 3. Equivalent circuit.

7 1.2.2. Phasors Now we switch our focus to phasors. In this course we use the following notation:

[ ] e jωt e V (z, t) = Re V e = |Vm|∠ϕ = V = phasor voltage (1.2)

e where V (z, t) represents the voltage in the time domain and V represents[ ] the voltage in the frequency domain. For example, if Ve = 3∠30 = 3ej30 then V (z, t) = Re 3ejωtej30 = 3 cos(ωt + 30). e e Next, if V1 and I1 are rms quantities, [ ] e e ∗ P1 = Re V1I1 [ ] e e ∗ = Re (I1Z1)(I1 ) [ ] e 2 = Re |I1| (R1 + jX1)

e 2 = |I1| R1 |Ve |2 = 1 . R1

e e Now let V1 = |V1| and I1 = |I1|. This then gives ( ) ( ) 2 P2 V2 R1 10 log = 10 log 2 P1 (V1 )R2 ( ) 2 V2 R1 = 10 log 2 + 10 log (V1 ) ( R2) V R = 20 log 2 + 10 log 1 . V1 R2

Therefore, ( ) ( ) P V 10 log 2 = 20 log 2 (1.3) P1 V1 only when R1 = R2. Next, we define dBm in the following manner: ( ) P P (dBm) = 10 log . (1.4) 1mW

8 The values written in terms of dBm simply mean that the power value of interest is referenced to 1 mW. ⇒ P = (10P (dBm)/10)1mW .

1.2.3. Example 1

Suppose I measure 20 dB of power across 50 Ω. When just dB is written, that means that the power is being referenced to 1 W. ⇒ 20dB = 10 log(P/1W ) ⇒ P = 102 = 100W . Next, what is 25 mW written in (a) dBm, (b) dB and (c) dBµW? (a) 10 log(25 × 10−3/1 × 10−3) = 13.98dBm

(b) 10 log(25 × 10−3/1) = 10 log(25) + 10 log(10−3) = −16.02dB

(c) 10 log(25 × 10−3/1 × 10−6) = 13.98 + 30 = 43.98dBµW

1.2.4. Example 2

Next, as another example, express 20 dB of power dissipated by a 50 Ω resistor in terms of dBV, dBµV, dBA and dBmA.

20dB = 10 log(P/1W ) ⇒ P = 100W . If we assume rms values of voltage and current,

P = V 2/R = I2R. ⇒ V = 70.71V and I = 1.414A. Therefore,

( ) 70.71V 20 log = 37dBV ( 1V ) 70.71V 20 log = 157dBµV ( 1µV ) 1.414A 20 log = 3dBA ( 1A ) 1.414A 20 log = 63dBmA. 1mA

1.2.5. Measurements using decibels

In this section we consider the problem described in Fig. 4. In Fig. 4 a device is radiating into the surrounding space. A biconical antenna is used to measure the frequency and magnitude of the radiated field. To convert the measured value into the magnitude of the electric field we introduce the Antenna Factor (AF) and it is related to the electric field in the following manner:

9 E AF = inc (1.5) Vr where Einc is the field radiated by the device and Vr is the voltage at the output terminals of the antenna.

E/H-field Biconical antenna

Measured with Radiating device Vr spectrum analyzer

Figure 4. Using a biconical antenna to measure the radiated fields from a device.

An alternate representation of the AF is the following:

[ ] E V inc = AF r . (1.6) 1 × 10−6 1 × 10−6

Taking 20 log() of (2.6) results in the following expression:

Einc(dBµV/m) = AF (dB) + Vr(dBµV ). (1.7)

Then, if the input impedance of the spectrum analyzer is 50Ω,

Vr(dBµV ) = P (dBm) + 107. (1.8)

If we need to add the cable loss then

Einc(dBµV/m) = P (dBm) + 107 + C.L.(dB) + AF (dB) (1.9) where C.L. is the cable loss in decibels. Note that the expression in (2.9) is at each frequency.

10 1.3. Capacitance and Inductance of Certain Structures

Q From applied electromagnetics we know C = V where C is the capacitance, Q is the total charge and V is the potential between the conductors of interest (Fig. 5). Using this expression we can derive the equivalent capacitance between conductors of certain common structures. There are three ways to determine C: ∫ 1) Assume ±Q on the conductors and determine V = − E¯ · d¯l. 2) Assume V between the conductors and determine Q (maybe solve ∇2V = 0 for V (z) then H E¯ = −∇V and Q = Dd¯ s¯). ∫ ∫ ∫ ¯ 2 2 3) Compute the energy stored in the structure by using WE = ε/2 |E| dV = 1/2CV ⇒

2 C = 2WE/V .

Conductors

+Q -Q

V

Figure 5. Definition of the capacitance between two conductors.

1.3.1. Parallel plate capacitor

For the first structure, we consider the two large parallel plates shown in Fig. 6. Us- ∫ ¯ ¯ ing method 1) (Fig. 7) we assume ±Q on the top and bottom plates. ⇒ V0 = − Edl = ∫ − d − ⇒ 0 (ρs/ε0)( aˆz)(dzaˆz) = ρsd/ε0 = Qd/(Sε0). C = ε0S/d. Next, using method 2) (Fig. 8) we have ∇2V = 0 + 0 + ∂2V/∂z2 = 0. ⇒ ∂2V/∂z2 = 0.

Assuming a solution of V (z) = Az + B and applying the B.C. of B = 0 and A = V0/d gives V (z) = ¯ V0z/d. Next, using E = −∇V = −∂V/∂zaˆz = (−V0/d)(ˆaz). From the boundary conditions at z = d we get Dn = ρs ⇒ ε0En = ρs. ⇒ ε0V0/d = ρs ⇒ Q = ρsS = Sε0V0/d. ⇒ C = Q/V0 = ε0S/d. 1.3.2. Two parallel wires

Next, it can be shown that the capacitance per unit length of the two-wire TL shown in Fig.

11 z

y Large plate with area S

Free space µ0, ε0 d (very small distance)

x Figure 6. Parallel plate capacitors.

Surface charge density +

Vd - +Q = (+ρs)(S)

Ez = (ρs/ ε0)z

-Q = (-ρs)(S) Figure 7. Charge distribution on the parallel plate capacitors.

9 is C ≈ πε/ ln(d/a) (F/m) where ε is the permittivity of the homogenious material containing the wires and d is the separation between the center of the conductors. Similarly, for the single conductor in Fig. 9 b), if h >> a then C ≈ 2πε/ ln(2h/a) (F/m).

1.3.3. Coaxial-cable

Next, we calculate the self inductance of the coaxial-cable TL shown in Fig. 10. The magnetic

field can be written as H = I/2πρaˆϕ for ρ > a and assuming the wire is along the z-axis. ⇒ ∫ ∫ L = Ψ/I. Assuming a constant current, the magnetic flux Ψ can be written as Ψ = Bd¯ s¯ = ∫ ∫ 1 b ⇒ 0 a (µI/2πρ)(ˆaϕ)dρdzaˆϕ = (µI/2π) ln(b/a). L = (µ/2π) ln(b/a). 1.3.4. Mutual inductance

Inductance is defined to be the (ratio of the magnetic flux linked)/(the current creating the

flux). Thus, self inductance deals with the flux that links the current that created it and mutual inductance deals with the flux that one current creates that links a second current (Fig. 11). From

12 z

V = V 0 at z = d

d ρv = 0

V = 0 at z = 0 Figure 8. Potential between the plates.

radius r = a

h radius r = a ground plane d a) b) Figure 9. a) Two parallel conductors; b) A single conductor above a ground plane. this we can write the self-inductance as NΨ L = (1.10) I and the mutual inductance as

N2Ψ12 M12 = (1.11) I1 where Ψ is the flux linking each of the turns, Ψ12 is the flux created by I1 that links each of the N2 turns and I1 is the current creating the flux. 1.3.5. Example 3

In this example we want to calculate the mutual inductance between the structures shown in

Fig. 12. If we assume that a constant current is flowing in the z-direction along the wire, then we can write the magnetic field as H = I/(2πρ)ˆaϕ (in cylindrical coordinates). Next we need to

13 z

dielectric Two conducting cylinders (σ,ε,µ0µr) a b H I Current returns on the shield I Figure 10. A coaxial-TL.

I1 I2

Figure 11. Mutual inductance.

compute Ψ12 in (2.10) in the following manner:

∫ ∫ ∫ ∫ ( ) [ ( )] 5 5 ¯ µ0I1 µ0I1 5 Ψ12 = B · ds¯ = aˆϕ (dρdzaˆϕ) = ln 5. 0 3 2πρ 2π 3

⇒ M12 = 5.1µH. In this case M12 = M21. 1.3.6. Internal inductance

Finally, the internal inductance of a wire (Fig. 13) can be written as Linternal = µ0/8π for a solid wire.

14 z

I1 5 m I2 3 m 2 m

Figure 12. Mutual inductance between a loop and a wire.

I

Solid wire

Figure 13. Internal inductance of a solid wire.

15 CHAPTER 2. TRANSMISSION LINES AND COUPLING

Next, consider the per-unit equivalent (lumped element model) circuit of a short TL shown in Fig. 14. R represents the conductor loss, L represents the line inductance, C represents the line capacitance and G represents the loss in the dielectric between the conductors. Now we want to derive expressions for V (z) and I(z) on the TL shown in Fig. 14 in terms of R, L, C and G.

1/2R∆z 1/2L∆z KCL 1/2L∆z 1/2R∆z + I I+ ∆I + Ic IG V V+ ∆V C∆z - G∆z KVL -

∆z Figure 14. Per-unit equivalent circuit of a TL.

First, using KVL on the circuit shown in Fig. 14:

1 1 ∂I 1 ∂ 1 V = R∆zI + L∆z + L∆z (I + ∆I) + R∆z(I + ∆I) + V + ∆V. (2.1) 2 2 ∂t 2 ∂t 2

⇒ ( ) V 1 1 ∂I 1 ∂I ∂∆I 1 V ∆V = RI + L + L + + R(I + ∆I) + + . (2.2) ∆z 2 2 ∂t 2 ∂t ∂t 2 ∆z ∆z

⇒ ∆V ∂I 1 1 ∂∆I = −RI − L − R∆I − L . (2.3) ∆z ∂t 2 2 ∂t

→ → → ∆V → ∂V Next, evaluating the limit ∆z 0 (i.e., lim∆z→0) we have I + ∆I I, ∆I 0 and ∆z ∂z . This then reduces 2.3 to the following:

( ) ∂V ∂I = − RI + L . (2.4) ∂z ∂t

16 Next, using KCL on the circuit shown in Fig. 14:

I = I + I + I + ∆I G (C ) ( ) ∆V ∂ ∆V = G∆z V + + C∆z V + + I + ∆I. (2.5) 2 ∂t 2

⇒ ( ) ( ) I ∆V ∂ ∆V I ∆I = G V + + C V + + + . (2.6) ∆z 2 ∂t 2 ∆z ∆z

⇒ ( ) ( ) ∆I ∆V ∂ ∆V = −G V + − C V + . (2.7) ∆z 2 ∂t 2

→ → → ∆I → ∂I Next, evaluating the limit ∆z 0 (i.e., lim∆z→0) we have V + ∆V V , ∆V 0 and ∆z ∂z . This then reduces 2.7 to the following:

( ) ∂I ∂V = − GV + C . (2.8) ∂z ∂t

Equations 2.4 and 2.8 are referred to as the telegraphist’s equations. Their solutions lead to the wave equations on the TL. Next, differentiating (2.4) w.r.t. z and (2.8) w.r.t. t we get:

∂2V ∂I ∂2I = −R − L (2.9) ∂z2 ∂z ∂t∂z and ∂2I ∂V ∂2V = −G − C . (2.10) ∂z∂t ∂t ∂t2

Next, substituting (2.8) and (2.10) into (2.9) gives

∂2V ∂2V ∂V = LC + (LG + RC) + RGV. (2.11) ∂z2 ∂t2 ∂t

17 Similar substitutions result in the following expression:

∂2I ∂2I ∂I = LC + (LG + RC) + RGI. (2.12) ∂z2 ∂t2 ∂t

Equations (2.11) and (2.12) represent the general wave equations for the TL in Fig. 14.

2.1. Lossless Propagation

2.1.1. Wave velocity and characteristic impedance

For lossless propagation we have R = G = 0 in Fig. 14. This then simplifies (2.11) and (2.12) to the following: ∂2V ∂2V = LC (2.13) ∂z2 ∂t2 and ∂2I ∂2I = LC . (2.14) ∂z2 ∂t2

Solving the second order partial differential equations in (2.13) and (2.14) results in the following assumed solutions:

+ − V (z, t) = f1(t − z/ν) + f2(t + z/ν) = V + V (2.15) where ν represents the wave velocity, V + represents the forward traveling wave and V − represents the backward traveling wave or reflected wave. The t − z/ν represents the forward traveling wave.

As t increases, z must also increase to sustain f(0) (the wave front). To solve for the wave velocity

∂2V ∂2V we consider the solution of V (z, t) to ∂z2 = LC ∂t2 . With out loss of generality we consider only f1. ⇒

∂V (z, t) ∂f ∂f ∂(t − z/ν) −1 ′ = 1 = 1 = f (2.16) ∂z ∂z ∂(t − z/ν) ∂z v 1

′ where f1 is the partial derivative w.r.t. the argument. Similarly we have

∂V (z, t) ∂f ∂f ∂(t − z/ν) ′ = 1 = 1 = f , (2.17) ∂t ∂t ∂(t − z/ν) ∂t 1

18 2 ∂ f 1 ′′ 1 = f (2.18) ∂z2 ν2 1 and 2 ∂ f ′′ 1 = f . (2.19) ∂t2 1

Notice that (2.18) and (2.19) are simply derivatives of f1 w.r.t. z and t, respectively. Substituting (2.18) and (2.19) into (2.13) results in the following expression:

2 2 ∂ V 1 ′′ ′′ ∂ V = f = LCf = LC (2.20) ∂z2 ν2 1 1 ∂t2 or 1 ′′ ′′ f = LCf . (2.21) ν2 1 1

′′ Canceling f1 results in the following expression for the wave velocity ν:

1 ν = √ . (2.22) LC

Similarly for (2.14) we have the following solution:

[ ] 1 + − 1 I(z, t) = f1(t − z/ν) − f2(t + z/ν) = I + I = V (z, t) (2.23) Lν Z0 where √ L Z = . (2.24) 0 C

Z0 is referred to as the characteristic impedance of the TL. Notice the expressions for the wave velocity and characteristic impedance are written entirely in terms of L and C. This indicates that ν and Z0 are dependent only on the dimensions of the physical structure and not time and frequency.

2.1.2. Phase constant, phase velocity and wavelength

In this section we derive the expressions for the voltage and current along the TL when a

19 steady-state sinusoidal source is used to drive the TL. Start by defining f1 = f2 = V0 cos(ωt + ϕ).

From the previous section we have t = t ± z/νp where νp is referred to as the phase velocity. ⇒

V (z, t) = |V0| cos[ω(t + z/νp) + ϕ]

= |V0| cos[ωt ± βz + ϕ]. (2.25)

⇒

+ V = Vf (z, t) = |V0| cos[ωt + βz + ϕ] (2.26) and

− V = Vb(z, t) = |V0| cos[ωt − βz + ϕ] (2.27) where ω β = . (2.28) νp

β is called the phase constant of the TL. If t = 0 (i.e., fix time and look at the spatial variation) then we have Vf (z, 0) = |V0| cos[βz]. Vf (z, 0) represents a periodic function that repeats w.r.t. a value of z. Denote this value as λ and call it the wavelength of the wave. This then gives βλ = 2π. ⇒ 2π ν λ = = p . (2.29) β f

Now, if z = 0 (fix position and look at time variation) then we have V (0, t) = |V0| cos[ωt]. This is illustrated in Fig. 15. Notice that the sinusoid repeats every 2π. ⇒ 1 T = (2.30) f where T is the period of the sinusoid.

2.1.3. Voltage and current along the transmission line

Here we want to represent the voltage along the TL as complex functions. Using Euler’s

20 V(0,t)

+ V0

ωt 2π

Figure 15. Sinusoidal voltage along the TL. identity we have ejx = cos(x) ± j sin(x). ⇒ [ ] [ ] 1 cos(x) = Re ejx = ejx + e−jx (2.31) 2 and [ ] [ ] 1 sin(x) = ±Im ejx = ± ejx − e−jx (2.32) 2j

⇒

V (z, t) = |V | cos[ωt ± βz + ϕ] 0 [ ] 1 j(ωtβz+ϕ) −j(ωtβz+ϕ) = |V0| e + e 2 [ ][ ] 1 jϕ −jϕ j(ωtβz) −j(ωtβz) = |V0| e + e e + e 2 [ ] j(ωtβz) −j(ωtβz) = V0 e + e . (2.33)

[ ] 1 | | jϕ −jϕ Note that V0 was used to represent the complex voltage magnitude 2 V0 e + e in (2.33). Next, define the following

jβz jωt Vc(z, t) = V0e e (2.34) and

jβz Vs(z) = V0e (2.35)

where Vc(z, t) is the complex instantaneous voltage and Vs(z) is the phasor voltage. Again, from

21 the general wave equation (2.11) we have

∂2V ∂2V ∂V = LC + (LG + RC) + RGV. (2.36) ∂z2 ∂t2 ∂t

∂ ⇔ In the phasor domain we also have the relation ∂t jω. ⇒ d2V s = −ω2LCV + jω(LG + RC)V + RGV . (2.37) dz2 s s s

⇒ d2V s = (R + jωL)(G + jωC)V = γ2V (2.38) dz2 s s √ where γ = (R + jωL)(G + jωC) = α + jβ is the propagation constant along the TL. Now

2 + −γz − +γz d Vs 2 assume that Vs(z) = V0 e + V0 e for a solution to dz2 = γ Vs. Similarly, assume Is(z) = + −γz − +γz I0 e + I0 e . Substituting the assumed voltage and current solutions into the transformed expressions of (2.4) and (2.8) gives the following expressions:

dV s = −(R + jωL)I (2.39) dz s and dI s = −(G + jωC)V . (2.40) dz s [ ] ⇒ − + −γz − +γz − + −γz + γz γV0 e + γV0 e = Z I0 e + I0 e where Z0 = R + jωL. Equating the coefficients −γz γz − + − + − − − of e and e gives γV0 = ZI0 and γV0 = ZI0 . Therefore, the characteristic impedance

22 Z0 is

+ V0 Z0 = + I0 − V0 = − − I0 Z = γ Z = √ √ZY Z = (2.41) Y where Y = G + jωC.

⇒ √ R + jωL Z = = |Z |ejθ. (2.42) 0 G + jωC 0

2.2. Examples: Transmission Lines

2.2.1. Example 1 Consider an 80 cm long lossless TL with a source connected to one end operating at 600 MHz.

The lumped element values of the TL are L = 0.25µH/m and C = 100pF/m. Find Z0, β and νp. Solution: Using (2.42) we have √ √ R + jωL 0 + jω.25 × 10−6 Z = = = 50Ω. 0 G + jωC 0 + jω100 × 10−12

√ √ √ Also from (2.38) we have γ = (R + jωL)(G + jωC) = (0 + jωL)(0 + jωC) = 0+jβ = jω LC. √ 6 8 ⇒ β = 2π(600 × 10 ) LC = 18.85rad/m. Finally, we have νp = ω/β = 2 × 10 m/s. 2.2.2. Example 2

A transmission line constructed of two parallel wires in air has a conductance of G = 0Ω. The two parallel wires are made of good conductors, therefore it is assumed that R = 0Ω. If Z0 = 50Ω, β = 20 rad/m and f = 700 MHz, find the per-unit inductance and capacitance of the TL.

Solution:

23 √ √ √ L Since R = G = 0, β = ω LC = 40 = 2π700MHz LC and Z0 = C = 50. Then the ratio of β and Z0 results in the following: β = ωC. Z0

Solving for C then gives:

β C = ωZ0 20 = 2π ∗ 700MHz ∗ 50 = 90.9pF/m.

Finally, solving for L gives:

2 L = Z0 C

= 502 ∗ 90.9 × 10−12

= 227nH/m.

2.3. Wave Reflections

2.3.1. Reflection coefficient and transmission coefficient Next, expressions for describing the reflections of wave along the TL are derived. To do this, consider the TL load in Fig. 16. Next, denote

−αz −jβz Vi(z) = V0ie e (2.43) and

+αz +jβz Vr(z) = V0re e . (2.44)

⇒

VL(0) = Vi(0) + Vr(0) = V0i + V0r (2.45)

24 and 1 IL(0) = I0i + I0r = [V0i − V0r]. (2.46) Z0

Now define the reflection coefficient at the load as

V0r ZL − Z0 Γ = = = |Γ|ejϕΓ . (2.47) V0i ZL + Z0

Now using Γ we can write the voltage at the load in terms of the reflection coefficient and the incident wave in the following manner:

VL = V0i + ΓV0i. (2.48)

Z0 + Vi(z)

VL ZL=R L+jX L Vr(z) -

z = 0 Figure 16. Voltage reflection at the load of a TL.

Now define the transmission coefficient as

V 2Z τ = L = 1 + Γ = L = |τ|ejϕt . (2.49) V0i Z0 + ZL

2.3.2. Reflected power

The time averaged power can be written as

( ) ∗ | |2 1 ∗ 1 −αz −jβz V0 −αz +jβz 1 V0 −2αz < P >= Re(VsIs ) = Re V0e e jθ e e = e cos θ. (2.50) 2 2 |Z0|e 2 |Z0|

Note that θ in (2.50) refers to the angle on the characteristic impedance Z0. Then for z = L we

25 have the following expression for the incident power:

| |2 1 V0 −2αL < Pi >= e cos θ. (2.51) 2 |Z0|

Then, to find the reflected power at the load substitute in the reflected wave in (2.48):

( ) ∗ 1 −αL −jβL (ΓV0) −αL jβL < Pr > = Re ΓV0e e jθ e e 2 Z0e 1 |Γ|2|V |2 = 0 e−2αL cos θ. (2.52) 2 |Z0|

This then leads to the following expression for the reflected power

< P > r = ΓΓ∗ = |Γ|2. (2.53) < Pi >

Similarly, for the transmitted power:

< P > t = 1 − |Γ|2. (2.54) < Pi >

2.4. Coupling Between Transmission Lines

2.4.1. General Problem

To investigate the coupling between two TLs we start with the general problem defined in Fig. 17. The problem insists of two parallel TLs above a common ground plane. The TL with the source is called the generator conductor and the TL with the two resistive loads is called the receptor conductor. Rs is the source resistance, RL is the load resistance, RNE is the near-end load on the receptor conductor and RFE is the far-end load on the receptor conductor. The receptor conductor has a length L. Next, we can derive an equivalent circuit of the coupled TLs. By looking at one small section of the coupled TLs we will be able to describe the interaction between the two TLs. The equivalent circuit for one section of coupled TLs is shown in Figs. 18. We want to simplify the analysis of the

26 Receptor conductor Generator conductor

RL RFE

length L

RNE Rs

Vs

Ground plane Figure 17. General TL coupling problem. coupling between the two TLs in Fig. 18 to the following two cases:

1) capacitive coupling (occurs in high impedance circuits)

2) inductive coupling (occurs in low impedance circuits)

Lg/2 Rg/2 Rg/2 Lg/2

Cgr Lgr /2 Lgr /2

Rs Lr/2 Rr/2 Rr/2 Lr/2 RL Cr Cg RNE RFE Vs

Figure 18. Equivalent circuit of the coupled transmission lines.

2.4.2. Capacitive coupling (low frequencies) For this analysis, we assume that we have high impedance loads on the coupled TLs in Fig.

17. If this is the case, then the coupling between the TLs is mostly capacitive. This reduces the equivalent circuit in Fig. 18 to the equivalent circuits shown in Figs. 19 a) and b).

Next, we want to write the voltages induced on RNE and RFE by Vs. Evaluating the equivalent

27 Receptor conductor Generator conductor

RL RFE Cgr = (cgr )L + + Cgr cap cap Rs L Cr R = RNE ||RFE Cg + r Cg R VNE FE C Vin = V RNE Vs Rs cap VNE - - Vs - Ground plane

a) b) Figure 19. a) Capacitive coupling between the coupled transmission lines and b) the equivalent circuit of the capacitively coupled transmission lines. circuit in Fig. 19 b) gives

( ) R|| 1 V cap = V cap = V jωCr NE FE in R|| 1 + 1 jωCr jωCgr ( ) jω Cgr = V Cgr+Cr . (2.55) in jω + 1 R(Cgr+Cr)

Next, for low frequencies we have the following assumption:

1 ω << . (2.56) R(Cgr + Cr)

This then simplifies (2.55) to cap cap ≈ VNE = VFE jωCgrVinR. (2.57)

Note again that (2.57) is for high impedance circuits. We can also write

( ) Zin Vin = Vs (2.58) Zin + Rs and ( ) [ ( )] 1 1 1 Zin = ||RL|| + R|| . (2.59) jωCg jωCgr jωCr

28 But, for low frequencies we can approximate a capacitor as an open. This then gives

( ) RL Vin ≈ Vg(DC) ≈ Vs . (2.60) RL + Rs

2.4.3. Inductive coupling (low frequencies)

In this section we want to look at the low frequency inductive coupling between the TLs. For this case we simply open all capacitors in Fig. 18. This then results in the equivalent circuit shown

ind in Fig. 20. The near-end voltage can be written as VNE = IrRNE and the far-end voltage can be

Receptor conductor Generator conductor - ind RL VFE RFE Lg Lr + Lgr Ig Ir + RNE Rs ind VNE

Vs - Ground plane Figure 20. The equivalent circuit of the inductively coupled transmission lines.

ind − written as VFE = IrRFE. Next, KVL for the receptor gives IrRNE +jωLrIr +RFEIr jωLgrIg = 0. ⇒

jωLgrIg Ir = . (2.61) (RNE + RFE) + jωLr

Next, KVL around the generator gives −Vs + RsIg + jωLgIg + IgRL − jωIrLgr = 0. ⇒

Vs jωLgr Ig = + Ir. (2.62) (Rs + RL) + jωLg (Rs + RL) + jωLg

Next, if we assume that ωLr << RNE + RFE, ωLg << (Rs + RL) and a weak coupling condition of

29 2 (ωLgr) << (Rs + RL)(RNE + RFE) then

Vs Ig ≈ = Ig(DC) (2.63) Rs + RL and

jωLgr Ir ≈ Ig(DC). (2.64) RNE + RFE

Then −R ind ≈ NE VNE jωLgr Ig(DC) (2.65) RNE + RFE and R ind ≈ FE VFE +jωLgr Ig(DC). (2.66) RNE + RFE

30 2.4.4. Equations for both inductive and capacitive coupling

ind cap Noting that both V and V are proportional to jω and Vs we can write the results as ( ) VNE ind cap = jω MNE + MNE (2.67) Vs and ( ) VFE ind cap = jω MFE + MFE (2.68) Vs where

ind RNE Lgr MNE = , (2.69) RNE + RFE Rs + RL

ind RFE Lgr MFE = (2.70) RNE + RFE Rs + RL and cap cap || RLCgr MNE = MFE = (RNE RFE) . (2.71) Rs + RL

This then results in the inductive/capacitive model shown in Fig. 21 where

RL Vg(DC) = Vs (2.72) RL + Rs and

Vs Ig(DC) = . (2.73) Rs + RL

jωLgr Ig(DC) - + + +

VNE RNE RFE VFE

jωCgr Vg(DC)

- -

Figure 21. The equivalent inductive/capacitive model of the coupled transmission lines.

31 Note that the equivalent circuit model shown in Fig. 21 breaks down for TL lengths longer than ≈ 0.2λ. Therefore, if the frequency is high enough then a smaller segment of the TL should be analyzed or a more accurate distributive model of the coupled TL should be used.

Next, we consider the problem in Fig. 17 for the case when the ground plane has finite conductivity. We represent the loss with a lumped resistor Ro = rol where l is the length of the

TL and ro is the per-unit loss of the ground plane. The problem with Ro defined is shown in Fig.

22. Ro is called the common impedance and Vo is called the common impedance voltage where

Vo = roIref . ⇒ Iref = Ir + Ig ≈ Ig(DC) at low frequencies. ⇒ ( ) Ro Vo ≈ Vs . (2.74) Rs + RL

This voltage appears on the receptor circuit also. Therefore, this contributes to the near- and far-end noise voltages at low frequencies. This then gives:

ci VNE ci = MNE (2.75) Vs and ci VFE ci = MFE (2.76) Vs where

ci RNE Ro MNE = (2.77) RNE + RFE Rs + RL and R R ci − FE o MFE = . (2.78) RNE + RFE Rs + RL

With this notation, we have the following final coupling equations that include the common impedance noise voltages: ( ) VNE ind cap ci = jω MNE + MNE + MNE (2.79) Vs

32 and ( ) VFE ind cap ci = jω MFE + MFE + MFE (2.80) Vs

This results in the equivalent circuit show in Fig. 23.

Rs Ig + + Ir Vs VNE RNE VFE RFE RL + - Vo - - Iref Ro Figure 22. Coupled transmission lines with a lossy reference conductor.

jωLgr Ig(DC) RoIg(DC) - - + + + +

VNE RNE RFE VFE

jωCgr Vg(DC)

- -

Figure 23. The equivalent inductive/capacitive model of the coupled transmission lines with a lossy reference conductor.

2.5. Shielding 2.5.1. Reducing capacitive coupling

In this section we investigate the use of shielding to reduce the coupling between the TLs in

Fig. 17. From (2.57) we can see that we can reduce the capacitive coupling by :

1) reducing frequency

2) reducing RNE and/or RFE

3) reducing Vg(DC) by reducing Vs

4) reducing Cgr by increasing the spacing between the traces and shielding For this section we will focus on using a shield around the receptor to reduce the capacitive

33 coupling. This problem is defined in Fig. 24 where Vs is the generator (source) open circuit voltage,

Vs,o is the output voltage of the source, Cg is the capacitance from the generator to the reference conductor, Cgs is the capacitance from the generator to the shield, Cgr is the capacitance from the generator to the reference conductor, Cs is the capacitance from the shield to the reference conductor, Crs is the capacitance from the receptor conductor to the shield, Cr is the capacitance from the receptor to the reference conductor and Vsh is the voltage between the shield and reference conductor. If we ground the shield on the receptor conductor (at both ends), then we have the equivalent circuit shown in Fig. 25.

Receptor conductor Shield Generator conductor +

FE RL R VFE

Cgs + Cs - Cgr Crs Vsh + g + C Cr - Rs RNE Vs,o VNE

Vs - - Ground plane Figure 24. Capacitively coupled transmission lines with a shielded receptor.

+ + Cgr cap cap Rs L Cr Crs NE FE Cg R Cgs R = R ||R VNE = VFE Vs,o Vg - - Figure 25. The equivalent circuit of the coupled transmission lines with a shielded receptor.

Using circuit analysis, the following expression can be evaluated from the circuit in Fig. 25:

( ( ) ) R|| 1 V cap = V ( jω(Crs+)Cr) (2.81) NE s,o R|| 1 + 1 jω(Crs+Cr) jωCgr or

34 ( ( ) ) jω Cgr V cap = V Cgr+Crs+Cr . (2.82) NE s,o jω + 1 R(Cgr+Crs+Cr)

At low frequencies we have Vs,o ≈ VsRL/(RL + Rs) = Vg(DC) and ω << 1/(R(Cgr + Cr + Crs)). This then simplifies (2.82) down to

cap cap ≈ VNE = VFE jωRCgrVg(DC). (2.83)

Equation (2.83) is similar to (2.57), except in (2.83) Cgr is much less than Cgr in (2.57). 2.5.2. Reducing inductive coupling

When looking at shielding for inductive coupling, we need to first consider the expressions in

(2.65) and (2.66). We can see that we can reduce the inductive coupling by :

1) reducing frequency

2) reducing Ig(DC)

3) reducing Lgr by i) reducing the area between the trace and ground plane

ii) orientation iii) a choke

Generator conductor Shield

RL Lg,sh Lsh Receptor conductor Lg + ind Lsh,r VFE Ig Rsh RFE Ish Lr Rs Lgr - Ir Vs -

ind RNE VNE + Figure 26. Inductively coupled transmission lines with a shielded receptor.

To understand the best method of shielding for inductive coupling we need to consider the problem in Fig. 26. We want to write the voltages across the near- and far-end resistors in

35 terms of the inductive coupling and the source voltage. First, KVL around the shield loop gives:

IshRsh + (jωLg,sh)Ig − (jωLsh)Ish − (jωLsh,r)Ir = 0. Solving for Ish gives

+jω(Lg,shIg + Lsh,rIr) Ish = . (2.84) Rsh + jωLsh

Next, KVL around the receptor loop gives: IrRNE −(jωLgr)Ig −(jωLsh,r)Ish +(jωLr)Ir +IrRFE = 0 ind ind − where VNE = IrRNE and VFE = IrRFE. Solving for Ir gives:

jω(LgrIg + Lsh,rIsh) Ir = . (2.85) RNE + RFE + jωLr

Next, substituting (2.84) into (2.85) gives

[ ] jω LgrIg(Rsh + jωLsh) − jωLsh,r(Lg,shIg + Lsh,rIr) Ir = . (2.86) RNE + RFE + jωLr Rsh + jωLsh

Rearranging then gives:

[ ] 2 jω Ig(LgrRsh + jωLshLgr − jωLsh,rLg,sh) + jω(Lsh,r) Ir Ir = . (2.87) RNE + RFE + jωLr Rsh + jωLsh

Now assume we have a uniform current distribution along the conductors in Fig. 43. This then gives Lgr ≈ Lg,sh and Lsh ≈ Lsh,r. Rearranging (2.87) and substituting in the above assumptions gives:

[ ] [ ] 2 (ωLsh,r) jωLgrRsh Ir 1 + = Ig . (2.88) [RNE + RFE + jωLr][Rsh + jωLsh] [RNE + RFE + jωLr][Rsh + jωLsh]

Solving for Ir gives

jωIgLgrRsh Ir = 2 . (2.89) [RNE + RFE + jωLr][Rsh + jωLsh] + (ωLsh,r)

2 Next, if we denote the denominator of (2.89) at DEN = [RNE +RFE +jωLr][Rsh +jωLsh]+(ωLsh,r)

36 and assume that Lr ≈ Lsh ≈ Lsh,r then DEN simplifies to DEN = (RNE +RFE)Rsh +jωLsh[RNE +

RFE + Rsh]. Next, if we assume that RNE + RFE >> Rsh then (2.89) simplifies to

+jωIgLgrRsh Ir ≈ . (2.90) (RNE + RFE)(Rsh + jωLsh)

Vs Using Ig ≈ Ig(DC) = . This then gives the following expressions for the near- and far-end Rs+RL voltages in Fig. 43:

[ ][ ] R R ind − ≈ NE sh VNE = RNEIr (jωLgrIg(DC)) (2.91) RNE + RFE Rsh + jωLsh and [ ][ ] −R R ind ≈ FE sh VFE = RFEIr (jωLgrIg(DC)) . (2.92) RNE + RFE Rsh + jωLsh

The [ ] R sh (2.93) Rsh + jωLsh term in (2.92) is referred to as the Shield Factor (SF). This term is the same in both (2.91) and

(2.92). Also note that

Rsh 1 SF = = L . (2.94) Rsh + jωLsh 1 + jω sh Rsh This then implies:   1 if ω << Rsh/Lsh SF = (2.95)  Rsh/jωLsh if ω >> Rsh/Lsh

What we see from (2.95) is that the shield has no effect on the coupling caused by the mutual inductance at low frequencies. The voltage w.r.t. frequency caused by mutual inductance is plotted in Fig. 27. We can see that the shield for the inductive coupling starts to reduce V ind at approximately Rsh/Lsh. Therefore, the shield grounded at one end does not improve the inductive crosstalk. To do this we need to ground the shield at both ends. However, shields grounded at both ends are susceptible to ground loop problems.

37 |V ind |

Low frequency (response with the shield grounded on High frequency one end)

20 dB/decade

ω ω ≅ Rsh /L sh Figure 27. Induced voltage caused by inductive coupling.

2.5.3. Summary of transmission line coupling equations Without a shield

For capacitive coupling without a shield we have the following equations:

cap cap ≈ VNE = VFE jωCgrVinR. (2.96)

For inductive coupling without a shield we have the following equations:

−R ind ≈ NE VNE jωLgr Ig(DC) (2.97) RNE + RFE and R ind ≈ FE VFE jωLgr Ig(DC) (2.98) RNE + RFE where Ig(DC) = Vs/(Rs + RL). Then to compute both the inductive and capacitive coupling between TLs without a shield we use the following expressions: ( ) VNE ind cap = jω MNE + MNE (2.99) Vs

38 and ( ) VFE ind cap = jω MFE + MFE (2.100) Vs where

ind RNE Lgr MNE = , (2.101) RNE + RFE Rs + RL

ind RFE Lgr MFE = (2.102) RNE + RFE Rs + RL and cap cap || RLCgr MNE = MFE = (RNE RFE) . (2.103) Rs + RL

Next, if we include the common impedance noise voltage (these expressions are valid with or without a shield) we have: ( ) VNE ind cap ci = jω MNE + MNE + MNE (2.104) Vs and ( ) VFE ind cap ci = jω MFE + MFE + MFE (2.105) Vs where

ci RNE Ro MNE = (2.106) RNE + RFE Rs + RL and R R ci − FE o MFE = . (2.107) RNE + RFE Rs + RL

With a shield

For capacitive coupling with a shield we have the following equations:

cap cap ≈ VNE = VFE jωRCgrVg(DC). (2.108)

For inductive coupling with a shield we have the following equations:

[ ] − ind RNE VNE = jωLgrIg(DC) SF (2.109) RNE + RFE

39 and [ ] ind RFE VFE = jωLgrIg(DC) SF (2.110) RNE + RFE where

Rsh 1 SF = = L . (2.111) Rsh + jωLsh 1 + jω sh Rsh This then implies:   1 if ω << Rsh/Lsh SF = (2.112)  Rsh/jωLsh if ω >> Rsh/Lsh

Then to compute both the inductive and capacitive coupling between TLs with a shield we use the following expressions: ( ) VNE ind cap = jω MNE + MNE (2.113) Vs and ( ) VFE ind cap = jω MFE + MFE (2.114) Vs where − ind RNE Lgr MNE = SF, (2.115) RNE + RFE Rs + RL

ind RFE Lgr MFE = SF (2.116) RNE + RFE Rs + RL and cap cap || RLCgr MNE = MFE = (RNE RFE) . (2.117) Rs + RL

2.6. Twisted pair The next TL coupling problem investigated is the twisted pair problem shown in Fig. 28. The problem consists of two conductors twisted together in the presence of a single conductor carrying a e current IG. In this problem there exist capacitive and inductive coupling between the twisted pair and the single conductor. To represent this coupling, we define the equivalent circuit shown in Fig.

29. We will evaluate this equivalent circuit to understand how the twisted affect of the wire can reduce the inductive coupling. For this investigation we have two possible loading configurations:

40 Coupling magnetic fields

IG

Figure 28. Twisted pair coupling problem.

LHT

+ - + -

E1 = jωlgr 1LHT Ig E1 = jωlgr 1LHT Ig

RNE RFE

E2 = jωlgr 2LHT Ig E2 = jωlgr 2LHT Ig

+ - + -

I1 = jωcgr 1LHT Vg I2 = jωcgr 2LHT Vg I1 = jωcgr 1LHT Vg I2 = jωcgr 2LHT Vg

Ground reference Figure 29. Equivalent circuit of the twisted pair coupling problem.

1) Balanced configuration - both wires have the same impedance to ground.

2) Unbalanced configuration - both wires do not have the same impedance to ground.

The ind./cap. model used to investigate the crosstalk in the twisted pair will depend on how the ground is connected (i.e., if a balanced or unbalanced system is used). First, if we assume an unbalanced system we get the equivalent circuits in Figs. 30 and 31. The model in Fig. 30 represents the inductive coupling and the model in Fig. 31 represents the capacitive coupling.

2.6.1. Inductive coupling - unbalanced

When evaluating the equivalent circuit in Fig. 30 using KVL we get the following equation: e e e e E1 + E2 − E1 − E2 = 0. This shows that for each unit of twisted wires along the twisted pair cable,

41 we have a zero-sum value for the KVL analysis of each twist. This indicates that the inductive coupling between the single wire and the twisted pair in Fig. 28 is almost zero or negligible. This then tells us that twisted pair is useful when it is desired to reduce the crosstalk due to inductive coupling.

+ - + - +

E1 = jωlgr 1LHT Ig E2 = jωlgr 2LHT Ig IND RNE VNE RFE

E2 = jωlgr 2LHT Ig E1 = jωlgr 1LHT Ig - + - + -

Figure 30. Equivalent circuit for the inductive coupling in the twisted pair coupling problem.

2.6.2. Capacitive coupling - unbalanced

Next, for the capacitive coupling we consider the equivalent circuit in Fig. 31. If we assume that the twisted pair is tight, then we can assume the the following: cgr1 ≈ cgr2. This assumption states that the capacitive between the generator in Fig. 28 and both of the conductors in the twisted pair are the same. This then reduces the circuit in Fig. 31 to the circuit in Fig. 32. We can then write the near-end and far-end voltage as

CAP ≈ || VNE jωcgr1LHT NT Vg(DC)RNE RFE (2.118) or CAP ≈ T || VNE jωCgr1Vg(DC)RNE RFE (2.119)

T where LHT is the length of the full-twist, NT is the number of twists and Cgr1 = cgr1LHT NT . Therefore, using a twisted pair with unbalanced grounding reduces V IND but not V CAP . Finally, in general we have

R [ ] ≈ NE − T || VNE jω(lgr1 lgr2)LHT I(DC) + jωCgr1Vg(DC)RNE RFE. (2.120) RNE + RFE

42 +

CAP RNE VNE RFE

-

I2 = jωcgr 2LHT Vg I1 = jωcgr 1LHT Vg I1 = jωcgr 1LHT Vg I2 = jωcgr 2LHT Vg

Figure 31. Equivalent circuit for the capacitive coupling in the twisted pair coupling problem.

+

CAP RNE VNE 2I 1 RFE

-

Figure 32. Reduced equivalent circuit for the capacitive coupling in the twisted pair coupling problem.

2.6.3. Balanced case

For this section we look at the balanced case (Fig. 33). The equivalent circuit for capacitive coupling for this case is shown in Fig. 34. The inductive coupling is the same as for the unbalanced case. We can see that the near-end voltage is zero for an even number of twists and close to zero for an odd number of twists. Therefore, for the balance case the capacitive coupling is essential zero. In summary, if possible it is best to use the twisted pair in a balanced case because both the inductive and capacitive coupling is minimized.

RNE /2 RFE /2

RNE /2 RFE /2

Figure 33. The twisted pair coupling problem with a balanced load.

43 { 0 for an even number of twists E1-E 2 for an odd number of twists

+ - + RNE /2 RFE /2

CAP VNE

RFE /2 RNE /2 -

N(I1+II2) N(I1+II2)

Figure 34. The equivalent circuit for the capacitive coupling in the twisted pair coupling problem with a balanced load.

44 CHAPTER 3. DESIGNING FOR EMC

3.1. Components 3.1.1. Conductors

From chapter 1 we know that the capacitance between two parallel plates with area S is

C = ε0S/d where ε0 is the permittivity of the material between the plates and d is the separation of the two parallel plates. It can also be shown that the capacitance between the two parallel wires in Fig. 9 a) is C = πε/ ln(d/a) and the capacitance between the wire and the ground plane in Fig. 9 b) is C = 2πε/ ln(2h/a). It can also be shown that the external inductance of the wire ≈ µ above the ground plane in Fig. 9 b) is Lext 2π ln(2h/a) H/m. Since we have LextC = µε then C = µε = 2πε/ ln(2h/a) F/m. Lext Next, we want to calculate the external inductance of the rectangular conductor in Fig. 35. The following can be shown:   ( )  2πh 5 ln w nH/in, w << 2h and t<

Next, it can be shown that the external inductance of the square conductors in Fig. 36 is

(πh) L ≈ 10 ln nH/in. (3.2) ext w

The DC resistance can also be shown to be

L R = (3.3) dc σS where L is the length of the conductor, σ is the conductivity of the conductor and S is the cross- sectional area for a round wire.

3.1.2. Skin depth

Next we introduce the concept of skin depth. To illustrate this consider the electric field

45 Rectangular w conductor t

h

Ground plane Figure 35. A single rectangular conductor over a ground plane.

Rectangular w conductor t

h

Rectangular w conductor t Figure 36. Two rectangular conductors in free-space. impinging on the material in Fig. 37. We define the skin depth as the value of δ such that e−αδ = e−1. Solving for δ gives (for a good conductor)

1 1 δ = = √ . (3.4) α πfµσ

3.1.3. AC parameters Using the definition of skin depth in 3.4 results in the following AC resistance for a conductors:

L R ≈ (3.5) AC σ(2πaδ) where L is the length of the conductor and a is the radius of the conductor. We can also write the

46 Eo (amplitude)

Envelope of e−α z 1/e Impinging βz electric field δ

(air) (material)

Figure 37. Definition of skin depth.

AC resistance in terms of the DC resistance. This then gives

√ RAC = [0.096(2a) f + 0.26]RDC Ω/in. (3.6)

For wires or conductor with different shapes, we can define an equivalent diameter of the conductor in the following manner: perimeter of cross − section d = . (3.7) π

In a similar manner, we can define the AC inductance as:

√ 2δ 1 µ L ≈ L = H/m (3.8) int,AC a int,DC 4πa πσf

where Lint,DC = µ/(8π). 3.1.4. Non-ideal capacitors

If current flows through a real conductor, then we are guaranteed to have inductance and resistance. If we have more than one conductor at different potentials, we are guaranteed to have capacitance. With this in mind, we will investigate non-ideal components. The first is the capacitor.

47 The impedance of a non-ideal capacitor is shown in Fig. 38. We can see that the “real” (non-ideal) capacitor behaves similar to an ideal capacitor up to a resonant point. Then the inductance of the component begins to dominant. This behavior leads to the equivalent circuit in Fig. 39. If R2 is neglected, then Z = R + j(ωL − 1/(ωC)). This then gives f = √1 . o 2π LC

|Z c|

20 dB/decade looks like an inductor

looks like a capacitor

R1 f fo Figure 38. Impedance of a non-ideal capacitor.

Leakage resistance (often neglected) R2

L R1

Due to conductors{ on leads C Figure 39. Equivalent circuit of a non-ideal capacitor.

3.1.5. Non-ideal resistors

There are three different types of resistors:

1) Composition - the inductance is very small.

2) Film type - the inductance is moderate - has some effect.

3) Wirewound - the inductance is very significant but can dissipate several Watts of power. The impedance of a typical non-ideal resistor is shown in Fig. 40. The equivalent circuit is shown in Fig. 41.

48 |Z r|

f fo Figure 40. Impedance of a non-ideal resistor.

C

L R

Figure 41. Equivalent circuit of a non-ideal resistor.

3.1.6. Non-ideal inductors

There are four types of inductors:

1) Wound on an open core (Fig. 42 a)):

a) permeable core - iron, etc. b) non-permeable material as core (wood, air, .etc)

2) Wound on a closed core (Fig. 42 b)):

a) permeable core - iron, etc.

b) non-permeable material as core (wood, air, .etc) We summarize the behavior of open- and closed-core inductors in the following table (1 is the worst and 4 is the best):

49 AIR cause of radiated emissions susceptible to radiated fields

open core 1 2

close core 3 4

MAGNETIC

open core 2 1 closed core 4 3

a) b) Figure 42. a) Open core inductor and b) closed core inductor.

One other aspect to consider is don’t pass to much current such that the inductor saturates.

The impedance of a typical non-ideal inductor is shown in Fig. 43. The equivalent circuit is shown in Fig. 44.

|Z L|

f Figure 43. Impedance of a non-ideal inductor.

3.2. Ferrite Beads

50 C

L R

Figure 44. Equivalent circuit of a non-ideal inductor.

Ferrite beads are a very useful tool for suppressing EMI in a system. Ferrite beads can be used to provide some impedances that can be used for high-frequency filtering (Fig. 45). To avoid saturation of ferrite beads, one may use some “rules of thumb,” such as:

1) onset of saturation is when

Ibead = 10Ri (3.9)

where Ri is the inner radius of the bead (in cm). 2) full saturation when

Ibead ≥ 10Ro (3.10)

where Ro is the outer radius of the bead (in cm).

Equivalent circuit Insert ferrite bead for filtering Signal line Noise on the line Capacitor for filtering signal line

Figure 45. Noise on a circuit.

3.3. Grounding

There are two main types of grounding. One for safety and one for signals. We can think of a ground for signals (or the signal ground) as

51 1) a place for source/sink of charge 2) a return path for current

3) a common reference points

4) a zero potential point

5) earth.

In this section, we will think of the signal ground as a return path for current. 3.3.1. 3-types of (signal) ground systems

The three main types of grounding are listed below:

1) A single-point ground

a) series connection (Fig. 46) or a daisy chain.

b) parallel connection (Fig. 47).

Source

1 2 3

I1 I2 I3 Z1 A Z2 B Z3 C

Ground Figure 46. Series connection.

Source

1 2 3

I1 I2 I3 B A C Z2

Z1 Z3 Ground Figure 47. Parallel connection.

52 For the series connection in Fig. 46 we have the following node voltage values

VA = Z1(I1 + I2 + I3)

VB = VA + Z2(I2 + I3)

VC = VB + Z3I3.

For the parallel connection in Fig. 47 we have

VA = Z1I1

VB = Z2I2

VC = Z3I3.

When comparing these node voltages to the node voltages for the series connection we can see that from a noise perspective a parallel connection is more desirable for low frequencies. This is because a parallel ground connection has no common impedance coupling.

2) A multi-point ground

A multi-point ground is shown in Fig. 48. This is very useful at high frequencies because this kind of grounding minimizes the capacitance between ground leads. The effect of inductance of your ground system is minimized at high frequencies.

Source

1 2 3

I1 I2 I3

Ground Figure 48. Multi-point connection.

53 3) Hybrid ground This system is shown in Fig. 49. This system may be a single point ground over one frequency range and a multi-point ground system over another frequency range.

Shield

Source

Ground Figure 49. Hybrid connection.

3.3.2. EMC grounding philosophy 1) Think of grounding as the closing of current loops.

2) Close current loops as compactly and locally as possible (including parasitic currents).

a) prevent external ground currents from flowing through your circuit.

b) provide known paths (that do not use external conductors) for your ground currents. 3) Limit currents to and from mother earth as much as possible.

a) use single point connection to AC power ground.

b) if single point AC power ground is not possible, use circuitry that can reject ground noise.

3.3.3. Examples of cable grounding

If we have a grounded load and an ungrounded source then where do we connect our shield? Connect the shield to the common of the load.

If we have a grounded source and an ungrounded load, then were do we connect our shield?

Connect the shield to the common of the source.

How do we minimize the effect of ground loops? 1) lift the ground at one end - if possible.

2) minimize the distance from the source to the load.

3) transformer couple the source to the load.

54 4) optically couple the source to the load. 5) use hybrid grounds.

6) use common mode chokes.

3.3.4. The 2-types of current in EMC

The two types of current typically investigated in EMC are:

1) common mode currents which are currents that flow in the same direction (Fig. 50). 2) differential mode currents which are the intended currents that flows in the opposite direction (Fig. 50).

3.3.5. Common-mode choke

We can see that if the turns of the common-mode choke in Fig. 51 are the same for each wire and that the flux Ψ perfectly links the other windings, then the total flux in the core as a result of differential mode currents is zero. Thus, the choke will not have any effect on the differential mode current. On the other hand, if common mode currents are present on the conductors, then the flux in the core created by these currents adds together in the core. And since inductance is the ratio of the flux Ψ to the current creating the flux, the choke is introducing an inductance to the common mode currents and essentially choking off the common mode current. In other words, the differential mode current does not “see” an impedance in the core but the common mode current is experiencing an inductance (or impedance).

Differential-mode Common-mode current Total current current

IC ID I1

circuit 1 IC I2 ID circuit 2

Total current

VG

Figure 50. Examples of common and differential mode currents.

55 differential-mode currents common-mode currents ψ D ψC

ID IC

ID ψ IC D ψC

Figure 51. Illustration of a common mode choke.

3.3.6. Balanced circuits

Another method to reduce common mode current is to design a balanced circuit (if possible).

Consider the problem in Fig. 52. The original problem has two conductors connecting circuit 1 to circuit 2. In this example, the two references for each circuit are not at the same potential and vary by a voltage denoted as VG. Because of this voltage VG, the return current through the conductors

(denoted as IN1 and IN2) travel in the same direction down each conductor. This then results in common mode currents. This then results in a noise voltage of

RL VN = VG . Rs + RL

We want to eliminate VN . One way to do this is to design the balanced circuit in Fig. 53. In this balanced case, the load resistor is split into two equal values. This then results in IN1 and IN2 traveling through each resistor in opposite directions. Thus, the resulting noise voltage VN is zero

RL − because VN = 2 (IN2 IN1) = 0 if IN1 = IN2 (perfect balance).

circuit 1 circuit 2 + Rs IN1 VN RL Vs -

IN2 VG

Figure 52. An unbalanced circuit with common-mode currents.

56

Rs/2 -

IN1 RL/2 Vs/2

VN

Vs/2 RL/2

IN2 +

Rs/2

VG

Figure 53. A balanced circuit eliminating common-mode currents.

3.4. Filtering 3.4.1. Introduction to insertion loss

When we discuss EMC filtering we need to be mindful of both emissions (filtering to prevent our noise form leaving) and immunity or susceptibility (filtering to protect our system from external noise). We need to think of both differential mode filtering and common mode filtering. The insertion loss (IL) is the figure of merit commonly used to gauge the effectiveness of a filter. Consider the IL of the filter in Fig. 54. The insertion loss is defined as:

PR(ref) VR(ref) IL = 10 log = 20 log (3.11) PR VR

where PR(ref) or VR(ref) refer to the power or voltage at the load without the filter in place.

Zs + + Filter R Vs Vin V ZR - -

Figure 54. Insertion loss of a filter.

3.4.2. Insertion loss example of a capacitor

In this example, we want to calculate the IL of a capacitor. To do this, consider the example

57 [ ]

ZR in Fig. 55. This then gives VR(ref) = Vs and ZR+Zs

[ ] ZR||ZL VsZR VR = Vs = . Zs + ZR||ZL (ZR + Zs) + jωC(ZsZR)

This then gives an IL of

VR(ref) IL = 20 log VR

ZR ZR + Zs + jωCZsZR = 20 log ZR + Zs ZR

jωCZsZR = 20 log 1 + √ Zs + ZR = 20 log 1 + (ωτ)2

where τ = C(Zs||ZR). The IL is plotted in Fig. 56.

Zs + +

Vs Vin C VR ZR - - Figure 55. Insertion loss of a capacitor example.

IL (dB)

20 dB/decade

ω ωτ = 1 Figure 56. Insertion loss of a capacitor.

3.4.3. Differential- and common-mode filters A differential mode filter is what you normally think of when you decide to design a filter. An illustration of a differential-mode filter is in Fig. 57. A common mode filter is slightly different. An

58 illustration of a common-mode filter is in Fig. 58. The differential-mode filter supports differential- mode currents while a common-mode filter is forced to use common-mode currents. Therefore, a common mode filter may only affect the common-mode operation of a circuit. Several more examples of common mode filters are shown in Fig. 59.

V0 Filter

ground Figure 57. Differential-mode filter.

Filter V0

Figure 58. Common-mode filter.

M

Figure 59. Examples of common-mode filters.

59 3.4.4. Designing maximally flat Butterworth filters In this section we want to design maximally flat butterworth filters (as one example of differential-mode filter design). Several examples of the I.L. for various filters are shown in Fig. 60.

There are 4-steps in designing butterworth filters:

1) provide specs (N dB/dec, HP, LP, BP, etc.)

2) design low frequency prototype 3) use frequency and impedance scaling to the desired problem

4) implementation (testing, simulation, etc.)

I.L. I.L. Low-pass High-pass

3 dB point 3 dB point ω ω fc fc

I.L. I.L. Band-pass Band-stop

3 dB point 3 dB point ω ω fcL fcU fcL fcU Figure 60. The I.L. of four typical filter responses.

3.4.5. Low-pass filter design There are two types of low frequency prototypes. Both are shown in Fig. 61. The prototype in Fig. 61 will be used in conjunction with the table in Fig. 62. From the list above, we need to define how many dB/dec of I.L. we want from our filter. Each element in the prototypes in Fig.

61 insert 20 dB/dec of I.L. (this was shown for a capacitor in a previous section). Therefore, if we want 60 dB/dec of I.L., we need three elements in our prototype design. Next, we choose the

60 appropriate low frequency prototype in Fig. 61 and determine the values of An. This is done by using the table in Fig. 62. The first step when using the tables is to calculate Rs/RL and RL/Rs where Rs is the source resistance and RL is the load resistance. Then use these values in the second column to determine the least number of elements and the values of An (we will do an example shortly). The next step is to then use frequency and impedance scaling to design the appropriate

filter. The cut-off frequency for the prototype filter is ωp = 1 rad/s and the normalized prototype load is RL,p = 1. Next, the following LP frequency scaling functions are used to determine the final LP filter design: C C = p (3.12) ωcRL and R L L = L p (3.13) ωc where Cp, Lp are prototype values from the table in Fig. 62, C,L are the final values of the circuit,

RL is the actual load resistor and ωc = 2πfc is the desired radian cutoff frequency. It should also be noted that frequency scaling functions will be introduced to convert the prototype filter to LP,

HP and BS filters.

Rs A2 A4 RL A1 A3 Vs

Rs A1 A3

RL A2 A4 Vs

Figure 61. Low frequency prototypes for butterworth filters.

61 Figure 62. Design tables for butterworth filters.

62 3.4.6. LP Butterworth filter example

For this example we want to design a low-pass filter with Rs = 100Ω, RL = 50Ω, fc = 50MHz and an I.L. of 60 dB/dec in the stop band. In particular, we want a differential mode filter

(maximally flat response). This then gives Rs/RL = 2 and RL/Rs = .5. Using the least number of elements and the table in Fig. 62 we get n = 3 and A1 = 1.181, A2 = .779 and A3 = 3.261. This then results in the prototype in Fig. 63. Next, using the frequency scaling functions in (3.12) and (3.13) results in the final circuit shown in Fig. 64.

Rs = 2 A1 = 1.181 A3 = 3.261 RL= 1 Vs A2 = .779

Figure 63. Low-frequency LP prototype.

Rs = 100 .118 µH .519 µH RL= 50 Vs 49.6 pF

Figure 64. Final LP filter design.

3.4.7. High-pass filter design In this section we derive LP to HP filter transformations. To illustrate these expressions we need to consider the responses in Fig. 65. If we use the transformation ωp = −ωc/ω or ω = −ωc/ωp where ωc is the radian cut-off frequency of the HP response - we will transform the LP prototype response to the desired HP response. Thus, as

+ ωp → 0 ⇒ ω → −∞

− ωp → 0 ⇒ ω → ∞

ωp → 1 ⇒ ω → −ωc

ωp → −1 ⇒ ω → +ωc.

63 ⇒ This then gives ( ) −ω 1 1 jω L → j c L = = p p ω p jω 1 jωC ωcLp where C = 1/(ωcLp). Therefore, replace the prototype inductors (Lp) with capacitors of value

1 C = . (3.14) ωcLp

And similarly replace the prototype capacitors (Cp) with

1 L = . (3.15) ωcCp

When including the impedance scaling values we have

1 C = (3.16) RωcLp and R L = . (3.17) ωcCp

IL IL

− + ωp = 0 ωp = 0 ωp ωp ωp = 1 −ω c ωc

Low-pass response High-pass response (prototype) Figure 65. IL of LP- and HP-prototype filters.

3.4.8. HP Butterworth filter example

A circuit monitoring a 30 MHz signal is being interfered with by low frequency noise. We

64 want a HP filter with fc = 10 MHz and 80 dB/dec in the stop band. If Rs = 100, RL =50, then design a HP filter with the listed specs.

Since we need 80 dB/dec. we need four elements. Again, Rs/RL = 2 and RL/Rs = .5. This then gives A1 = .218, A2 = 2.452, A3 = .883 and A4 = 3.187. This then results in the LP prototype circuit in Fig. 66. The final HP filter is shown in Fig. 67.

2 2.452 3.187 .218 .883 1 Vs

Figure 66. Low-frequency LP prototype.

129.8 pF 99.9 pF

100 50 Vs 3.65 µH .9 µH

Figure 67. Final HP filter design.

3.4.9. Band-pass filter design

In this section we introduce the design of BP filters. To do this, consider the illustration in

Fig. 68. The prototype frequency ωp can be mapped to the frequency for the BP filter as

IL IL

3 dB 3 dB

ωp ωp 1 −ω 2 −ω 0 −ω 1 ω1 ω0 ω2

Low-pass response (prototype) Band-pass response Figure 68. IL of LP- and BP-prototype filters.

65 ( ) ω ω ωo ωp = − . ω2 − ω1 ωo ω

This then gives ( ) √ ( ) ω − ω ω − ω 2 ω = ω 2 1 ± ω2 2 1 + ω2. p 2 p 2 o √ 2 We usually simplify this by assuming ωo = ω1ω2 ⇒ ω = ω1ω2. Then

( ) √ ω − ω 1 ω = ω 2 1 ± ω2(ω − ω )2 + 4ω ω . p 2 2 p 2 1 1 2

− − If we say ∆ = ω2 ω1 = f2 f1 where ∆ is the fractional BW then our transformation is ωo fo ( ) 1 ω ωo ωp = − . ∆ ωo ω

This then gives

[ ( ) ] 1 ω ωo jωLp jωoLp jωLp → j − Lp = − ∆ ωo ω ∆ω(o )∆ω L 1 = jω p + ( ). ∆ω o jω ∆ ωoLp

Note that the term ( ) L jω p ∆ωo and (1 ) jω ∆ ωoLp can be written as

BP jωLL and 1 BP jωCL 66 BP BP where LL = Lp/(∆ωo) and CL = ∆/(ωoLp). Therefore, we can replace a LP prototype inductor

BP BP with a series inductance and capacitance with values LL and CL respectively. An illustration of this is shown in Fig. 69. Therefore, including frequency scaling we have

BP RLp LL = (3.18) ∆ωo and

BP ∆ CL = . (3.19) ωoLpR

Finally, we replace the capacitors with the parallel LC circuit shown in Fig. 70. To compute the equivalent values we use:

BP ∆R LC = (3.20) ωoCp and

BP Cp CC = . (3.21) ∆ωoR

BP BP CL Lp LL

Figure 69. LP- to BP- inductor element substitution

BP CC

Cp

BP LC Figure 70. LP- to BP- capacitor element substitution

Finally, to pick the number of elements needed for the LP prototype we have the following relation: BW f = . (3.22) BWc fc

67 The values of BW and BWc are shown in Fig. 71. The value of BWc is the BW desired at the center frequency fc and the value of BW is the bandwidth at another frequency f where this other frequency value is associated with more IL past the 3 dB cutoff. Then (3.22) along with the chart shown in Fig. 72 will be used to determine the number of elements needed in the LP prototype

filter design.

I.L. Band-pass

BW BW c 3 dB point

ω fcL fcU Figure 71. BW definitions for a BP-filter.

3.4.10. BP Butterworth filter example one

For this example we want to determine how many elements are needed for a filter with a 3dB

BW of 2 MHz and 40 dB of IL at a BW of 6 MHz. To determine how many elements we need in our LP-prototype example we calculate

f 6MHz = = 3. fc 2MHz

Then using the chart in Fig. 72 we can see that n = 4 or 5. We may need to try both and simulate the resulting filter to determine if the requirements are met.

68 Figure 72. I.L. requirements for BP- and BS-butterworth filters.

69 3.4.11. BP Butterworth filter example two For this example we want to design a BP filter with a center frequency of 75 MHz with a 3 dB BW of 7 MHz and an IL of 45 dB at a BW of 35 MHz. The source impedance is 50 Ω and the load impedance is 100 Ω. Again, using (3.22) we have

BW f 35MHz = = = 5. BWc fc 7MHz

From the chart in Fig. 72 we can see that we need at least 4 elements to provide 45 dB of IL. Next, calculating the impedance ratios: Rs/RL = .5 and RL/Rs = 2. Using the table in Fig. 62 gives

A1 = .218, A2 = 2.452, A3 = .883 and A4 = 3.187. This resulted in the prototype filter design shown in Fig. 73. Then, using the frequency and impedance scaling functions in (3.18)-(3.21) and substituting we get the final BP design show in Fig. 74.

A1 = .218 A3 = .883

Rs = .5

RL= 1 A2 = 2.452 A4 = 3.187 Vs

Figure 73. LP-prototype for the BP example.

.496 µH 9.086 pF 2 µH 2.24 pF

50 6.2 nH

Vs .557 nF 8.1 nH .72 nF 100

Figure 74. Final BP-filter circuit.

3.4.12. Band-stop filter design

In this section we introduce the band-stop filter design transformations. The desired insertion loss of a band-stop filter is shown in Fig. 60. The transformation involved with the LP prototype

filter is to first replace ωp with ∆ . ω − ωo ωo ω

70 this will then result in the following transformation equations for the prototype inductor:

BS Lp∆R LpBWR LL = = 2 (3.23) ωo 2πfo and

BS 1 1 CL = = (3.24) LpRωo∆ LpR2πBW where

ω2 − ω1 ∆ = = f2 − f1fo. ωo

Then the LP prototype inductor is replaced with the capacitor and inductor connected in parallel shown in Fig. 75. Next, the following transformation equations for the prototype capacitor can be written as:

BS R R LC = = (3.25) ωo∆Cp 2πBW Cp and

BS ∆Cp CpBW CC = = 2 . (3.26) Rωo R2πfo

The LP prototype capacitor is replaced with the capacitor and inductor connected in series shown in Fig. 76.

BS CL

Lp

BS LL Figure 75. LP- to BS- inductor element substitution

BS Cp BS CC LC

Figure 76. LP- to BS- capacitor element substitution

71 Finally, to pick the number of elements needed for the LP prototype we have the following relation: BW f = (3.27) BWc fc except the values of BW and BWc are defined slightly different in Fig. 77 for the BS-filter. Then (3.27) can be used in the chart in Fig. 72 to determine the number of elements for the filter design.

I.L. Band-stop

BW c

3 dB point BW ω fcL fcU Figure 77. BW definitions for a BS-filter.

72 CHAPTER 4. DIGITAL CIRCUITS

4.1. Noise When laying out a digital circuit, we want to minimize the noise caused by digital circuitry.

In analog circuits we are often working at lower voltage levels which means we have a much lower noise margin. With digital circuits, we are often working with much larger voltage levels. This often results in much higher radiated noise. To start our investigation on how to reduce the noise from digital circuits we start with the digital circuit in Fig. 78. The problem consists of four digital gates. When the output of gate 1 changes from a logic high to a logic zero, the stray capacitance needs to discharge before the input to gate 3 has a logic zero. This discharge happens through gate

1. The path the current takes is to ground, which is through the ground inductance. If the discharge is fast enough a voltage will be induced across the ground inductance. Thus, if gate 2 is at a logic 0, the reference for this logic 0 changes from 0V to some other voltage proportional to the induce voltage across the ground inductance. This then causes the output of gate 2 to rise momentarily above zero. If this rise is high enough, then a logic 1 may be interpreted by gate 4. This could change the output of gate 4. This wrong output is referred to as ground noise or switching noise.

Vcc

1 3

Cstray

Vcc

2 4

Ground inductance Idischarge

Figure 78. Noise in digital circuits.

We can minimize the effect of ground noise induced by parasitic capacitance by 1) reducing stray capacitance (short traces, reduce fan-out); 2) reducing ground inductance (provide return

73 path directly below signal line); 3) reduce voltage levels; 4) increase ∆ t. To minimize ground inductance we should use ground planes (if possible) or ground grids.

For the purposes of quick analysis of digital waveforms, we usually assume a trapezoidal wave

(Fig. 79). Next, we use the following equation when determining the max frequency of noise and radiation from digital circuits: 1 BW = (4.1) πtr

th where tr is the rise time defined in Fig. 79. The n harmonic of current is written as

sin(nπd) sin(nπtr/T ) In = 2dIpp (4.2) nπd nπtr/T where T is the period and d is the duty cycle.

Ipp t tr T Figure 79. Digital signal approximation.

4.2. Decoupling Capacitors

When the switching circuitry is far from the power supply and the power plane inductance is minimized, then we may provide a source of charge near the gates using decoupling capacitors. To illustrate a decoupling capacitor we consider the digital circuit in Fig. 80. Much of the information in this section comes from the paper “Power Bus Decoupling on Multilayer Printed Circuit Boards,” by T. H. Hubing, J. L. Drewniak, T. P. Van Doren and D. M. Hockanson, IEEE Transactions on

Electromagnetic Compatibility, Vol. 37, No. 2, May 1995, pp. 155-166. The voltage at the board can be written as: di V (t) = V (t) − (L + L ) . (4.3) board supply G P dt

Now suppose that we have Lp ≈ 10µH and Lg is negligible. If we have 300 mA in 1 µS, then

di ∆V = (LP + LG) dt = 3V . For this course, we usually assume a low frequency model for our problems. For this example, our low frequency model assumes that the inductance of the traces on

74 Circuit LP

+ + Cbulk = Cb supply Vboard - V -

LG Power Supply PCB Figure 80. Decoupling capacitor problem.

the PCB are negligible compared to LP and LG. Then we can calculate the Thevenin impedance of the circuit shown in Fig ??. This then gives

( )

1 Zth = jω(LG + LP ) (4.4) ȷωCb and ( 1 ) jωCb Vth = Vsupply 1 . (4.5) + jω(LP + LG) jωCb From (4.4) and (4.5) we can see that the supply voltage can have a significant impedance.

There are two ways to think about the role of decoupling capacitors: 1) In the time domain, the decoupling capacitors supply a source of charge for transient loads and 2) in the frequency domain, the decoupling capacitors provide a low impedance to the board to minimize ∆V . When implementing decoupling capacitors, there are a few key design rules to keep in mind for minimizing the inductance of the decoupling capacitors: 1) use short traces; 2) use surface mount parts; 3) be careful with the size of vias on multi-layer boards and 4) might use many capacitors in parallel, since L in parallel is reduced.

The following method is Dr. Jorgenson’s Method for choosing decoupling capacitors (both bulk decoupling and chip decoupling): → dV ⇒ If we are given Icc, rise time (tr) and frequency f or 1/f = tclock, then based on i = C dt dt C = i dV we have 0.7I t C = cc clock (4.6) bulk dV

75 and 0.2I t C = cc r . (4.7) chip dV

76