Gcc and Make Outline C and Java

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Outline

• We will look at the following software development tools: COMP 2718: § The gcc compiler § The make build tool (usually used for C/C++) Software Development § (later) The ant built tool (usually used for Java) Tools: • Along the way we’ll introduce some additional concepts: § Compiling and linking gcc and make § Object files • We will not focus on the actual programming language concepts,

Slides adapted by Andrew Vardy (Memorial University) but on the tools themselves. So don’t worry if you don’t know or Originally created by Marty Stepp, Jessica Miller, and Ruth Anderson (University of Washington) remember either Java or C/C++. http://www.cs.washington.edu/390a/

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C and Java

• We will discuss tools for software development, mostly with respect to C and Java • C is one of the most well-used programming languages § C++ is the object-oriented successor to C § Yet C continues to be used, particularly for embedded systems § C/C++ are compiled languages. The compiler generates a machine language executable program. • Java is also extremely popular and shares many of its object- oriented features with C++ § Java programs are compiled to Java bytecode (not machine language) § Java bytecode runs on a Java Virtual Machine (JVM) which can be implemented on a wide array of platforms according to the Java slogan: "Write once, run anywhere"

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Compiling: Java Compiling: C

• What happens when you compile a Java program? command description gcc GNU C compiler $ javac Example.java produces Example.class

Answer: It produces a .class file. • To compile a C program called source.c, type: gcc -o target source.c target § Example.java is compiled to create Example.class produces (where target is the name of the executable program to build) • How do you run this Java program? § the compiler builds an actual executable file (not a .class like Java) $ java Example § Example: gcc -o hi hello.c Compiles the file hello.c into an executable called “hi” • To run your program, just execute that file: § Example: ./hi

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Multiple Files Object files (.o)

• single-file programs do not work well when code gets large • A .c file can also be compiled into an object (.o) file with -c : § compilation can be slow $ gcc -c part1.c part1.o § hard to collaborate between multiple programmers $ ls produces § more cumbersome to edit part1.c part1.o part2.c

• larger programs are split into multiple files § a .o file is a binary “blob” of compiled C code that cannot be directly “ ” § each file represents a partial program or module executed, but can be directly inserted into an executable later § modules can be compiled separately or together § a module can be shared between multiple programs • You can compile a mixture of .c and .o files: $ gcc -o combined part1.o part2.c combined produces Avoids recompilation of unchanged partial program files (e.g. part1.o)

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Header files (.h) Compiling large programs

• header : A C file whose only purpose is to be #included (#include is • Compiling multi-file programs repeatedly is cumbersome: like java import statement) § generally a filename with the .h extension $ gcc -o myprogram file1.c file2.c file3.c § holds shared variables, types, and function declarations § similar to a java interface: contains function declarations but not • Retyping commands like this is wasteful: implementations § often the required compile command is much longer for larger projects • key ideas: § § every name.c intended to be a module (not a stand alone program) even if one file is changed (e.g. file3.c) all files need to be has a name.h recompiled; again this becomes really time consuming for larger § name.h declares all global functions/data of the module projects § other .c files that want to use the module will #include name.h • We’ll look at this through the following Running Example...

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------hello.c ------/* Classic "hello world" program, split into three .c files. */ Running Example #include "file2.h" Running Example #include "file3.h" #include

int main(void) { print_hello(); printf(" "); • We have three modules: hello, file2, file3 print_world(); printf("\n"); } • Two of the modules have both .h and .c files: file2, file3

------file2.h § These are intended to be used externally ------/* Print "hello". */ void print_hello(void); • The third module is the main program: hello

------file2.c § No .h file because this module is the main one, it pulls in file2 and file3 ------#include "file2.h" #include with include statements

void print_hello(void) { printf("hello"); • Simplest solution to compile is the following one-liner: } § ------gcc -o hello hello.c file2.c file3.c --- file3.h ------/* Print "world". */ • Using this one-liner we would have to re-compile if any file changes void print_world(void);

------• No intelligence built into this process; easy for mistakes to be made --- file3.c ------#include "file3.h" (e.g. file2.h is changed, but we forget to re-compile) #include

void print_world(void) { printf("world"); }

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Running Example make

• The following solution is a bit better: • make : A utility for automatically compiling ("building") executables § gcc -c hello.c and libraries from source code. •Generates hello.o § a basic compilation manager § gcc -c file2.c § often used for C programs, but not language-specific •Generates file2.o § primitive, but still widely used due to familiarity, simplicity § gcc -c file3.c § similar programs: ant, maven, IDEs (Eclipse), ... •Generates file3.o § gcc -o hello hello.o file2.o file3.o • Makefile : A script file that defines rules for what must be compiled •Generates hello executable and how to compile it. • Yes, this was more work to type, but the .o files can be separately § Makefiles describe which files depend on which others, and how to re-compiled if necessary create / compile / build / update each file in the system as needed. • Still it would be good to encode all of this in a script or something; Even better if files could be made to compile only when necessary

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Dependencies make Exercise

• dependency : When a file relies on the contents of another. • figlet : program for displaying large ASCII text (like banner). § can be displayed as a dependency graph § http://freecode.com/projects/figlet § to build main.o, we need data.h, main.c, and io.h § if any of those files is updated, we must rebuild main.o § if main.o is updated, we must update project1 • Download a piece of software and compile it with make: § download .tar.gz file § un-tar it § look at README file to see how to compile it § (sometimes) run ./configure •for cross-platform programs; sets up make for our operating system § run make to compile the program § (optional) run sudo make install to install on your system § execute the program

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Makefile rule syntax Running make target : source1 source2 ... sourceN $ make target command § uses the file named Makefilein current directory command ... § Finds a rule in Makefile for building target and follows it § source1 through sourceN are the dependenciesfor building •if the target file does not exist, or if it is older than any of its sources, target its commands will be executed § Make will execute the commands in order • variations: $ make Example: § builds the first target in the Makefile myprogram : file1.c file2.c file3.c gcc -o myprogram file1.c file2.c file3.c $ make -f makefilename $ make -f makefilename target this is a tab THIS IS NOT spaces!! § uses a makefile other than Makefile § The command line must be indented by a single tab •not by spaces; NOT BY SPACES! SPA CES WILL NOT WORK! 17 18

Making a Makefile Making a Makefile

• Here is a very simple makefile for our running example:

hello: hello.c file2.c file3.c gcc -o hello hello.c file2.c file3.c

• Its nice and short but notice that it is really just the same as our first gcc “one-liner”, only wrapped in the syntax of a makefile although it does have some advantages: § Documents build instructions § Will re-build hello if any of the .c files change (if make is called) • The disadvantage is that a change requires compilation of all files.

courtesy XKCD

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Separate Targets Rules with no dependencies

• Lets add multiple targets to our Makefile to build the .o files individually, then build the executable: clean: rm file1.o file2.o file3.o myprog hello: hello.o file2.o file3.o gcc -o hello hello.o file2.o file3.o • make assumes that a rule's command(s) will build/create its target hello.o: hello.c § but if your rule does not actually create its target, the target will still gcc -c hello.c not exist the next time, so the rule will always execute its commands (e.g. clean above) file2.o: file2.c gcc -c file2.c § make clean is a convention for removing all compiled files

file3.o: file3.c gcc -c file3.c • This is better because changing one file will not require complete recompilation

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Rules with no commands Variables all: myprog myprog2 NAME = value (declare) $(NAME) (use) myprog: file1.o file2.o file3.o Note that Makefile syntax is similar to bash syntax but also differs (e.g. spaces gcc -o myprog file1.o file2.o file3.o Example Makefile: allowed in variable assignment) myprog2: file4.c OBJFILES = file1.o file2.o file3.o gcc -o myprog2 file4.c PROGRAM = myprog ... $(PROGRAM): $(OBJFILES) gcc -o $(PROGRAM) $(OBJFILES) • all rule has no commands, but depends on myprog and myprog2 clean: § typing make all will ensure that myprog, myprog2are up to date rm $(OBJFILES) $(PROGRAM) § all rule often put first, so that typing make will build everything • variables make it easier to change one option throughout the file § also makes the makefile more reusable for another project

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Adding Features to Example More variables

OBJECTS = hello.o file2.o file3.o Example Makefile: PROG = hello Disadvantages of all: $(PROG) this version: OBJFILES = file1.o file2.o file3.o • Much longer! PROGRAM = myprog hello: $(OBJECTS) (we will fix this) CC = gcc gcc -o $(PROG) $(OBJECTS) CCFLAGS = -g -Wall Advantages: hello.o: hello.c • Vari abl es al l ow gcc -c hello.c customization $(PROGRAM): $(OBJFILES) • The clean target $(CC) $(CCFLAGS) -o $(PROGRAM) $(OBJFILES) file2.o: file2.c allows us to gcc -c file2.c start from a clean slate file3.o: file3.c gcc -c file3.c • many makefiles create variables for the compiler, flags, etc. clean: § this can be overkill, but you will see it "out there" rm -f $(OBJECTS) $(PROG)

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Special variables Auto-conversions

$@ the current target file • Rather than specifying individually how to convert every .c file into $^ all sources listed for the current target its corresponding .o file, you can set up an implicit target: $< the first (left-most) source for the current target # conversion from .c to .o Makefile comments! (there are other special variables*) .c.o: Example Makefile: gcc $(CCFLAGS) -c $< myprog: file1.o file2.o file3.o gcc $(CCFLAGS) -o $@ $^ § "To create filename.o from filename.c, run gcc -g -Wall -c filename.c"

file1.o: file1.c file1.h file2.h gcc $(CCFLAGS) -c $< • For making an executable (no extension), simply write .c : .c: gcc $(CCFLAGS) -o $@ $<

*http://www.gnu.org/software/make/manual/html_node/Automatic-Var iabl es.html #Automati c-Vari abl es

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Final Version of Example

OBJECTS = hello.o file2.o file3.o Nice features of PROG = hello this final version: • More compact all: $(PROG) than previous • Can be easily $(PROG): $(OBJECTS) customized for gcc -o $(PROG) $(OBJECTS) similar projects just by .c.o: modifying variables gcc -c $< clean: rm -f $(OBJECTS) $(PROG)