16 Investigation of Multiple-Valued Logic Technologies
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Magnonic Logic Circuits
IOP PUBLISHING JOURNAL OF PHYSICS D: APPLIED PHYSICS J. Phys. D: Appl. Phys. 43 (2010) 264005 (10pp) doi:10.1088/0022-3727/43/26/264005 Magnonic logic circuits Alexander Khitun, Mingqiang Bao and Kang L Wang Device Research Laboratory, Electrical Engineering Department, Focus Center on Functional Engineered Nano Architectonics (FENA), Western Institute of Nanoelectronics (WIN), University of California at Los Angeles, Los Angeles, California, 90095-1594, USA Received 23 November 2009, in final form 31 March 2010 Published 17 June 2010 Online at stacks.iop.org/JPhysD/43/264005 Abstract We describe and analyse possible approaches to magnonic logic circuits and basic elements required for circuit construction. A distinctive feature of the magnonic circuitry is that information is transmitted by spin waves propagating in the magnetic waveguides without the use of electric current. The latter makes it possible to exploit spin wave phenomena for more efficient data transfer and enhanced logic functionality. We describe possible schemes for general computing and special task data processing. The functional throughput of the magnonic logic gates is estimated and compared with the conventional transistor-based approach. Magnonic logic circuits allow scaling down to the deep submicrometre range and THz frequency operation. The scaling is in favour of the magnonic circuits offering a significant functional advantage over the traditional approach. The disadvantages and problems of the spin wave devices are also discussed. 1. Introduction interest in spin waves as a potential candidate for information transmission. The situation has changed drastically as the There is an immense practical need for novel logic devices characteristic distance between the devices on the chip entered capable of overcoming the constraints inherent to conventional the deep-submicrometre range. -
ERSFQ 8-Bit Parallel Arithmetic Logic Unit
1 ERSFQ 8-bit Parallel Arithmetic Logic Unit A. F. Kirichenko, I. V. Vernik, M. Y. Kamkar, J. Walter, M. Miller, L. R. Albu, and O. A. Mukhanov Abstract— We have designed and tested a parallel 8-bit ERSFQ To date, the reported superconductor ALU designs were arithmetic logic unit (ALU). The ALU design employs wave- implemented using RSFQ logic following bit-serial, bit-slice, pipelined instruction execution and features modular bit-slice ar- chitecture that is easily extendable to any number of bits and and parallel architectures. adaptable to current recycling. A carry signal synchronized with The bit-serial designs have the lowest complexity; however, an asynchronous instruction propagation provides the wave- their latencies increase linearly with the operand lengths, hard- pipeline operation of the ALU. The ALU instruction set consists of ly making them competitive for implementation in 32-/64-bit 14 arithmetical and logical instructions. It has been designed and processors [17], [18]. Bit-serial ALUs were used in 8-bit simulated for operation up to a 10 GHz clock rate at the 10-kA/cm2 fabrication process. The ALU is embedded into a shift-register- RSFQ microprocessors [19]-[24], in which an 8 times faster based high-frequency testbed with on-chip clock generator to allow internal clock is still feasible. As an example, an 80 GHz bit- for comprehensive high frequency testing for all possible operands. serial ALU was reported in [25]. The 8-bit ERSFQ ALU, comprising 6840 Josephson junctions, has In order to alleviate the high-clock requirements and long 2 been fabricated with MIT Lincoln Lab’s 10-kA/cm SFQ5ee fabri- latencies of bit-serial design while keeping moderate hardware cation process featuring eight Nb wiring layers and a high-kinetic inductance layer needed for ERSFQ technology. -
Japan's ERATO and PRESTO Basic Research Programs
Japanese Technology Evaluation Center JTEC JTEC Panel Report on Japan’s ERATO and PRESTO Basic Research Programs George Gamota (Panel Chair) William E. Bentley Rita R. Colwell Paul J. Herer David Kahaner Tamami Kusuda Jay Lee John M. Rowell Leo Young September 1996 International Technology Research Institute R.D. Shelton, Director Geoffrey M. Holdridge, WTEC Director Loyola College in Maryland 4501 North Charles Street Baltimore, Maryland 21210-2699 JTEC PANEL ON JAPAN’S ERATO AND PRESTO PROGRAMS Sponsored by the National Science Foundation and the Department of Commerce of the United States Government George Gamota (Panel Chair) David K. Kahaner Science & Technology Management Associates Asian Technology Information Program 17 Solomon Pierce Road 6 15 21 Roppongi, Harks Roppongi Bldg. 1F Lexington, MA 02173 Minato ku, Tokyo 106 Japan William E. Bentley Tamami Kusuda University of Maryland 5000 Battery Ln., Apt. #506 Dept. of Chemical Engineering Bethesda, MD 20814 College Park, MD 20742 Jay Lee Rita R. Colwell National Science Foundation University of Maryland 4201 Wilson Blvd., Rm. 585 Biotechnology Institute Arlington, VA 22230 College Park, MD 20740 John Rowell Paul J. Herer 102 Exeter Dr. National Science Foundation Berkeley Heights, NJ 07922 4201 Wilson Blvd., Rm. 505 Arlington, VA 22230 Leo Young 6407 Maiden Lane Bethesda, MD 20817 INTERNATIONAL TECHNOLOGY RESEARCH INSTITUTE WTEC PROGRAM The World Technology Evaluation Center (WTEC) at Loyola College (previously known as the Japanese Technology Evaluation Center, JTEC) provides assessments of foreign research and development in selected technologies under a cooperative agreement with the National Science Foundation (NSF). Loyola's International Technology Research Institute (ITRI), R.D. -
Arxiv:1611.03715V1 [Cs.OH] 25 Oct 2016
On the optimality of ternary arithmetic for compactness and hardware designI Harris V. Georgiou (MSc, PhD)1,1 aDepartment of Informatics & Telecommunications (DIT), National Kapodistrian University of Athens (NKUA/UoA), Greece Abstract In this paper, the optimality of ternary arithmetic is investigated under strict mathematical formulation. The arithmetic systems are presented in generic form, as the means to encode numeric values, and the choice of radix is asserted as the main parameter to assess the efficiency of the representation, in terms of information compactness and estimated implementation cost in hardware. Using proper formulations for the optimization task, the universal constant e (base of natural logarithms) is proven as the most efficient radix and ternary is asserted as the closest integer choice. Keywords: arithmetic systems, ternary arithmetic, computer technology 1. Introduction The term arithmetic system refers to the way a number is represented as a sequence of symbols associated with a specific power series. More specifically, a radix r is selected as the the base of the arithmetic system and every number is expressed as a sum of powers of this radix. As humans, we learn to count in the decimal arithmetic system, i.e., using powers of 10, purely for practical reasons. Children learn basic arithmetic by using their ten fingers, thus each time they count to 10, a carrier is created and added to the next power index. For example, the number 1,234 is actually a shortcut to the full representation: 3 2 1 0 arXiv:1611.03715v1 [cs.OH] 25 Oct 2016 123410 = 1 · 1:000 + 2 · 100 + 3 · 10 + 4 = 1 · 10 + 2 · 10 + 3 · 10 + 4 · 10 The proper representation of the number orders the coefficients for each radix power in left-to-right ranking and includes a subscript displaying the radix. -
A Stochastic-Computing Based Deep Learning Framework Using
A Stochastic-Computing based Deep Learning Framework using Adiabatic Quantum-Flux-Parametron Superconducting Technology Ruizhe Cai Olivia Chen Ning Liu Ao Ren Yokohama National University Caiwen Ding Northeastern University Japan Northeastern University USA [email protected] USA {cai.ruiz,ren.ao}@husky.neu.edu {liu.ning,ding.ca}@husky.neu.edu Xuehai Qian Jie Han Wenhui Luo University of Southern California University of Alberta Yokohama National University USA Canada Japan [email protected] [email protected] [email protected] Nobuyuki Yoshikawa Yanzhi Wang Yokohama National University Northeastern University Japan USA [email protected] [email protected] ABSTRACT increases the difficulty to avoid RAW hazards; the second is The Adiabatic Quantum-Flux-Parametron (AQFP) supercon- the unique opportunity of true random number generation ducting technology has been recently developed, which achieves (RNG) using a single AQFP buffer, far more efficient than the highest energy efficiency among superconducting logic RNG in CMOS. We point out that these two characteristics families, potentially 104-105 gain compared with state-of-the- make AQFP especially compatible with the stochastic com- art CMOS. In 2016, the successful fabrication and testing of puting (SC) technique, which uses a time-independent bit AQFP-based circuits with the scale of 83,000 JJs have demon- sequence for value representation, and is compatible with strated the scalability and potential of implementing large- the deep pipelining nature. Further, the application of SC scale systems using AQFP. As a result, it will be promising has been investigated in DNNs in prior work, and the suit- for AQFP in high-performance computing and deep space ability has been illustrated as SC is more compatible with applications, with Deep Neural Network (DNN) inference approximate computations. -
Nonconventional Computer Arithmetic Circuits, Systems and Applications Leonel Sousa, Senior Member, IEEE
1 Nonconventional Computer Arithmetic Circuits, Systems and Applications Leonel Sousa, Senior Member, IEEE Abstract—Arithmetic plays a major role in a computer’s basic levels and leads to high power consumption. Hence, performance and efficiency. Building new computing platforms the research on unconventional number systems is of the supported by the traditional binary arithmetic and silicon-based utmost interest to explore parallelism and take advantage of technologies to meet the requirements of today’s applications is becoming increasingly more challenging, regardless whether we the characteristics of emerging technologies to improve both consider embedded devices or high-performance computers. As a the performance and the energy efficiency of computational result, a significant amount of research effort has been devoted to systems. Moreover, by avoiding the dependencies of binary the study of nonconventional number systems to investigate more systems, nonconventional number systems can also support efficient arithmetic circuits and improved computer technologies the design of reliable computing systems using the newest to facilitate the development of computational units that can meet the requirements of applications in emergent domains. available technologies, such as nanotechnologies. This paper presents an overview of the state of the art in non- conventional computer arithmetic. Several different alternative computing models and emerging technologies are analyzed, such A. Motivation as nanotechnologies, superconductor devices, and biological- and quantum-based computing, and their applications to multiple The Complementary Metal-Oxide Semiconductor (CMOS) domains are discussed. A comprehensive approach is followed transistor was invented over fifty years ago and has played in a survey of the logarithmic and residue number systems, a key role in the development of modern electronic devices the hyperdimensional and stochastic computation models, and and all that it has enabled. -
Computer Aided Systems Theory – EUROCAST 2019
Remarks on the Design of First Digital Computers in Japan - Contributions of Yasuo Komamiya B Radomir S. Stankovi´c1( ), Tsutomu Sasao2, Jaakko T. Astola3, and Akihiko Yamada4 1 Mathematical Institute of SASA, Belgrade, Serbia [email protected] 2 Department of Computer Science, Meiji University, Kawasaki, Kanagawa 214-8571, Japan 3 Department of Signal Processing, Tampere University of Technology, Tampere, Finland 4 Computer Systems and Media Laboratory, Tokyo, Japan Abstract. This paper presents some less known details about the work of Yasuo Komamiya in development of the first relay computers using the theory of computing networks that is based on the former work of Oohashi Kan-ichi and Mochiori Goto at the Electrotechnical Laboratory (ETL) of Agency of Industrial Science and Technology, Tokyo, Japan. The work at ETL in the same direction was performed under guidance of Mochinori Goto. Keywords: Digital computers · Relay-based computers · Parametron computers · Transistorised computers · History · Arithmetic circuits 1 Introduction In the first half of the 20th century, many useful algorithms were developed to solve various problems in different areas of human activity. However, most of them require intensive computations, due to which their applications, espe- cially wide applications, have been suppressed by the lack of the correspond- ing computing devices. Even before that, already in late thirties, it was clear that discrete and digital devices are more appropriate for such applications that require complex computations. Therefore, in fifties of the 20th century, the work towards development of digital computers was a central subject of research at many important national level institutions. This research was performed equally in all technology leading countries all over the world, notably USA, Europe, and Japan. -
Theory, Synthesis, and Application of Adiabatic and Reversible Logic
University of South Florida Scholar Commons Graduate Theses and Dissertations Graduate School 11-23-2013 Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits For Security Applications Matthew Arthur Morrison University of South Florida, [email protected] Follow this and additional works at: https://scholarcommons.usf.edu/etd Part of the Computer Engineering Commons Scholar Commons Citation Morrison, Matthew Arthur, "Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits For Security Applications" (2013). Graduate Theses and Dissertations. https://scholarcommons.usf.edu/etd/5082 This Dissertation is brought to you for free and open access by the Graduate School at Scholar Commons. It has been accepted for inclusion in Graduate Theses and Dissertations by an authorized administrator of Scholar Commons. For more information, please contact [email protected]. Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits For Security Applications by Matthew A. Morrison A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Department of Computer Science and Engineering College of Engineering University of South Florida Major Professor: Nagarajan Ranganathan, Ph.D. Sanjukta Bhanja, Ph.D. Srinivas Katkoori, Ph.D. Jay Ligatti, Ph.D. Kandethody Ramachandran, Ph.D. Hao Zheng, Ph.D. Date of Approval: November 22, 2013 Keywords: Charge Based Computing, DPA Attacks, Encryption, Memory, Power Copyright © 2014, Matthew A. Morrison DEDICATION To my parents, Alfred and Kathleen Morrison, and to my grandparents, Arthur and Betty Kempf, and Alfred and Dorothy Morrison, for making all the opportunities I have possible. ACKNOWLEDGMENTS I would like to thank my advisor, Dr. -
Numbers and Calculators ARCHI 2019 Summit 2,397,824 Cores 2,801,664 GB Mem 200,795 Tflop/S
Numbers and Calculators ARCHI 2019 Summit 2,397,824 Cores 2,801,664 GB mem 200,795 TFlop/s 13,000,000 W 200,000,000 $ Summit MareNostrum P9 CTE 2,397,824 Cores 19,440 Cores 2,801,664 GB mem 27,648 GB mem 200,795 TFlop/s 1,018 TFlop/s 13,000,000 W 85,000 W 200,000,000 $ 34,000,000 € Summit MareNostrum P9 CTE 2,397,824 Cores 19,440 Cores 2,801,664 GB mem 27,648 GB mem Version N°3 200,795 TFlop/s 1,018 TFlop/s 38 PFlop/s 13,000,000 W 85,000 W 20 Watts 200,000,000 $ 34,000,000 € 30,000 € Summit MareNostrum P9 CTE 2,397,824 Cores 19,440 Cores 2,801,664 GB mem 27,648 GB mem Version N°3 200,795 TFlop/s 1,018 TFlop/s 38 PFlop/s 13,000,000 W 85,000 W 20 Watts 200,000,000 $ 34,000,000 € 30,000 € Outline 1.Analogic computation 2.Computer’s Zoo 3.A few words about gate 4.How to use transistors 5.Number’s representation Outline 1.Analogic computation 2.Computer’s Zoo 3.A few words about gate 4.How to use transistors 5.Number’s representation Numbers in continuous space: Analog computer • Uses continuous property of physical phenomena (electrical, mechanical, hydraulic) • Resilient to quantization noise But subject to physical noise (electronic, °C, …) • Can be more powerful than digital computer • Dominant in HPC until the 70s • Example: • Used for the Apollo 11 mission • Tide-Prediction machine (William & James Thomson) Alternatives to numerical computer • Human Brain • 38 PetaFlops, 20 Watts • Analog computer • Not program by algorithm no need to store, fetch, decode instructions and operand • Hybrid digital / analog computer • Complement their digital counterparts in solving equations relevant in: Biology, fluid dynamics, weather prediction, quantum chemistry, plasma physics, … Toward an hybrid analog co-processor Telefunken RA770 • System configured by the equations similar to the targeted system and allow variables in the analog computer to evolve with time • Analog computer to provide a quick approximation • Digital computer for programming, storage and precision • Example 2 diff. -
All-NDR Crossbar Logic Dmitri B
All-NDR Crossbar Logic Dmitri B. Strukov, Member, IEEE, and Konstantin K. Likharev, Fellow, IEEE Abstract—We propose new crossbar circuits in which the hybrid CMOS/nanocrossbar circuits do, resulting in a logic functionality, signal restoration, and connectivity are all significant footprint overhead – see, e.g., reviews [8-10]. performed by similar bistable two-terminal devices with For that, however, the gate insulation problem should be negative differential resistance (NDR) in one of the states. The solved. Namely, in all earlier NDR logic circuits we are gate isolation challenge is met by using device’s nonlinearity aware of, Goto pair connection has been performed using together with a multiphase clocking scheme. A preliminary evaluation shows that for at least some applications, the all- some other two-terminal devices – see, e.g., Refs. 11, 12. In NDR approach enables circuit density and data throughput simple (two-wire-layer, uniform) crossbars, this is not an higher than those of hybrid CMOL FPGA ICs. option. In this paper, we propose a solution of the gate isolation problem, based on a multiphase clocking scheme and a specifically engineered device nonlinearity. I. INTRODUCTION ttempts to utilize the negative differential resistance II. ALL-NDR LOGIC CIRCUITS A (NDR) effect in two-terminal devices (based, e.g., on Figure 1a shows an example of the device capable of band-to-band tunneling in Esaki diodes [1] or on resonant performing all the functions we need. Its stack consists of tunneling through quantum wells [2]) for computing have a two back-to-back Esaki diodes (which ensure a symmetric long history. -
Some Key Issues in Microelectronic Packaging
G. V. CLATTERBAUGH, P. VICHOT, AND H. K. CHARLES, JR. Some Key Issues in Microelectronic Packaging Guy V. Clatterbaugh, Paul Vichot, and Harry K. Charles, Jr. Military and space electronics are tending toward increased system perfor- mance, i.e., higher speed, higher circuit density, and higher functionality. Recent reductions in government spending on space and military hardware have also made cost reduction a key consideration. As electronics approach physical size and performance limits, practical considerations such as wireability, thermal management, electromagnetic compatibility, and system reliability become dominant issues in system design. Resolving such issues requires the use of sophisticated analysis and computational methods. (Keywords: Electronic packaging, Multiconductor transmission line analysis, Printed circuit board thermal analysis, Wireability.) INTRODUCTION In recent years, the electronics industry has discov- functionality and performance while reducing volume ered that the major economic advances made in high- and weight. performance electronic circuitry have come with in- The quest to achieve better performance (higher creased integration. The industry is rapidly converging speed and integration) has placed pressure on manu- toward true wafer-scale integration, i.e., toward an facturers and has forced integrated circuits (ICs) closer entire system fabricated on one silicon substrate. Every together. High-speed computer systems require that 5 years or so, we see wafer foundries processing larger the central processing unit and the memory and con- silicon wafers with smaller line geometries. Today, 12- trollers be proximal to minimize interconnection de- in. wafers are being processed with 0.35-mm lines. By lays. The increased functionality of these chips has the year 2010, 16-in. -
Generalization of the Landauer Principle for Computing Devices Based on Many-Valued Logic
entropy Article Generalization of the Landauer Principle for Computing Devices Based on Many-Valued Logic Edward Bormashenko Department of Chemical Engineering, Engineering Sciences Faculty, Ariel University, Ariel 407000, Israel; [email protected]; Tel.: +972-074-729-68-63 Received: 7 October 2019; Accepted: 22 November 2019; Published: 25 November 2019 Abstract: The Landauer principle asserts that “the information is physical”. In its strict meaning, Landauer’s principle states that there is a minimum possible amount of energy required to erase one bit of information, known as the Landauer bound W = kBTln2, where T is the temperature of a thermal reservoir used in the process and kB is Boltzmann’s constant. Modern computers use the binary system in which a number is expressed in the base-2 numeral system. We demonstrate that the Landauer principle remains valid for the physical computing device based on the ternary, and more generally, N-based logic. The energy necessary for erasure of one bit of information (the Landauer bound) W = kBTln2 remains untouched for the computing devices exploiting a many-valued logic. Keywords: Landauer principle; binary logic; ternary logic; Landauer bound; trit 1. Introduction Modern computers use the binary system, whereby a number is expressed in the base-2 numeral system. The base-2 numeral system is a positional notation with a radix of 2. Each digit is referred to as a bit. The base-2 is ubiquitous in computing devices because of its straightforward implementation in digital electronic circuitry using binary logic gates. However, one of the first computing machines was based on the ternary logic.