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STM32 Cortex®-M4 Mcus and Mpus Programming Manual

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STM32 Cortex®-M4 Mcus and Mpus Programming Manual PM0214 Programming manual STM32 Cortex®-M4 MCUs and MPUs programming manual Introduction This programming manual provides information for application and system-level software developers. It gives a full description of the STM32 Cortex®-M4 processor programming model, instruction set and core peripherals. The applicable products are listed in the table below. The Cortex®-M4 processor used in STM32F3 Series, STM32F4 Series, STM32G4 Series, STM32H745/755 and STM32H747/757 Lines, STM32L4 Series, STM32L4+ Series, STM32WB Series, STM32WL Series and STM32MP1 Series, is a high performance 32-bit processor designed for the microcontroller and microprocessor market. It offers significant benefits to developers, including: • Outstanding processing performance combined with fast interrupt handling • Enhanced system debug with extensive breakpoint and trace capabilities • Efficient processor core, system and memories • Ultra-low power consumption with integrated sleep modes • Platform security Table 1. Applicable products Type Product Series and Lines STM32F3 Series, STM32F4 Series, STM32G4 Series, STM32L4 Series, Microcontrollers STM32L4+ Series, STM32WB Series, STM32WL Series STM32H745/755 and STM32H747/757 Lines Microprocessors STM32MP1 Series Reference documents Available from STMicroelectronics web site www.st.com: • Datasheets of STM32F3 Series, STM32F4 Series, STM32G4 Series, STM32H745/755 and STM32H747/757 Lines, STM32L4 Series, STM32L4+ Series, STM32MP1 Series, STM32WB Series and STM32WL Series • Reference manuals of STM32F3 Series, STM32F4 Series, STM32G4 Series, STM32H745/755 and STM32H747/757 Lines, STM32L4 Series, STM32L4+ Series, STM32MP1 Series, STM32WB Series and STM32WL Series March 2020 PM0214 Rev 10 1/262 www.st.com 1 Contents PM0214 Contents 1 About this document . 12 1.1 Typographical conventions . 12 1.2 List of abbreviations for registers . 12 1.3 About the STM32 Cortex-M4 processor and core peripherals . 13 1.3.1 System level interface . 14 1.3.2 Integrated configurable debug . 14 1.3.3 Cortex-M4 processor features and benefits summary . 15 1.3.4 Cortex-M4 core peripherals . 16 2 The Cortex-M4 processor . 17 2.1 Programmers model . 17 2.1.1 Processor mode and privilege levels for software execution . 17 2.1.2 Stacks . 17 2.1.3 Core registers . 18 2.1.4 Exceptions and interrupts . 26 2.1.5 Data types . 26 2.1.6 The Cortex microcontroller software interface standard (CMSIS) . 26 2.2 Memory model . 28 2.2.1 Memory regions, types and attributes . 29 2.2.2 Memory system ordering of memory accesses . 29 2.2.3 Behavior of memory accesses . 30 2.2.4 Software ordering of memory accesses . 31 2.2.5 Bit-banding . 32 2.2.6 Memory endianness . 34 2.2.7 Synchronization primitives . 34 2.2.8 Programming hints for the synchronization primitives . 36 2.3 Exception model . 37 2.3.1 Exception states . 37 2.3.2 Exception types . 37 2.3.3 Exception handlers . 39 2.3.4 Vector table . 40 2.3.5 Exception priorities . 41 2.3.6 Interrupt priority grouping . 41 2.3.7 Exception entry and return . 42 2/262 PM0214 Rev 10 PM0214 Contents 2.4 Fault handling . 44 2.4.1 Fault types . 45 2.4.2 Fault escalation and hard faults . 46 2.4.3 Fault status registers and fault address registers . 47 2.4.4 Lockup . 47 2.5 Power management . 47 2.5.1 Entering sleep mode . 48 2.5.2 Wakeup from sleep mode . 48 2.5.3 External event input / extended interrupt and event input . 49 2.5.4 Power management programming hints . 49 3 The STM32 Cortex-M4 instruction set . 50 3.1 Instruction set summary . 50 3.2 CMSIS intrinsic functions . 58 3.3 About the instruction descriptions . 60 3.3.1 Operands . 60 3.3.2 Restrictions when using PC or SP . 60 3.3.3 Flexible second operand . 60 3.3.4 Shift operations . 62 3.3.5 Address alignment . 65 3.3.6 PC-relative expressions . 65 3.3.7 Conditional execution . 65 3.3.8 Instruction width selection . 68 3.4 Memory access instructions . 69 3.4.1 ADR . 70 3.4.2 LDR and STR, immediate offset . 71 3.4.3 LDR and STR, register offset . 73 3.4.4 LDR and STR, unprivileged . 74 3.4.5 LDR, PC-relative . 75 3.4.6 LDM and STM . 76 3.4.7 PUSH and POP . 78 3.4.8 LDREX and STREX . 79 3.4.9 CLREX . 80 3.5 General data processing instructions . 81 3.5.1 ADD, ADC, SUB, SBC, and RSB . 83 3.5.2 AND, ORR, EOR, BIC, and ORN . 85 PM0214 Rev 10 3/262 8 Contents PM0214 3.5.3 ASR, LSL, LSR, ROR, and RRX . 86 3.5.4 CLZ . 87 3.5.5 CMP and CMN . 88 3.5.6 MOV and MVN . 89 3.5.7 MOVT . 91 3.5.8 REV, REV16, REVSH, and RBIT . 92 3.5.9 SADD16 and SADD8 . 93 3.5.10 SHADD16 and SHADD8 . 94 3.5.11 SHASX and SHSAX . 95 3.5.12 SHSUB16 and SHSUB8 . 96 3.5.13 SSUB16 and SSUB8 . 97 3.5.14 SASX and SSAX . 98 3.5.15 TST and TEQ . 99 3.5.16 UADD16 and UADD8 . ..
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