The Fresh Breeze Model of Thread Execution Jack B

Total Page:16

File Type:pdf, Size:1020Kb

The Fresh Breeze Model of Thread Execution Jack B The Fresh Breeze Model of Thread Execution Jack B. Dennis MIT Computer Science and Artificial Intelligence Laboratory Cambridge, MA 617-253-6956 [email protected] ABSTRACT The Fresh Breeze architecture explores a set of ideas that depart We present the program execution model developed for the Fresh from conventional computer architecture: Breeze Project, which has the goal of developing a multi-core chip Simultaneous multithreading can improve the uti- architecture that supports a better programming model for parallel lization of function units and allow more effective latency computing. The model combines the spawn/sync ideas of Cilk tolerance of memory transactions[22]. with a restricted memory model based on chunks of memory that A global shared address space permits abolition of can be written only while not shared. The result is a multi-thread the conventional distinction between “memory” and program execution model in which determinate behavior may be the file system, and supports a superior execution guaranteed while general forms of parallel computation are environment meeting requirements of program supported. modularity and software reuse[3][5] No memory update of shared data in a Fresh Breeze Categories and Subject Descriptors computer system eliminates the multiprocessor cache C.0 [Computer Systems Organization]: Hardware/software coherence problem: any object retrieved from the memory interfaces; D.1.1 [Programming Languages]: Applicative system is immutable. (Functional) Programming; D.1.3 [Programming Languages]: Cycle-free heap. The no-update rule In a Fresh Breeze Concurrent Programming; D.3.3 [Programming Languages]: computer system makes it easy to prevent the formation Language Constructs and Features; E.1 [Data]: Data Structures. of pointer cycles[7]. Efficient reference-count garbage collection can be implemented in the hardware. General Terms We will show how a program execution model based on these Design, Languages. ideas can provide a platform for robust, general-purpose, parallel computation. In particular, much of the difficulty of writing correct parallel programs stems from problems in getting Keywords synchronization correct. The commonly used methods of thread Program execution model, concurrency, multithreading, coordination are prone to exhibiting nondeterminate behavior, determinacy, streams, transactions. making errors difficult to track down. Moreover, getting control synchronization correct is no guarantee that accesses to data will 1. INTRODUCTION be effected without hazard, especially when memory access has With multiprocessing becoming the usual mode of computing, it is significant latency and memory is shared among concurrently more pressing than ever to adopt a model of program execution executing threads. that supports general parallel programming while avoiding the Our hypothesis is that handling control and data coordination programing difficulties attending the coordination of concurrent separately is a bad idea. Here we explore an approach in which computations in contemporary systems. data and control synchronization are always performed together, This presentation concerns the program execution model as a single atomic operation. This is offered as an alternative to developed for the Fresh Breeze Project[8][6], which has the goal transactional memory approaches that add complexity, often of developing a multi-core chip architecture that supports a better including redundant computation and retry mechanisms. programming model for parallel computing, achieving high Principle: Combine control and data synchronization in performance through parallelism rather than increased clock speed. the design of mechanisms for coordinating concurrent activities. We begin with an introduction to the Fresh Breeze memory model. Permission to make digital or hard copies of all or part of this work The program execution structure of threads of control and method for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial activations is described. Then we present the basic concurrent advantage and that copies bear this notice and the full citation on programming structure of this paper, an adaptation of the classic the first page. To copy otherwise, or republish, to post on servers fork/join control primitives for concurrent processes. We argue or to redistribute to lists, requires prior specific permission and/or a that use of this program structure yields multi-thread programs fee. that are guaranteed to be determinate. Subsequent sections deal concurrently with other subexpressions. with generalization and extension of the basic concept to programs Functions. Function applications may be evaluated that operate on data structures and data streams. How a Fresh concurrently if none uses the results of others. Breeze system can be used to run inherently nondeterminate Data Parallel. The general expression for an array computations such as general transaction processing is discussed element may be evaluated concurrently over all elements in the final section. of the array. Producer/Consumer. If one program module passes a 2. FRESH BREEZE MEMORY MODEL series of values to a second module, then both modules The Fresh Breeze architecture views memory as a collection of may run concurrently. fixed-size chunks, each holding 1024 bits of code or data. A chunk Cascaded Data Structure Construction. This is a kind may hold 32 words of 32 bits each, 16 double length words, or 32 of generalization of producer/consumer concurrency and instructions of a program method. Each chunk has a unique 64-bit will be treated in a later section. identifier (UID) that serves as a pointer for accessing the chunk. A We will show how our thread coordination model supports chunk may also hold up to 16 UIDs to represent structured each of these forms of parallelism. information. For example, a three-level tree of chunks could represent an array of 16 * 16 * 32 elements. 5. THE BASIC SCHEME The collection of chunks containing pointers to other chunks Our basic program structure for concurrency is an adaptation of forms a heap which may be regarded as a graph. The Fresh Breeze the fork/join model and is similar to the concurrency scheme of program execution model is designed so that cycles in the heap Cilk[14]. A master thread spawns a slave thread (executing a new cannot be constructed. This is ensured by the rule that updates to function activation) that performs an independent computation the contents of chunks are disallowed once they are shared, and and terminates by joining with the master thread. The problem to marking pointers to chunks in process of definition (creation) so be solved is that of performing the join in a safe manner -- in a that a thread may not store them in any chunk that is under way that does not introduce the possibility of hazards. For the construction. present we assume that the slave computation is contributing a In a Fresh Breeze system all on-line data, including files and single value (one computer word) to the computation being databases, are held in the chunk memory as data structures in the performed by the master thread. heap. Because, in our model, there is no shared data between the master In the following, we will show how this memory model can and slave threads, updating shared data cannot be used to support a variety of program constructions for parallel communicate the slave result to the master. (This is good because computation. a shared data mechanism would likely introduce possible hazards.) Our scheme is the following: When the master spawns the slave 3. PROGRAM EXECUTION thread, it initializes a join point and provides the slave thread with Computation in a Fresh Breeze system is carried out by method a join ticket that permits it to exercise (use) the join point. The join activations on behalf of a system user. Computation in a method point is a special entry in the local data segment of the master activation is performed by exactly one thread of instruction thread that has (1) space for a record of master thread status; and execution. The thread has access to the code segment of the (2) space for the result value that will be computed by the slave method, a local data segment, and a set of registers that hold thread. The join point includes a flag that indicates whether a intermediate results. The code segment is read-only and may be value has been entered by the slave thread, and a flag that indicates shared by many threads for different method activations. The that a join ticket has been issued. registers and local data segment are private data of the thread and A join ticket is similar to the return address of a method, and is are only accessible to it. held at a protected location in the local data segment of the slave Note that in this model of computation, a thread (method method activation. It consists of (1) the unique identifier (pointer) activation) can only access information in the heap that it creates of the local data segment of the master thread; and (2) the index of or that is given to it when it begins execution. the join point within the master thread local data segment. Special instructions are provided to access a join point. The 4. FORMS OF PARALLELISM instruction. The Spawn instruction sets a flag in the join point and Functional programming languages are known to offer better starts execution by the slave thread after storing a joint ticket in its programmer productivity due to their
Recommended publications
  • An Execution Model for Serverless Functions at the Edge
    An Execution Model for Serverless Functions at the Edge Adam Hall Umakishore Ramachandran Georgia Institute of Technology Georgia Institute of Technology Atlanta, Georgia Atlanta, Georgia ach@gatech:edu rama@gatech:edu ABSTRACT 1 INTRODUCTION Serverless computing platforms allow developers to host single- Enabling next generation technologies such as self-driving cars or purpose applications that automatically scale with demand. In con- smart cities via edge computing requires us to reconsider the way trast to traditional long-running applications on dedicated, virtu- we characterize and deploy the services supporting those technolo- alized, or container-based platforms, serverless applications are gies. Edge/fog environments consist of many micro data centers intended to be instantiated when called, execute a single function, spread throughout the edge of the network. This is in stark contrast and shut down when finished. State-of-the-art serverless platforms to the cloud, where we assume the notion of unlimited resources achieve these goals by creating a new container instance to host available in a few centralized data centers. These micro data center a function when it is called and destroying the container when it environments must support large numbers of Internet of Things completes. This design allows for cost and resource savings when (IoT) devices on limited hardware resources, processing the mas- hosting simple applications, such as those supporting IoT devices sive amounts of data those devices generate while providing quick at the edge of the network. However, the use of containers intro- decisions to inform their actions [44]. One solution to supporting duces some overhead which may be unsuitable for applications emerging technologies at the edge lies in serverless computing.
    [Show full text]
  • CS 2210: Theory of Computation
    CS 2210: Theory of Computation Spring, 2019 Administrative Information • Background survey • Textbook: E. Rich, Automata, Computability, and Complexity: Theory and Applications, Prentice-Hall, 2008. • Book website: http://www.cs.utexas.edu/~ear/cs341/automatabook/ • My Office Hours: – Monday, 6:00-8:00pm, Searles 224 – Tuesday, 1:00-2:30pm, Searles 222 • TAs – Anjulee Bhalla: Hours TBA, Searles 224 – Ryan St. Pierre, Hours TBA, Searles 224 What you can expect from the course • How to do proofs • Models of computation • What’s the difference between computability and complexity? • What’s the Halting Problem? • What are P and NP? • Why do we care whether P = NP? • What are NP-complete problems? • Where does this make a difference outside of this class? • How to work the answers to these questions into the conversation at a cocktail party… What I will expect from you • Problem Sets (25%): – Goal: Problems given on Mondays and Wednesdays – Due the next Monday – Graded by following Monday – A learning tool, not a testing tool – Collaboration encouraged; more on this in next slide • Quizzes (15%) • Exams (2 non-cumulative, 30% each): – Closed book, closed notes, but… – Can bring in 8.5 x 11 page with notes on both sides • Class participation: Tiebreaker Other Important Things • Go to the TA hours • Study and work on problem sets in groups • Collaboration Issues: – Level 0 (In-Class Problems) • No restrictions – Level 1 (Homework Problems) • Verbal collaboration • But, individual write-ups – Level 2 (not used in this course) • Discussion with TAs only – Level 3 (Exams) • Professor clarifications only Right now… • What does it mean to study the “theory” of something? • Experience with theory in other disciplines? • Relationship to practice? – “In theory, theory and practice are the same.
    [Show full text]
  • The Problem with Threads
    The Problem with Threads Edward A. Lee Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2006-1 http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-1.html January 10, 2006 Copyright © 2006, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Acknowledgement This work was supported in part by the Center for Hybrid and Embedded Software Systems (CHESS) at UC Berkeley, which receives support from the National Science Foundation (NSF award No. CCR-0225610), the State of California Micro Program, and the following companies: Agilent, DGIST, General Motors, Hewlett Packard, Infineon, Microsoft, and Toyota. The Problem with Threads Edward A. Lee Professor, Chair of EE, Associate Chair of EECS EECS Department University of California at Berkeley Berkeley, CA 94720, U.S.A. [email protected] January 10, 2006 Abstract Threads are a seemingly straightforward adaptation of the dominant sequential model of computation to concurrent systems. Languages require little or no syntactic changes to sup- port threads, and operating systems and architectures have evolved to efficiently support them. Many technologists are pushing for increased use of multithreading in software in order to take advantage of the predicted increases in parallelism in computer architectures.
    [Show full text]
  • Toward IFVM Virtual Machine: a Model Driven IFML Interpretation
    Toward IFVM Virtual Machine: A Model Driven IFML Interpretation Sara Gotti and Samir Mbarki MISC Laboratory, Faculty of Sciences, Ibn Tofail University, BP 133, Kenitra, Morocco Keywords: Interaction Flow Modelling Language IFML, Model Execution, Unified Modeling Language (UML), IFML Execution, Model Driven Architecture MDA, Bytecode, Virtual Machine, Model Interpretation, Model Compilation, Platform Independent Model PIM, User Interfaces, Front End. Abstract: UML is the first international modeling language standardized since 1997. It aims at providing a standard way to visualize the design of a system, but it can't model the complex design of user interfaces and interactions. However, according to MDA approach, it is necessary to apply the concept of abstract models to user interfaces too. IFML is the OMG adopted (in March 2013) standard Interaction Flow Modeling Language designed for abstractly expressing the content, user interaction and control behaviour of the software applications front-end. IFML is a platform independent language, it has been designed with an executable semantic and it can be mapped easily into executable applications for various platforms and devices. In this article we present an approach to execute the IFML. We introduce a IFVM virtual machine which translate the IFML models into bytecode that will be interpreted by the java virtual machine. 1 INTRODUCTION a fundamental standard fUML (OMG, 2011), which is a subset of UML that contains the most relevant The software development has been affected by the part of class diagrams for modeling the data apparition of the MDA (OMG, 2015) approach. The structure and activity diagrams to specify system trend of the 21st century (BRAMBILLA et al., behavior; it contains all UML elements that are 2014) which has allowed developers to build their helpful for the execution of the models.
    [Show full text]
  • A Brief History of Just-In-Time Compilation
    A Brief History of Just-In-Time JOHN AYCOCK University of Calgary Software systems have been using “just-in-time” compilation (JIT) techniques since the 1960s. Broadly, JIT compilation includes any translation performed dynamically, after a program has started execution. We examine the motivation behind JIT compilation and constraints imposed on JIT compilation systems, and present a classification scheme for such systems. This classification emerges as we survey forty years of JIT work, from 1960–2000. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors; K.2 [History of Computing]: Software General Terms: Languages, Performance Additional Key Words and Phrases: Just-in-time compilation, dynamic compilation 1. INTRODUCTION into a form that is executable on a target platform. Those who cannot remember the past are con- What is translated? The scope and na- demned to repeat it. ture of programming languages that re- George Santayana, 1863–1952 [Bartlett 1992] quire translation into executable form covers a wide spectrum. Traditional pro- This oft-quoted line is all too applicable gramming languages like Ada, C, and in computer science. Ideas are generated, Java are included, as well as little lan- explored, set aside—only to be reinvented guages [Bentley 1988] such as regular years later. Such is the case with what expressions. is now called “just-in-time” (JIT) or dy- Traditionally, there are two approaches namic compilation, which refers to trans- to translation: compilation and interpreta- lation that occurs after a program begins tion. Compilation translates one language execution. into another—C to assembly language, for Strictly speaking, JIT compilation sys- example—with the implication that the tems (“JIT systems” for short) are com- translated form will be more amenable pletely unnecessary.
    [Show full text]
  • A Parallel Program Execution Model Supporting Modular Software Construction
    A Parallel Program Execution Model Supporting Modular Software Construction Jack B. Dennis Laboratory for Computer Science Massachusetts Institute of Technology Cambridge, MA 02139 U.S.A. [email protected] Abstract as a guide for computer system design—follows from basic requirements for supporting modular software construction. A watershed is near in the architecture of computer sys- The fundamental theme of this paper is: tems. There is overwhelming demand for systems that sup- port a universal format for computer programs and software The architecture of computer systems should components so users may benefit from their use on a wide reflect the requirements of the structure of pro- variety of computing platforms. At present this demand is grams. The programming interface provided being met by commodity microprocessors together with stan- should address software engineering issues, in dard operating system interfaces. However, current systems particular, the ability to practice the modular do not offer a standard API (application program interface) construction of software. for parallel programming, and the popular interfaces for parallel computing violate essential principles of modular The positions taken in this presentation are contrary to or component-based software construction. Moreover, mi- much conventional wisdom, so I have included a ques- croprocessor architecture is reaching the limit of what can tion/answer dialog at appropriate places to highlight points be done usefully within the framework of superscalar and of debate. We start with a discussion of the nature and VLIW processor models. The next step is to put several purpose of a program execution model. Our Parallelism processors (or the equivalent) on a single chip.
    [Show full text]
  • Computer Architecture: Dataflow (Part I)
    Computer Architecture: Dataflow (Part I) Prof. Onur Mutlu Carnegie Mellon University A Note on This Lecture n These slides are from 18-742 Fall 2012, Parallel Computer Architecture, Lecture 22: Dataflow I n Video: n http://www.youtube.com/watch? v=D2uue7izU2c&list=PL5PHm2jkkXmh4cDkC3s1VBB7- njlgiG5d&index=19 2 Some Required Dataflow Readings n Dataflow at the ISA level q Dennis and Misunas, “A Preliminary Architecture for a Basic Data Flow Processor,” ISCA 1974. q Arvind and Nikhil, “Executing a Program on the MIT Tagged- Token Dataflow Architecture,” IEEE TC 1990. n Restricted Dataflow q Patt et al., “HPS, a new microarchitecture: rationale and introduction,” MICRO 1985. q Patt et al., “Critical issues regarding HPS, a high performance microarchitecture,” MICRO 1985. 3 Other Related Recommended Readings n Dataflow n Gurd et al., “The Manchester prototype dataflow computer,” CACM 1985. n Lee and Hurson, “Dataflow Architectures and Multithreading,” IEEE Computer 1994. n Restricted Dataflow q Sankaralingam et al., “Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture,” ISCA 2003. q Burger et al., “Scaling to the End of Silicon with EDGE Architectures,” IEEE Computer 2004. 4 Today n Start Dataflow 5 Data Flow Readings: Data Flow (I) n Dennis and Misunas, “A Preliminary Architecture for a Basic Data Flow Processor,” ISCA 1974. n Treleaven et al., “Data-Driven and Demand-Driven Computer Architecture,” ACM Computing Surveys 1982. n Veen, “Dataflow Machine Architecture,” ACM Computing Surveys 1986. n Gurd et al., “The Manchester prototype dataflow computer,” CACM 1985. n Arvind and Nikhil, “Executing a Program on the MIT Tagged-Token Dataflow Architecture,” IEEE TC 1990.
    [Show full text]
  • Ece585 Lec2.Pdf
    ECE 485/585 Microprocessor System Design Lecture 2: Memory Addressing 8086 Basics and Bus Timing Asynchronous I/O Signaling Zeshan Chishti Electrical and Computer Engineering Dept Maseeh College of Engineering and Computer Science Source: Lecture based on materials provided by Mark F. Basic I/O – Part I ECE 485/585 Outline for next few lectures Simple model of computation Memory Addressing (Alignment, Byte Order) 8088/8086 Bus Asynchronous I/O Signaling Review of Basic I/O How is I/O performed Dedicated/Isolated /Direct I/O Ports Memory Mapped I/O How do we tell when I/O device is ready or command complete? Polling Interrupts How do we transfer data? Programmed I/O DMA ECE 485/585 Simplified Model of a Computer Control Control Data, Address, Memory Data Path Microprocessor Keyboard Mouse [Fetch] Video display [Decode] Printer [Execute] I/O Device Hard disk drive Audio card Ethernet WiFi CD R/W DVD ECE 485/585 Memory Addressing Size of operands Bytes, words, long/double words, quadwords 16-bit half word (Intel: word) 32-bit word (Intel: doubleword, dword) 0x107 64-bit double word (Intel: quadword, qword) 0x106 Note: names are non-standard 0x105 SUN Sparc word is 32-bits, double is 64-bits 0x104 0x103 Alignment 0x102 Can multi-byte operands begin at any byte address? 0x101 Yes: non-aligned 0x100 No: aligned. Low order address bit(s) will be zero ECE 485/585 Memory Operand Alignment …Intel IA speak (i.e. word = 16-bits = 2 bytes) 0x107 0x106 0x105 0x104 0x103 0x102 0x101 0x100 Aligned Unaligned Aligned Unaligned Aligned Unaligned word word Double Double Quad Quad address address word word word word -----0 address address address address -----00 ----000 ECE 485/585 Memory Operand Alignment Why do we care? Unaligned memory references Can cause multiple memory bus cycles for a single operand May also span cache lines Requiring multiple evictions, multiple cache line fills Complicates memory system and cache controller design Some architectures restrict addresses to be aligned Even in architectures without alignment restrictions (e.g.
    [Show full text]
  • CNT6008 Network Programming Module - 11 Objectives
    CNT6008 Network Programming Module - 11 Objectives Skills/Concepts/Assignments Objectives ASP.NET Overview • Learn the Framework • Understand the different platforms • Compare to Java Platform Final Project Define your final project requirements Section 21 – Web App Read Sections 21 and 27, pages 649 to 694 and 854 Development and ASP.NET to 878. Section 27 – Web App Development with ASP.NET Overview of ASP.NET Section Goals Goal Course Presentation Understanding Windows Understanding .NET Framework Foundation Project Concepts Creating a ASP.NET Client and Server Application Understanding the Visual Creating a ASP Project Studio Development Environment .NET – What Is It? • Software platform • Language neutral • In other words: • .NET is not a language (Runtime and a library for writing and executing written programs in any compliant language) What Is .NET • .Net is a new framework for developing web-based and windows-based applications within the Microsoft environment. • The framework offers a fundamental shift in Microsoft strategy: it moves application development from client-centric to server- centric. .NET – What Is It? .NET Application .NET Framework Operating System + Hardware Framework, Languages, And Tools VB VC++ VC# JScript … Common Language Specification Visual Studio.NET Visual ASP.NET: Web Services Windows and Web Forms Forms ADO.NET: Data and XML Base Class Library Common Language Runtime The .NET Framework .NET Framework Services • Common Language Runtime • Windows Communication Framework (WCF) • Windows® Forms • ASP.NET (Active Server Pages) • Web Forms • Web Services • ADO.NET, evolution of ADO • Visual Studio.NET Common Language Runtime (CLR) • CLR works like a virtual machine in executing all languages. • All .NET languages must obey the rules and standards imposed by CLR.
    [Show full text]
  • The CLR's Execution Model
    C01621632.fm Page 3 Thursday, January 12, 2006 3:49 PM Chapter 1 The CLR’s Execution Model In this chapter: Compiling Source Code into Managed Modules . 3 Combining Managed Modules into Assemblies . 6 Loading the Common Language Runtime. 8 Executing Your Assembly’s Code. 11 The Native Code Generator Tool: NGen.exe . 19 Introducing the Framework Class Library . 22 The Common Type System. 24 The Common Language Specification . 26 Interoperability with Unmanaged Code. 30 The Microsoft .NET Framework introduces many new concepts, technologies, and terms. My goal in this chapter is to give you an overview of how the .NET Framework is designed, intro- duce you to some of the new technologies the framework includes, and define many of the terms you’ll be seeing when you start using it. I’ll also take you through the process of build- ing your source code into an application or a set of redistributable components (files) that contain types (classes, structures, etc.) and then explain how your application will execute. Compiling Source Code into Managed Modules OK, so you’ve decided to use the .NET Framework as your development platform. Great! Your first step is to determine what type of application or component you intend to build. Let’s just assume that you’ve completed this minor detail; everything is designed, the specifications are written, and you’re ready to start development. Now you must decide which programming language to use. This task is usually difficult because different languages offer different capabilities. For example, in unmanaged C/C++, you have pretty low-level control of the system.
    [Show full text]
  • 10. Assembly Language, Models of Computation
    10. Assembly Language, Models of Computation 6.004x Computation Structures Part 2 – Computer Architecture Copyright © 2015 MIT EECS 6.004 Computation Structures L10: Assembly Language, Models of Computation, Slide #1 Beta ISA Summary • Storage: – Processor: 32 registers (r31 hardwired to 0) and PC – Main memory: Up to 4 GB, 32-bit words, 32-bit byte addresses, 4-byte-aligned accesses OPCODE rc ra rb unused • Instruction formats: OPCODE rc ra 16-bit signed constant 32 bits • Instruction classes: – ALU: Two input registers, or register and constant – Loads and stores: access memory – Branches, Jumps: change program counter 6.004 Computation Structures L10: Assembly Language, Models of Computation, Slide #2 Programming Languages 32-bit (4-byte) ADD instruction: 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 opcode rc ra rb (unused) Means, to the BETA, Reg[4] ß Reg[2] + Reg[3] We’d rather write in assembly language: Today ADD(R2, R3, R4) or better yet a high-level language: Coming up a = b + c; 6.004 Computation Structures L10: Assembly Language, Models of Computation, Slide #3 Assembly Language Symbolic 01101101 11000110 Array of bytes representation Assembler 00101111 to be loaded of stream of bytes 10110001 into memory ..... Source Binary text file machine language • Abstracts bit-level representation of instructions and addresses • We’ll learn UASM (“microassembler”), built into BSim • Main elements: – Values – Symbols – Labels (symbols for addresses) – Macros 6.004 Computation Structures L10: Assembly Language, Models
    [Show full text]
  • Executing UML Models
    Executing UML Models Miguel Pinto Luz1, Alberto Rodrigues da Silva1 1Instituto Superior Técnico Av. Rovisco Pais 1049-001 Lisboa – Portugal {miguelluz, alberto.silva}@acm.org Abstract. Software development evolution is a history of permanent seeks for raising the abstraction level to new limits overcoming new frontiers. Executable UML (xUML) comes this way as the expectation to achieve the next level in abstraction, offering the capability of deploying a xUML model in a variety of software environments and platforms without any changes. This paper comes as a first expedition inside xUML, exploring the main aspects of its specification including the action languages support and the fundamental MDA compliance. In this paper is presented a future new xUML tool called XIS-xModels that gives Microsoft Visio new capabilities of running and debugging xUML models. This paper is an outline of the capabilities and main features of the future application. Keywords: UML, executable UML, Model Debugging, Action Language. 1. Introduction In a dictionary we find that an engineer is a person who uses scientific knowledge to solve practical problems, planning and directing, but an information technology engineer is someone that spends is time on implementing lines of code, instead of being focus on planning and projecting. Processes, meetings, models, documents, or even code are superfluous artifacts for organizations: all they need is well design and fast implemented working system, that moves them towards a new software development paradigm, based on high level executable models. According this new paradigm it should be possible to reduce development time and costs, and to bring new product quality warranties, only reachable by executing, debugging and testing early design stages (models).
    [Show full text]