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ADSP-TS201 Tigersharc Processor Hardware Reference, Revision 1.0, November 2004

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ADSP-TS201 Tigersharc Processor Hardware Reference, Revision 1.0, November 2004 ADSP-TS201 TigerSHARC® Processor Hardware Reference Revision 1.1, December 2004 Part Number 82-000815-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information © 2004 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo, Blackfin, EZ-ICE, SHARC, TigerSHARC, the TigerSHARC logo, and VisualDSP++, and are registered trademarks of Analog Devices, Inc. Static Superscalar is a trademark of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. CONTENTS CONTENTS PREFACE Purpose of This Manual ................................................................. xxi Intended Audience ......................................................................... xxi Manual Contents .......................................................................... xxii What’s New in This Manual ......................................................... xxiv Technical or Customer Support ..................................................... xxv Supported Processors .................................................................... xxvi Product Information ................................................................... xxvii MyAnalog.com ...................................................................... xxvii Processor Product Information ............................................... xxvii Related Documents .............................................................. xxviii Online Technical Documentation ........................................... xxix Accessing Documentation From VisualDSP++ ..................... xxx Accessing Documentation From Windows ........................... xxx Accessing Documentation From the Web ............................ xxxi Printed Manuals ..................................................................... xxxi ADSP-TS201 TigerSHARC Processor Hardware Reference iii CONTENTS VisualDSP++ Documentation Set ...................................... xxxi Hardware Tools Manuals .................................................. xxxii Processor Manuals ............................................................ xxxii Data Sheets ...................................................................... xxxii Conventions .............................................................................. xxxiii PROCESSOR ARCHITECTURE Processor Core .............................................................................. 1-8 Compute Blocks ................................................................... 1-10 Arithmetic Logic Unit (ALU) ............................................ 1-12 Communications Logic Unit (CLU) .................................. 1-12 Multiply Accumulator (Multiplier) .................................... 1-12 Bit Wise Barrel Shifter (Shifter) ........................................ 1-13 Integer Arithmetic Logic Unit (IALU) ................................... 1-13 Program Sequencer ............................................................... 1-15 Processor Core Controls ........................................................ 1-17 Clock Domains ................................................................ 1-17 Operation Modes ............................................................. 1-18 User Mode ................................................................... 1-19 Supervisor Mode ........................................................... 1-20 Emulator Mode ............................................................ 1-20 Boot Modes ...................................................................... 1-22 Memory, Registers, and Buses ..................................................... 1-22 Internal Buses ....................................................................... 1-23 Internal Registers .................................................................. 1-23 iv ADSP-TS201 TigerSHARC Processor Hardware Reference CONTENTS SOC Interface ............................................................................. 1-24 Timers ........................................................................................ 1-24 Flags ........................................................................................... 1-25 Interrupts ................................................................................... 1-26 Direct Memory Access ................................................................. 1-26 External (Address and Data) Port ................................................. 1-28 External Bus and Host Interface ............................................. 1-28 External Memory .............................................................. 1-29 Multiprocessing ................................................................ 1-30 Host Interface ................................................................... 1-31 Link Ports ................................................................................... 1-32 JTAG Port and Debug Interface .................................................. 1-32 Programming Information ........................................................... 1-33 MEMORY AND REGISTERS Host Address Space ....................................................................... 2-4 External Memory Bank Space ........................................................ 2-4 Multiprocessor Space ..................................................................... 2-6 Internal Address Space .................................................................. 2-7 Universal (Ureg) Register Space ..................................................... 2-8 Compute Block Register Groups ............................................ 2-14 Unmapped Compute Block Registers ................................. 2-19 IALU Register Groups ........................................................... 2-22 IALU Status (J31/JSTAT and K31/KSTAT) Registers ......... 2-26 Sequencer Register Groups .................................................... 2-27 ADSP-TS201 TigerSHARC Processor Hardware Reference v CONTENTS Flag Control (FLAGREG) Register ................................... 2-28 Sequencer Control (SQCTL) Register ............................... 2-29 Static Flags (SFREG) Register ........................................... 2-30 Sequencer Control Set Bits (SQCTLST) Register .............. 2-31 Sequencer Control Clear Bits (SQCTLCL) Register ........... 2-31 Sequencer Status (SQSTAT) Register ................................ 2-31 Cache Register Groups .......................................................... 2-34 Cache/Memory System Command/Status (CACMDx, CCAIRx, and CASTATx) Registers ............. 2-36 Interrupt Register Groups ..................................................... 2-41 Interrupt Vector Table Register Groups ............................. 2-41 Interrupt Control (INTCTL) Register ............................... 2-45 Interrupt Latch (ILATL/ILATH) Registers ........................ 2-46 Interrupt Pointer Mask (PMASKL/PMASKH) Registers .... 2-47 Interrupt Mask (IMASKL/IMASKH) Registers .................. 2-47 Timer Interrupt (TIMERxH/L) Registers .......................... 2-50 Timer Initial Value (TMRINxH/L) Registers ..................... 2-50 DMA Control and Status Register Group .............................. 2-51 DMA Control (DCNT) Register ....................................... 2-51 DMA Status (DSTAT) Register ......................................... 2-53 External Port DMA TCB Register Group ............................... 2-56 Link Port Transmit DMA TCB Register Group ...................... 2-57 Link Port Receive DMA TCB Register Group ........................ 2-58 AutoDMA Register Group .................................................... 2-60 vi ADSP-TS201 TigerSHARC Processor Hardware Reference CONTENTS DMA Index (DI), X-Dimension (DX), Y-Dimension (DY), and Pointer (DP) TCB Registers ........... 2-61 Link Port Register Groups ..................................................... 2-65 Link Receive Control (LRCTLx) Registers ......................... 2-68 Link Transmit Control (LTCTLx) Registers ....................... 2-69 Link Receive Status (LRSTATx) Registers .......................... 2-70 Link Transmit Status (LTSTATx) Registers ........................ 2-71 External Bus Interface Register Groups .................................. 2-72 System Configuration (SYSCON) Register ........................ 2-73 Bus Lock (BUSLOCK) System Control Register ................ 2-76 SDRAM Configuration (SDRCON) Register .................... 2-76 System Status (SYSTAT) Register ...................................... 2-77 Bus Master Maximum (BMAX) Register ............................ 2-80 Bus Master Maximum Current Count (BMAXC) Register .. 2-80 JTAG Test and Emulation Register Groups ............................ 2-81 Emulation Control (EMUCTL) Register ........................... 2-82 Emulation Status (EMUSTAT) Register ............................
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