Tigersharc DSP Hardware Specification, Revision 1.0.2, Direct Memory Access

7 DIRECT MEMORY ACCESS Figure 7-0. Table 7-0. Listing 7-0. Overview Direct Memory Access (DMA) is a mechanism for transferring data with- out core being involved. The TigerSHARC® DSP’s on-chip DMA controller relieves the core processor of the burden of moving data between internal memory and an external device, external memory, or between link ports and internal or external memory. The fully-integrated DMA controller allows the TigerSHARC® DSP core processor, or an external device, to specify data transfer operations and return to normal processing while the DMA controller carries out the data transfers in the background. The TigerSHARC® DSP DMA competes with other masters for internal memory access. For more information, see “Architecture and Microarchi- tecture Overview” on page 6-7. This conflict is minimized due to the large internal memory bandwidth that is available. The DMA includes 14 DMA channels, four of which are dedicated to external memory devices, eight to link ports, and two to AutoDMA registers. TigerSHARC DSP Hardware Specification 7 - 1 Overview Figure 7-1 shows a block diagram of the TigerSHARC® DSP’s DMA controller. TRANSMITTER RECEIVER TCB TCB REGISTERS REGISTERS Internal DMA DMA CONTROLLER Bus Requests Interface Figure 7-1. DMA Block Diagram Data Transfers — General Information The DMA controller can perform several types of data transfers: • Internal memory ⇒ external memory and memory-mapped peripherals • Internal memory ⇒ internal memory of other TigerSHARC® DSPs residing on the cluster bus • Internal memory ⇒ host processor • Internal memory ⇒ link port I/O • External memory ⇒ external peripherals 7 - 2 TigerSHARC DSP Hardware Specification Direct Memory Access • External memory ⇒ internal memory • External memory ⇒ link port I/O • Link port I/O ⇒ internal memory • Link port I/O ⇒ external memory • Cluster bus master via AutoDMA registers ⇒ internal memory Internal-to-internal memory transfers are not directly supported. Trans- fers may be executed through the multiprocessing space, although this loads the cluster bus. The AutoDMA registers (see “AutoDMA Register Control” on page 7-23) are accessed by a cluster bus master or by the core itself via the multiprocessing address space. They cannot be accessed via the internal address space. In chained DMA operations, a DMA transfer can be programmed to auto-initialize another DMA operation to follow the current one. This technique is primarily used for the same DMA channel, but, in some cases, it may be used for a different channel. DMAR I/O Pins The DMA request pins (DMAR[3:0]) allow I/O devices to request DMA services from the TigerSHARC® DSP. As a response to a DMA request, the TigerSHARC® DSP performs DMA transfers according to DMA channels initialization. Any DMA request from an uninitialized channel is ignored. The DMAR inputs are edge-sensitive. The TigerSHARC® DSP supports four external DMA request input signals, DMAR0, DMAR1, DMAR2 and DMAR3, and one output signal, FLYBY, to support DMA transfers between external peripheral devices. In FLYBY TigerSHARC DSP Hardware Specification 7 - 3 Overview transactions internal memory or peripherals are not involved. Only channel 0 should be defined to work in flyby mode. By asserting a DMARx pin and waiting for the appropriate bus transaction to be performed by the TigerSHARC® DSP, an I/O device can transfer data to TigerSHARC® DSP internal memory, or links. FLYBY output can be used to transfer data between an I/O device and external memory—in this case the TigerSHARC® DSP performs a bus transaction but does not read or write data. Terminology Terms that appear several times in this chapter are defined below: • External Port Input FIFO (IFIFO) This refers to the TigerSHARC® DSP Bus Interface Unit (BIU) input FIFO. It is used for all externally-supplied data by bus masters (other TigerSHARC® DSPs or a host processor), direct writes or external reads. The IFIFO also holds on-chip destination addresses and data attributes. • External Port Output FIFO(OFIFO) This refers to the TigerSHARC® DSP BIU output FIFO. It is used for all outgoing external port addresses, data, and transaction control signals, including DMA transfers to and from external address space. • Transfer Control Block (TCB) This is a quad word that defines a set of parameters for the DMA operation. •DMA TCB register This is a quad word register that contains a Transfer Control Block. 7 - 4 TigerSHARC DSP Hardware Specification Direct Memory Access • TCB chain loading This refers to the process in which the TigerSHARC® DSP’s DMA controller downloads a TCB from memory and auto-initializes the DMA TCB register. • AutoDMA registers These are two virtual DMA registers that can only be accessed by a cluster bus master and that allow data to be moved to a block defined by the channel's TCB register. For more information, see “AutoDMA Register Control” on page 7-23. DMA Controller Features There are 14 DMA channels, dedicated to four types of transfers: 1. Between internal memory and cluster bus (both directions) – these channels have two TCBs each: transmitter TCB and receiver TCB. 2. From AutoDMA register to internal memory – these channels have one receiver TCB. 3. From internal or external memory to the links – these channels have one transmitter TCB. 4. To internal or external memory from the links – these channels have one receiver TCB. Cluster Bus Transfers Cluster bus data transfers move data between the TigerSHARC® DSP internal memory and external memory or external I/O devices: • Internal to external memory transfers Transmitter DMA TCB registers are programmed with the internal memory address, the address increment, the number of transfers, TigerSHARC DSP Hardware Specification 7 - 5 Overview and the control bits. Receiver DMA TCB registers are programmed with the external memory address, the address increment, the number of transfers, and the control bits. • External to internal memory transfers Transmitter DMA TCB registers are programmed with the external memory address, the address increment, the number of transfers and control bits. Receiver DMA TCB registers are programmed with the internal memory address, the address increment, the number of transfer, and control bits. Once setup programming is complete, DMA transfers start automatically and either continue until the entire block is transferred, or until one transaction after each DMARx pulse. TCB programming determines the instructions to be followed. • External device and external memory transfers An additional DMA capability allows the TigerSHARC® DSP to support data transfers between an external device and external memory (flyby transactions). This transfer does not interfere with internal TigerSHARC® DSP operations. An external I/O device, unlike memory, should give an indication that it is ready for data transfer. A source device is ready if it has data to write. A receiver is ready when it has space in its write buffer. There are two techniques that these devices can synchronize with the TigerSHARC® DSP DMA channels: a. The source or receiver can assert a DMA Request input (DMARx) every time that it is ready to transfer new data. The DMA requests are accumulated in the DMA and it issues a transaction on the corresponding channel per DMA request. Up to 15 requests may be accumulated. 7 - 6 TigerSHARC DSP Hardware Specification Direct Memory Access b. A source that can be a master on the cluster bus can write to an AutoDMA register. After data are written to the AutoDMA register, the AutoDMA channel transfers the data according to its initialization. Link Transfers Link DMA transfers handle data transmitted and received through the TigerSHARC® DSP's link ports. The following features are included: • Data is automatically transferred from or to internal or external memory, when performing direct memory accesses to or from a link. • Support for link-to-link port data transfers. Two-Dimensional DMA The DMA is able to address and transfer two-dimensional memory arrays, where X and Y array dimensions are defined in transmitter and receiver TCB registers. • Receiver array dimensions can differ from those of the transmitter's, as long as the total number of words in source and destination are equal. • A two-dimensional memory array can be moved to a one-dimensional array and vice versa, as long as the total number of words in source and destination are equal. • A two-dimensional block in memory can be transmitted via links, or a block received through links or from AutoDMA can be placed in memory as a two-dimensional array. TigerSHARC DSP Hardware Specification 7 - 7 Overview DMA Architecture Overview DMA transfers are characterized by the direction of data flow, that is, from the transmitter (source) to the receiver (destination). If the transmitter or receiver is memory, it is characterized by a TCB register. Link and AutoDMA channels have one TCB register each. A transmit channel has one source TCB. A receive link or AutoDMA channel has one destination TCB register. Feedthrough from the receiver link to another transmitter link can be caused by using a receiver link channel for programming its TCB to send data to the target transmitter link buffer. DMA initiates a transaction as specified by TCB programming and requests. The TCB programming determines if the DMA operates continu- ously or on requests (handshake mode). The link channels and AutoDMA channels always work by requests, which are generated internally by the link or by the AutoDMA registers. The memory-to-memory DMA channels can work either autonomously after initialization, or in handshake mode, using DMARx input pins. The bus transaction is always initiated by the DMA; the source of the transaction is the transmitter; and the transaction destination is the receiver. Transactions that involve link or transactions where the transmitter is the internal memory are issued on the internal bus.

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