MICROCOMPUTER CONTROL and OPTIMIZATION of ELECTROCHEMICAL INSTRUMENTATION William Franklin Farrell Jr. a Thesis Submitted for Th

MICROCOMPUTER CONTROL AND OPTIMIZATION OF ELECTROCHEMICAL INSTRUMENTATION

William Franklin Farrell Jr.

A thesis submitted for the degree of Doctor of Philosophy of the University of London

Chemistry Department September 1979. Imperial College of Science and Technology London SW7 2AZ ABSTRACT Microcomputer Control and Optimization of Electrochemical Instrumentation by William F. Farrell Jr.

Microcomputer-based experimental control and optimization are applied to three electrochemical techniques : ion- selective electrode potentiometry, stationary electrode polarography (SEP) and staircase voltammetry (SCV). For each technique, a hierarchical computer system is used incorporating a mini-computer/microcomputer pair for the potentiometry and polarography experiments, and a microcomputer/ microcomputer pair for the voltammetry experiments.

In the potentiometric experiments, the computer system is used for the data logging of ion selective electrode signals during calibration and selectivity studies. A sodium selective liquid-membrane electrode based on a neutral carrier ligand synthesized by Simon is evaluated. The electrode exhibits a high selectivity to sodium over potassium, magnesium and calcium, low drift characteristics and a rapid. response time in both aqueous solution and whole blood. Closed-loop control is applied to stationary electrode polarography using a glassy carbon/wall-jet cell as an electrochemical detector for HPLC. The computer system monitors continuously the column eluent and determines the optimum location to perform an SEP scan. Background subtraction improves the utility of SEP to qualitative and semi-quantitative analysis for this application. A binary search optimization technique is coupled with closed-loop control to optimize staircase voltammetry using a glassy carbon working electrode. The characteristics of the charging current, resulting from a potential step at the working electrode, and the minimization of its effect on SCV analyses is examined. The charging current is found to be significant up to ten milliseconds after the potential step. This time extends as the surface of the working electrode changes. An algorithm is used which automatically determines the extent of the charging current and optimizes the data sampling time to minimize the effect of the charging current on the analytical signal. • ACKNOWLEDGEMENTS

The work described in this thesis was carried out between June 1976 and October 1978 and is entirely original except where due reference is made.

I would first like to thank my supervisor, Dr. Bernard Fleet for his advice and guidance, both academic and non- academic, during the entire research programme.

I would also like to acknowledge the Laboratory of the

Government Chemist and in particular Dr. Peter Stockwell, and Corning Medical for financial support of the projects associated with the research programme.

My appreciation is expressed to Dr. Gordon Kirkbright and the entire analytical group for the interesting discussions and helpful criticisms over the past two years. I owe particular thanks to Dr. Fred Alder who taught me to ask for a straight glass and Dr. Hari Gunasingham who often demonstrated that good results could be obtained without using computers.

Finally I would like to thank sincerely Ms Helen Moore

for help in translating this thesis from American to English. TABLE OF CONTENTS

INTRODUCTION 1 HISTORICAL DEVELOPMENT 4 CHAPTER 1 MICROCOMPUTERS 10 1.1 INTRODUCTION 10 1.2 THE MPU 11 1.2.1 REGISTERS 11 1.2.1.1 The Accumulator 11 1.2.1.2 The Program Counter 12 1.2.1.3 The Instruction Register 13 1.2.1.4 The Address Register 13 1.2.1.5 General Purpose Registers 14 1.2.1.6 The Stack Pointer 15 1.2.2 THE ALU 15 1.2.2.1 The Status Register 16 1.2.3 TIMING, AND SYNCHRONIZATION 16 1.2.3.1 The Clock 16 1.2.3.2 States and Cycles 17 1.2.3.3 Synchronization 17 1.2.4 MEMORY 18 1.2.4.1 ROM 18 1.2.4.2 PROM 19 1.2.4.3 EPROM 19 1.2.4.4 RAM 19 1.2.5 PROGRAMMABILITY 20 1.2.5.1 Instruction Set 20 1.2.5.2 Addressing 21 1.2.6 INPUT AND OUTPUT 23 1.2.6.1 Control Signals 24 1.2.6.2 Interrupts 25 CHAPTER 2 ELEMENTS OF DIGITAL LOGIC AND INTERFACING 26 2.1 INTRODUCTION 26 2.2 NUMBER SYSTEMS 28 2.2.1 BINARY NOTATION 28 2.2.2 BINARY ARITHMETIC 29 2.2.3 OCTAL NOTATION 32 2.2.4 HEXADECIMAL NOTATION 33 2.2.5 BITS, BYTES, AND WORDS 34 2.2.6 RESOLUTION 35 2.2.7 MULTIPRECISION ARITHMETIC 35 2.3 BOOLEAN ALGEBRA 36 2.3.1 BASIC OPERATORS 36 2.3.2 THEOREMS 37 2.3.3 SPECIAL FUNCTIONS 39 2.3.4 NEGATIVE LOGIC 39 2.4 DIGITAL LOGIC 41 2.4.1 GATES 41 2.4.2 DIODE-RESISTOR LOGIC 42 2.4.3 DIODE-TRANSISTOR LOGIC 43 2.4.4 TRANSISTOR-TRANSISTOR LOGIC 45 2.4.5 EMITTER-COUPLED LOGIC 46 2.4.6 CURRENT-INJECTED LOGIC 48 2.5 LOGIC DESIGN 49 2.5.1 EXCLUSIVE OR 51 2.5.2 COINCIDENCE FUNCTION 53 2.5.3 ADDER 53 2.5.4 THE FLIP-FLOP 54 2.5.5 J-K FLIP-FLOP 57 2.5.6 MASTER-SLAVE FLIP-FLOP 60 2.5.7 D-TYPE FLIP-FLOP 61 2.5.8 LATCHES 62 2.5.9 COUNTERS 63 2.5.10 SHIFT REGISTERS 65 2.6 TRANSDUCERS 66 2.6.1 INPUT TRANSDUCERS 66 2.6.2 OUTPUT TRANSDUCERS 67 2.7 DIGITAL TRANSLATION ELEMENTS 68 2.7.1 DIGITAL-TO-ANALOGUE CONVERSION 68 2.7.1.1 Weighted Current Source DAC 70 2.7.1.2 R-2R Ladder Network DAC 71 2.7.2 COMPARATORS 72 2.7.3 SCHMITT TRIGGERS 72 2.7.4 ANALOGUE-TO-DIGITAL CONVERSION 74 2.7.4.1 Counter Type ADC 77 2.7.4.2 Voltage-to-Frequency Converter 79 2.7.4.3 Dual-Slope Converter 79 2.7.4.4 Successive-Approximation Converter 81 2.7.4.5 Flash Encoding 83 2.8 ANALOGUE TRANSLATION ELEMENTS 84 2.8.1 OPERATIONAL AMPLIFIERS 84 2.8.1.1 The Ideal Op-Amp 84 2.8.1.2 Real Op-Amps 87 2.8.2 TRACK-AND-HOLD AMPLIFIERS 89 2.8.3 SAMPLE-AND-HOLD AMPLIFIER 91 2.8.4 RANGING AMPLIFIER 92 2.8.5 MULTIPLEXERS 93 2.9 TIMING AND SYNCHRONIZATION ELEMENTS 94 2.9.1 ONE-SHOT 94 2.9.2 IC TIMERS 95 2.10 PERIPHERAL INTERFACE ELEMENTS 96 CHAPTER 3 MICROCOMPUTER ASSISTED EVALUATION OF A SODIUM ION-SELECTIVE ELECTRODE 97 3.1 INTRODUCTION 97 ELECTRODES 101 3.2 HARDWARE 104 3.2.1 HIERARCHICAL COMPUTER SYSTEM 104 3.2.2 14-bit ADC 107 3.2.3 ELECTRODE PREPARATION 107 3.3 SOFTWARE 111 3.4 APPLICATION 114 3.4.1 RESPONSE TO SODIUM ION 114 3.4.2 RESPONSE TO POTASSIUM, CALCIUM, AND MAGNESIUM 116 3.4.3 SELECTIVITY OF SODIUM OVER POTASSIUM 118 3.4.4 BEHAVIOUR IN WHOLE BLOOD 118 CHAPTER 4 BACKGROUND SUBTRACTION IN VOLTAMMETRIC ANALYSIS 122 4.1 STATIONARY ELECTRODE POLAROGRAPHY 122 4.1.1 BACKGROUND SUBTRACTION 125 4.2 THE WALL-JET CELL 127 4.3 EXPERIMENTAL 130

4.3.1 MINICOMPUTER SYSTEM 130 4.3.1.1 Hardware 130 4.3.1.2 Software 132 4.3.1.3 Application to SEP 135 4.3.2 MICROCOMPUTER SYSTEM 145 4.3.2.1 Hardware 145 4.3.2.2 Software 149 4.3.2.3 Application to HPLC 156 4.3.3 HIERARCHICAL SYSTEM 160 4.3.3.1 Hardware 160 4.3.3.2 Software 160 4.3.3.3 Application to HPLC 162 CHAPTER 5 MICROCOMPUTER CONTROL AND OPTIMIZATION OF STAIRCASE VOLTAMMETRY 165 5.1 STAIRCASE VOLTAMMETRY 167 5.1.2 OPTIMIZATION TECHNIQUES 173. 5.1.2.1 SCV Optimization 174 5.2 MICROCOMPUTER SYSTEM 176 5.2.1 HARDWARE 176 5.2.1.1 Hierarchical Computer System 176 5.2.1.2 Potentiostat Design 180 5.2.2 SOFTWARE 184 5.2.2.1 Cassette Interface 184 5.2.2.2 Data Acquisition 186 5.2.2.3 VDT Display 186 5.2.2.4 Staircase Generation 188 5.2.2.5 SCV Software 190 5.3 APPLICATIONS 194 5.3.1 REAGENTS AND ELECTRODES 197 5.3.2 EXPERIMENTAL 197 5.3.3 VDT DISPLAY 204 CONCLUSIONS AND SUGGESTIONS FOR FURTHER WORK 208 APPENDIX 1 211 APPENDIX 2 217 REFERENCES 222 1 INTRODUCTION

The demands for chemical analysis have increased rapidly in most fields of science and industry. The number of samples to be analysed for a wide variety of compounds, at various concentration levels and in many diverse matrices has grown steadily in response to greater interest in environmental issues, expanded clinical services and stringent industrial quality control regulations. Many instrumental methods of analysis have been developed to cope with the increasing demand for analytical services, providing both qualitative and quantitative information at a lower cost and in less time than by manual means. The development and application of instrumental analysis is a well documented topic both in academic journals and in textbooks and, therefore, is not the subject here.

The nature of instrumental analysis, however, is changing.

The introduction of an inexpensive device, the microcomputer, which enables sophisticated control and computational power to be incorporated into conventional analytical. instrumentation is revolutionizing not only data acquisition - and data display but provoking a re-examination of the philosophy and rationale of instrumental analysis. The application of digital computers to chemical instrumentation is not new, although widespread use of digital techniques has been restrained by the high investment both in time and money required to either build or purchase the necessary equipment. The microcomputer, costing no more than several rolls of chart recorder paper, is enabling digital techniques to be employed in routine data acquisition and control situations which have not previously warrented dedicated minicomputer systems. 2 In many instances digital methods and correct application of microcomputer power can increase significantly the overall effectiveness of analytical instrumentation. Polarography, for example, is an ideal analytical technique for the application of digital methods. Data acquisition and experimental control can be handled electronically and generally do not require expensive or elaborate electromechanical transducers. Chapters 4 and 5 discuss the application of microcomputer technology in this area in more detail.

The trend towards instrumental analysis in analytical chemistry accelerated in the past decade with the introduction of integrated circuit technology, particularly the operational amplifier, which enabled the chemist with a minimal background in electronics to design and construct analytical instrumentation to meet individual laboratory and experimental needs. The drive to push detection limits lower while maintaining quantitative accuracy and precision required sensitive measurements to be made routinely and confidently. Sophis- ticated but reliable electronic instrumentation, whether purchased or built, virtually freed the chemist from the mechanics of obtaining accurate and precise data, allowing more time for, contemplation on the philosophy of the experiment and interpretation of results.

The present status' of the microcomputer in analytical chemistry is similar to that of the operational amplifier a decade ago. Early reports in the literature featured operational amplifiers, although today the device is accepted as a standard piece of laboratory equipment and is seldom high- lighted. Similarly, as application of microcomputers becomes more common, they, too, will become standard equipment and no longer receive the attention they do now.

This is not to say that the principles of digital electronics should be neglected. On the contrary, for the correct application of digital methods to analytical situations it is important to characterize accurately experimental or instrumental parameters in digital terms. This can only be accomplished if the basic principles of digital methods are clearly understood. The following two chapters present material relevant to the understanding of basic digital interfacing concepts and the relationship between the microcomputer and analogue instrumentation. 4 HISTORICAL DEVELOPMENT

The first 8-bit general purpose microprocessor was introduced in December 1971 by the Intel Corporation. Desig- nated the 8008, the 18-pin dual-in-line packaged P-channel MOS device required 60 additional components to configure an average sized system. With an instruction execution time of 20 micro-seconds, the 8008 found immediate applications in products such as computer terminals and peripheral devices. The function of microprocessors in these early applications was limited to simple tasks such as code matching, serial/ parallel data conversions, parity checking and generation, and checksum computations. The use of microprocessors in a control capacity, however, soon followed with the incorporation of microprocessors into devices for computation and control marking the beginning of the "intelligent" instrumentation era.

Within a span of seven years the one-chip microprocessor had evolved into a one-chip microcomputer requiring no additional support components, with an expanded instruction set and an instruction execution time reduced by a factor of

ten to two micro-seconds. The sudden availability of low cost, reliable control and computational devices prompted a re- thinking of the design and application of intelligent instrumentation in all disciplines.

It was in the middle of the 1960's that digital computer handling of experimental data became necessary due to the large volumes of raw data being generated by modern instrumental techniques. The union of gas chromatography with mass spectrometry, for example, required the sequential acquisition

of numerous mass spectra per chromatogram for proper 5 qualitative interpretation. A typical gas chromatogram could be composed of several hundred intensities. Early applications in this area involved direct digitization of mass spectral data onto magnetic tape for subsequent transfer to a large computer for processing (1). A similar approach was taken for the analysis of electroanalytical data by Booman (2), who demonstrated the advantages of direct digitization of experimental data over conventional analogue data acquisition..

A common feature to work carried out prior to 1967 was the physical abstraction of the digital computer from the experiment or instrument. Analogue data was first digitized, stored on some medium such as paper tape or magnetic tape, and then transferred to a computer for processing. Although this method was very successful and is in some instances still used today, it was soon realized that the rate determining step in digital data treatment involved the transfer of digitized data from the location of the experiment to the location of the computer. The advantages of moving the computer into the laboratory were pointed out in 1963 (3), although the first reports of on-line data acquisition did not appear until three years later. The incorporation of computers into chemical instrumentation was slow, primarily due to cost.

The cost of a digital computer dropped sharply with the appearance of third generation models based on integrated circuit technology. Still, the expense of a small general purpose system consisting of a digital computer, teletype and software was high, around $20,000. An investment of that magnitude was clearly out of the reach of all but the well funded establishments, and thus it was not surprising, in light of the expense, that the first reported applications of on-line data 6 acquisition were in the field of nuclear chemistry. Several papers appeared in 1966 describing computer systems at the Brookhaven Cyclotron and Rutgers-Bell accelerator (4). It was not until several years later, when the price of computer hardware had dropped even further that the number of on-line applications in the laboratory began to increase.

In addition to the initial high cost of computer equipment, the digital revolution happened so suddenly that the practising scientist realized a major gap in his technical background. The nature of much chemical instrumentation and experimentation precluded the use of generalized computer equipment, thus scientists found the need to either construct their own systems or at least be able to specify their requirements in computer terminology. Consequently, many early applications of digital computers to chemical instrumentation were variations of data logging in which the computer acquired data and presented it in some pre-defined format to the operator. Experience gained by data logging applications laid the foundation for more sophisticated computer controlled experimentation.

In 1967, Laurer et al (5), described an electrochemical data acquisition and analysis system based on a digital computer.

The $25,000 system consisting of a computer with 4096 words of memory, a 5 micro-second instruction cycle time and assembly language software, was capable of performing a number of electrochemical techniques, presenting analysed data 10-100 seconds after the completion of an experiment. The ability to complete rapidly a series of experiments and obtain both quantitatively and qualitatively correlated information proved extremely advan- tageous. Perone, Jones and Gutknecht (6) demonstrated a computer controlled discontinuous sweep stationary electrode 7 polarography experiment which enabled the analysis of difficultly reducible electroactive compounds in the presence of easily reducible species. The electrolysis currents from easily reducible species often mask or distort the polarographic waves produced by more difficultly reducible species. By interrupting the voltage sweep after detecting a- reducible species, the solution near the surface of the working electrode became depleted. Resumption of the sweep after an appropriate time interval allowed the currents from more difficultly reducible species to be detected relatively free of interferences. Rapid computer processing of data enabled the experimenters to conveniently interact with the experiment to assure that satisfactory conditions existed at all times. A 100-fold increase in qualitative sensitivity over conventional polarographic methods was claimed with quantitative analysis of 1000:1 mixtures of thallium and lead reported.

James and Pardue (7), illustrated the versatility of software controlled experimentation for reaction rate methods of analysis. Preliminary data acquisition was used to adjust data acquisition rates and other operating parameters to the optimum values for each experiment. A wide range of experimental con-

ditions were made possible without hardware or experimental changes; relative standard deviations in experimental data were held below 1%.

The introduction of the general purpose minicomputer in the early 1970's placed computing power within the reach of even moderately funded laboratories. Several reviews have since appeared describing laboratory applications of digital computers in many areas of chemistry (8-20). Articles have also appeared covering the topics of interfacing (21,22) and

software (23). 8 Applications of digital computers have been noted in all of the major branches of chemistry: analytical, biochemistry, inorganic and physical. Many instrumental techniques have been computerized as illustrated recently by articles describing automatic titrators (24-26), chromatographic systems (27- 30), applications in spectroscopy (31-44), and electroanalytical chemistry (45-55). Unique applications to ultracent- rifugation (56), thermal conductivity (57), scintillation counting (58,59) laser induced photochemistry (60), neutron activation analysis (61) and stopped-flow kinetics (62a, 62b) , have also appeared, The high speed at which digital computers operate was used advantageously by several investigators who realized the potential of controlling several instuments or experiments with a single computer (63-65). Jones and Perone (66), in 1970 designed special purpose electroanalytical instrumentation based on the results of computer-based prototypes. Such interactive equipment could not have been readily constructed without optimum parameters first defined by computerized studies.. General purpose data acquisition systems optimized for laboratory environments (65-71), educational (72-75), simulation and quality control applications (76-81) have also been described.

The number of reports concerning the direct application of microcomputers, as opposed to minicomputers, in the laboratory has been conservative. A few general papers have appeared describing the applicability of microprocessors in instrumentation (82-87, 103) and several directed towards specialized subjects: chromatography (88-94), stopped-flow analysis (95), photoluminescence (96), titration (97,98), scanning dye lasers (99), nuclear chemistry (100,101), NMR (102), Mossbauer spectroscopy (103), electro-chemistry (46,63, 104,105) and process control (106). 9 In 1971, Perone (8) pointed out that the number of papers appearing in the literature describing computer applications in chemistry was increasing exponentially. This trend does not seem to have continued with the "microcomputer revolution". The apparent decrease in the rate of new applications is primarily the result of two factors. In the first instance the use of a microcomputer in the laboratory is very much like that for a minicomputer. The conceptual interactions between macrocomputer hardware and software and chemical instrumentation are the same as for minicomputers although the specifics may differ. Consequently it does not follow that the availability of microcomputers would lead to immediate widespread use. Laboratories and manufacturers with experience in minicomputers were the first to make the transition to microcomputers and experienced users followed. With respect to chemistry, the success of the microcomputer has not been so much' the single application but rather its incorporation into commercial instrumentation. This second factor in the lack ōf reported applications of microcomputers is a result of the use of commercially available equipment employing micrcomputer control and/or data acquisition. To paraphrase Perone, the number of instruments incorporating microcomputers is increasing exponentially. Although the indirect use of microcomputers is more difficult to access the overall impact on analytical methods will be substantial. 10 CHAPTER 1. MICROCOMPUTERS

1.1 INTRODUCTION

Microcomputers can be disguised in many ways. A microcomputer may reside on a single silicon die, encased in a dual- in-line package with between 28 and 52 pins or alternatively may be a collection of two or more integrated circuits organ- ized On one or more printed circuit boards. A microcomputer may be so incorporated into the device it operates or which operates it that the essence of "microcomputerness" is lost altogether, replaced by a symbiotic quality which embraces the characteristics of each. Intelligent computer terminals, programmable ovens and other consumer goods, automated analytical instrumentation, and array processors all utilize one or more microcomputers, although identifying a particular portion as "a microcomputer" may not be straightforward.

For orientation purposes, however, a microcomputer can be generalized as a physically small electronic device which possesses all of the minimum requirements of .a digital computer, i.e: 1. It contains a micro-processing unit which incorporates both arithmetic and logic units. 2. It contains memory. 3. It is programmable. 4. It can input and output data.

Each of these requirements is discussed below.

The term micro-processing unit (MPU) is intentionally used here in place of the more ubiquitous term, central processing unit (CPU) to distinguish microcomputers from minicomputers which are also physically small. In fact, certain minicomputers 11 incorporate both microcomputers and microprocessors which only serve to make classifications more difficult.

1.2 THE MPU

Microprocessors are often confused with microcomputers, the terms being used interchangeably. The function of the microprocessor is to carry out the arithmetic and logical operations of a computer system. As a unifying element, it controls the functions performed by the other components of the system, timing and synchronization. The workings of the MPU can be described entirely as a series of READ and WRITE operations during which information is tranferred between the MPU and a particular memory of I/O location.

1.2.1 REGISTERS

Each READ or WRITE operation involves communication between a number of registers within the MPU. Although the numbers and functions of registers vary from one MPU to another, there are four which constitute the minimum configuration; the accumulator, program counter, instruction register and address register. These four registers provide the MPU with the basic information required to execute program instructions. General purpose registers, index registers and stack pointer registers contribute to the overall versatility and flexibility of a MPU but vary somewhat between manufacturers.

1.2.1.1 The Accumulator

In the general case, all arithmetic and logical operations take place through the accumulator, sometimes called the A register. The accumulator usually stogies one of the operands to be operated upon by the arithmetic logic unit (ALU) within 12 the MPU. In the case where only one operand is required, such

as a rotate instruction, the A register contains all of the information required for the execution of that instruction. It is more often the case, however, that two operands are required, for example in add, subtract and logical instructions; in this instance a general purpose register or memory location • is used in addition to the A register.

1.2.1.2 The Program Counter

The program counter is a register that contains the address

of the memory location which holds the next instruction to be executed by the MPU. The program counter is automatically incremented by the MPU to point to the N+l instruction during the execution of instruction N, unless instruction N is a jump or a call instruction.

A jump instruction, for example, incorporates the memory address of the next instruction to be executed by the MPU. During the execution of the jump instruction the contents of the program counter are replaced by the address within the jump instruction so that program control is transferred to a new location not sequential to the main program flow.

Similarly the call instruction embodies the memory address of the next instruction to be executed. The contents of the program counter are first saved in a special location, however, before the new contents are overlaid. A call instruction is usually followed at some time by a return instruction which restores the program counter with the information saved by the Call. Thus, it is possible using a combination of Calls and Returns to depart from the sequential execution of a program, continue processing in another location and then return to the 13 point at which sequential program execution was interrupted. This is the technique employed by subroutines to maintain program continuity.

1.2.1.3 The Instruction Register

The instruction register stores the instruction fetched from memory throughout the execution of that instruction. The instruction stored in this register is decoded by the instruction and associated control circuitry which causes specific activities to occur within the MPU. These activities may include information being transferred between registers or between registers and memory, arithmetic or logical operations, or I/O. Most microcomputer instruction sets contain instruction codes that are one, two or three bytes in length. Whereas many operations may be performed using one-byte codes, it is sometimes necessary to provide more than one byte of information. This is the case for jump and call instructions; one byte identifies the instruction and two bytes specify a memory address. When a jump instruction is decoded, for example, one of the activities performed by the instruction decoder is to replace the contents of the program counter with the memory address located in the second and third bytes of the jump instruction. The three-byte call instruction is functionally similar except that the instruction decoder first causes the program counter to be saved. In general, multibyte instructions are necessary when more than one memory reference operation is required.

1.2.1.4 The Address Register

The address register holds the address of the memory location referenced by the MPU. The address register differs from the program counter in that the contents of the memory 14 location specified by the address register are treated as data by the MPU rather than as instructions. The contents of a particular memory location are designated data or instructions only within the context by which the MPU sees them. It is upon this basis that instructions can be modified during the execution of a particular program segment will cause different actions to occur. For example, in the Intel 8080 instruction set an instruction which causes the A register to be rotated to the left can be masked by a logical operation upon that instruction to produce an instruction which will cause the A register to be rotated to the right. In this example the rotate instruction is treated as both an instruction and as data; its identity as such is valid only within the context of its usage.

1.2.1.5 General Purpose Registers

General purpose registers can be used to improve both ' the flexibility and speed of program execution. Most microcomputers utilize at least two general purpose registers; the Intel microcomputer line uses seven.

In many instances, data can be manipulated between regis-

ters using single byte instruction, thus simplifying program bookkeeping. Register referenced instructions encompass the same arithmetic, data transfer and logical operations as can be performed upon memory referenced data.

Faster execution times of up to 30% can be achieved with register operations since they do not require address register interactions. The time saved during the execution of a program may not warrant overzealous use of register operations if a slower but more straightforward approach is available 15 through the use of memory referenced instructions. In real- time situations where very fast processing is necessary, register operations may provide the only alternative.

1.2.1.6 The Stack Pointer

An additional register which bears mentioning is the stack pointer. Many microcomputer manufacturers allow the user to specify an arbitrary portion of memory to be used as a stack. Data can be placed on or removed from the stack without reference to the particular memory location within the stack once the stack pointer has been set. The stack pointer keeps track of the memory location which corresponds to the top of the stack. When data is pushed onto the stack, the stack pointer automatically points to the next location which then identifies the top of the stack. Conversely, when data is popped off the stack, the stack pointer adjusts accordingly. Many microprocessors use stack operations to save the program counter during the execution of a call instruction. A Call, for instance, would push the program counter onto the stack, whereas a Return would cause the contents on the top of the stack to be transferred back to the program counter. It is the responsi- bility of the programmer, of course, to ensure that the stack pointer points to the'correct data during a Return if instructions immediate to the Return involve stack operations.

1.2.2 THE ALU

The arithmetic logic unit (ALU) contains the circuitry which performs arithmetic and logical operations between registers in the CPU. Elements of the ALU include the A register, several temporary registers and at least one status register. During arithmetic or logical operations, the temporary registers hold data and intermediate results from 16 general purpose registers and memory, while the status register reflects the outcome of operations with respect to sign, zero, carry and parity.

1.2.2.1. The Status Register

The status register is used by conditional instructions whose execution depends upon the outcome of arithmetic or logical operations. For example, an arithmetic operation which results in a zero will cause the zero bit in the status register to be set. An instruction conditional upon the zero bit such as jump-if-zero-bit-set (JZ) instruction will perform a jump whereas it is ignored if the zero bit. is reset.

1.2.3 TIMING AND SYNCHRONIZATION

The MPU executes instructions one at a time. Each instruction requires a specific number of READ and WRITE operations to occur so that the MPU can acquire all of the information it needs to execute that instruction. The synchronization of these operations requires precise timing which is usually provided by a crystal oscillator based free running clock.

1.2.3.1. The Clock

The basic clock frequency governs the speed at which instructions are executed but the actual clock frequency limitations are imposed by the MPU hardware and not the availability of high frequency oscillators. The frequency range over which commercial microprocessors are designed to operate at varies between 1MHz and 10MHz. 17 1.2.3.2 States and Cycles

The basic clock frequency is usually divided by some

factor to produce a series of precisely spaced pulses. The interval between two successive pulses is known as a state and each instruction cycle is composed of a number of states. The instruction cycle time is determined by the number of states or units of processing activity required to complete the operations specified by the instruction. In some microprocessors, for example the Intel 8080A, several states are grouped together as machine cycles, thus an instruction cycle may be defined as a certain number of machine cycles in which each machine cycle is composed of several states. When determining the instruction cycle time for a particular microprocessor from the manufacturer's printed specifications it is important to understand the exact nomenclature used when inter- preting "cycle times". In the case of the 8085A, Intel quotes a machine cycle time of 330ns and an instruction cycle time of 1.32-6.08 ps (114). Cycle times may vary between instructions but the cycle time for a particular instruction is always precisely the same. The precision of instruction cycle times enables the microcomputer to be used for a multitude of real-

time situations in which timing is a critical factor.

1.2.3.3 Synchronization

Synchronization of events external to the MPU is critical to efficient processing. After the MPU has sent a signal, a READ for example, to a peripheral element, it may be required to wait for a response from the external device that occurs asynchronously. Internal logic based on the principles discussed in Chapter 2 provides the neccessary signal conditioning. 1.8 Other asynchronous events are interrupts. When an external interrupt occurs, it is first synchronized by setting an internal flag. During the execution of each instruction, the MPU checks to see if the internal interrupt flag has been set. If so, an interrupt acknowledge signal is generated and the interrupt is processed.

1.2.4 MEMORY

Memory can be considered as a series of physical locations each with a unique address where data can be stored and retrieved.

The two main types of memory in use today are magnetic and semi- conductor. Magnetic memory consists primarily of the familiar ferrite core, often referred to as simple core, and the novel solid state magnetic bubble memory devices. Although ferrite core memory is both non-volatile and permits random access t information, it has been largely supplanted by semi-conductor memory due to its low cost, low power consumption and small size.

Semi-conductor memories are either volatile, random access memory (RAM) or non-volatile, read only memory (ROM), programmable read only memory (PROM) and erasable programmable read only memory (EPROM). As the names suggest RAM data can be

randomly accessed permitting both read and write operations, while ROM, PROM and EPROM devices allow only read operations.

1.2.4.1. ROM

ROM is also known as "masked ROM" since the operations which fix the data into the device occur c'uring the masking operations of its manufacturing. Masked ROM cannot be programmed by the user although it is ideally suited for mass production. 19 1.2.4.2 PROM

PROM is designed for experimental or one-off projects which do not warrant large scale production. PROM is programmed by applying a voltage pulse of certain specifications to the programming pin located on the dual-in-lane PROM package. The effect of the pulse is to melt a fusable link within the PROM which effectively programs one bit. The links cannot be restored and a PROM cannot be reprogrammed unless the reprogram- ming operation involves the breaking of links.

1.2.4.3 EPROM

EPROM's are electronically programmable in that the programming pulse causes an electronic charge to be built up within the field effect transistors which act as data bits. Without applied power, the charges remain for many years. When exposed to ultraviolet light with wavelengths less than about 400nm, the charges are quickly leached; the EPROM is effectively erased, and can be completely reprogrammed. Exposure to direct sunlight or room level fluourescent lighting, for periods of one week and three years respectively, may cause some erasure. Protection from accidental erasing can be achieved by placing an opaque label over the transparent window of the EPROM.

1.2.4.4 RAM

Programs and data that have been thoroughly tested and de- bugged are generally placed in ROM, PROM, or EPROM for routine execution. Temporary programs and data that require frequent or real-time changes require the read/write features of RAM. There are two types of RAM, static and dynamic. 20 Dynamic RAM requires a periodic refresh pulse to maintain its contents. Static RAM does not require refreshing but con- sumes more power than dynamic RAM. Both types, however, lose their contents when the power supply is disconnected. The decision to use static or dynamic RAM depends upon the particular application. The control circuitry requirements for static RAM are far less than that for dynamic RAM although dynamic RAM is cheaper per bit, uses less power and has a higher bit density. If the memory size requirements are high enough, the extra cost and complexity of dynamic RAM control circuitry may be offset in the long run.

1.2.5 PROGRAMABILITY

A program is a sequence of coded instructions which causes a specific activity to be carried out by the MPU. The coded instructions must be stored in memory in a form that the MPU can understand and this format is referred to as machine language. Each machine language instruction defines a particular function that the MPU can perform, thus the range of basic functions available to the programmer is encompassed by the instruction set.

1.2.5.1 Instruction Set

The instruction set can be grouped into a number of

functional categories:

The arithmetic group instructions add, subtract, increment or decrement, and in some cases multiply or divide data in registers or memory. Complex mathematical functions, trigo- nometric functions and transforms must be approximated by numerical methods and implemented with the basic arithmetic

group instructions. 21 The branch group instructions alter the normal sequential program flow Tihether conditionally or unconditionally. These instructions include jumps, calls and returns which may be executed unconditionally or qualified by the status register flags indicating zero, sign, carry and parity.

The control group instructions enable or disable the MPU interrupt system, halt program execution, perform stack and index register operations, manipulate status register flags and include the "no operation", NOP. These instructions find. extensive application in real-time control programming.

The data transfer group instructions move data between registers, between memory and registers or between memory registers and I/O ports. Most commercial MPU's allow both single and multibyte data transfers which significantly lowers programming overheads.

The input/output instructions initiate data input or output operations. MPU instruction sets which do not have dedicated I/O instructions must rely entirely on memory mapped I/O.

The logical_ group instructions perform Boolean logic operations, as discussed in section 2.3 on data in memory and registers, and in some instances on status register flags. These instructions are indispensable for maiipulating data in serial and parallel, and in masking operations.

1.2.5.2 Addressing

A major contribution to computer science was made by John von Neumann who proposed that both data and instructions could be written in the same notation. The information that resides in memory is interpreted by the MPU as data or instructions 22 depending on the order in which it is fetched. The program counter always points to the memory address of the next instruction to be executed but often the addresses of additional data are required by the MPU to complete a particular operation. For example, an instruction which adds the contents of a memory location to the A register requires the address of the memory location to be added before the instruction can be completed.

The number of instruction addressing modes varies considerably between MPU's. Generally, however, the modes can be described as direct, immediate, implied, indexed, indirect, register and combined.

Direct addressing incorporates the address.of the data in the instruction. For 8-bit processors addressing a 16-bit field, this necessitates the use of three bytes, one for the instruction and two for the data address.

Immediate addressing incorporates the data into the instruction rather than an address. When the MPU executes an immediate instruction, it knows to treat the second bytes or the next two bytes of the instruction as data. Immediate instructions are generally used for storing constants which do not change throu4xut the execution of a program or subroutine.

Instructions which do not address a particular memory or register location may imply an address. For example, instructions that set or reset flag bits do not access memory or registers although they perform actions at particular locations implied in their code.

Some microprocessors use a special index register for memory addressing. The index register does not usually contain a complete address but rather a value to which another 23 value from an index instruction is temporarily added to create a. complete address. For example, if it were desired to access sequential memory locations an initial address could be first placed in the index register. The contents of an incrementing counter could then be combined with the contents or the index register to produce an incrementing memory address.

Indirect addressing refers the MPV. to a memory location that contains the address of the data sought. Thus two memory references fetches are required to acquire the data. This mode of addressing is most common to microprocessors that organize memory into pages and do not allow direct access to data in locations across page boundaries.

Instructions may also specify working registers which contain the data. The number of working registers varies between microprocessors from two to seven. In general, the accumulator is implied as a second operand in register addressed instructions. Alternatively, other registers or memory locations may be specified.

Finally, combinations of the above addressing modes may be employed. Register indirect addressing, for example, speci- fies a particular register or register pair as holding the memory address for data. Instructions using this mode of addressing achieve indirect addressing by using directly address information in a register pair thus save a considerable amount of processing time by avoiding an extra memory fetch operation.

1.2.6 INPUT AND OUTPUT

For a computer to communicate with the outside world, some

provision must be made for I/O. 24 A variety of data, address and control signals are used by microprocessors to aid in communication with peripheral devices. Signals input to the MPU carry request and status information necessary to the execution of instructions while output signals are used to synchronize and control peripheral elements. There are no hard guidelines regulating the configuration of microprocessor I/0, consequently the characteristics of a microprocessor must be carefully considered when Choosing one for a particular application. The same considerations also apply when designing an application around a particular microprocessor.

The physical size and package configurations of microprocessors limits the number of pins which can have unique assignments. Many MPU designs are, therefore, based on bus or multiplexed bus I/0. In some cases, for example, the Intel 8080 and the Motorola 6800, data and address buses are separate while in other such as the Intel 8085, the data bus is multiplexed to half of the address bus. Multiplexed bus systems enable extended control features to be incorporated into the microprocessor package at the expense of requiring more sophisticated decoding hardward. Dedicated bus systems are by and large easier implement with standard components but are limited in the amount of control flexibility that they can provide.

1.2.6.1 Control Signals

Control signals are used to turn on or gate peripheral devices and memory, provide status information about the state of the data and address bus and synchronize external asynchronous events. It is usually disasterous for more than one peripheral device to have simultaneous access to either the data 25 or address bus, as either or both devices can be damanged. This is especially true for RAM and programmable interface accessories. To avoid this problem, each peripheral device has a chip select or chip enable pin used to enable all internal functions which are in contact with the system bus. Thus the MPU can communicate with an individual device by enabling its select pin while simultaneously disabling all others.

Other control signals are used to synchronize peripheral devices with read and write operations. During the execution of an instruction, the MPU. sends out over its control bus a set of signals corresponding with memory fetch and memory store operations. The correct memory components must be selected, data and address busses enabled and read/write operations identified- in order to carry out correctly data transfers between the MPU and memory.

1.2.6.2 Interrupts

External events may occur which require the immediate attention of the MPU. One approach to cope with asynchronous external events is to have the microcomputer programmed to wait

for the event to occur. This is not the most efficient approach, however, since the time wasted by the computer waiting for the event could be used for other processing needs. A more efficient approach uses special control signals called interrupts.

During the execution of each instruction, the MPU checks to see if an interrupt has occurred. Although the exact handling of interrupts varies between MPU's, in general an interrupt causes a non-sequential instruction to be executed. Usually the instruction is a CALL which saves the contents of the 25a program counter and causes a jump to a subroutine written to process the interrupt. Alternatively, some microprocessors utilize hardware interrupts which automatically save the program counter and jump to a predefined location in memory.

A special interrupt, the RESET, initializes all status registers, clears all interrupts and sets the program counter to zero. The RESET is used to force the MPU into a known state prior to the execution of programs. 26 CHAPTER 2 ELEMENTS OF DIGITAL LOGIC AND INTERFACING

2.1 INTRODUCTION

Microcomputers manipulate numbers expressed in the number system of the Radix 2 commonly known as binary. In the binary system, all numbers are represented by combinations of two digits, 1 and 0. The selection of binary as a number system for microcomputers is based on considerations that are partly historical and partly technological.

Historically, all electronic digital computers and also much of the theory of computer science have been based on the binary number system. Considering the legacy of computer hardware, software and theory it is not surprising tAat the microcomputer has inherited a binary-based architecture. Binary is by no means the best or only system possible for the design of digital computers, but alternative systems have not yet provided much competition.

The success of the digital computer in computation and control lies in its inherent reliability and consistancy. Technically, it is far easier to design and manufacture logic circuits which discriminate two states rather than three or more states. The unambiguous nature of determining whether a value is true or false, on or off, is unmatched by analogous comparisons of intermediate levels necessary of systems based on many states.

Digital logic circuits perform operations in the digital domain on continuous values. In many instances, digital circuits can be used to appr'iximate analogue circuits with no appreciable loss in performance, and with the advantage of 27 being computer compatible. This characteristic is becoming more important as the availability and utilization of microcomputers becomes more widespread. 28 2.2. NUMBER SYSTEMS

2.2.1 BINARY NOTATION

The number 24610 can be resolved into a 2x102+4x101+6x100. If one considers the number 246 as elements of an array such that the least significant data is represented by the zeroth element of the array:

(cc2 04 0(0 )=(2 4 6) (2.1) the decimal number 24610 can be expressed as

2 24610= 0(i . 101 (2.2) i-0

A general expression for a decimal number, N, represented as n elements of an array is

N=) ' libi (2.3) i=0

where b is the base or radix of the number system.

In binary notation, b=2. The representations of 21 for i=0 to 10 are presented overleaf with their decimal equivalents. 29

BINARY DECIMAL

0 1 1

1 10 2

2 100 4

3' 1000 8

4 10000 16

5 100000 32

6 1000000 64

7 10000000 128

8 100000000 256

9 1000000000 512

10 10000000000 1024

Using relationship (2.3), the binary number 1101 becomes 1310.

2.2.2 BINARY ARITHMETIC

Binary arithmetic is straightforward. Addition of binary numbers follows the same rules as for decimal numbers; the addition of two binary l's causing a carry:

1011 0011 0011

+0101 +1100 +0111

10000 1111 1010

Subtraction is carried out by negation followed by addition. Digital computer hardware has no provision for "+" and "-" signs therefore complementary arithmetic is used to deal with negative numbers. As a convention, a negative number is identified if the most significant digit is a 1. The convention can be used. 30 freely by the programmer and does not apply in every instance.

There are two approaches to negative numbers used by computer manufacturers, l's complement and 2's complement. In l's complement a negative number is expressed as the complement of its absolute binary value, where complementation involves replacing the l's with 0's and vice versa. For example, the complement of 000111 is 111000. If however, a binary number and its complement are added the following occurs:

00101 ( 5) 11010 (-5) 11111 ( 0)

The complement of 111111 is all 0's, but according to the convention, the most significant bit instructs that 111111=-0. Furthermore, if the difference is a positive number, a carry results:

00110 ( 6)

11011 (-4) (1)00001 2

The correct result, 00010 is obtained by adding the carry to the differences.

These inconveniences can be avoided by using 2's comple ment in which a negative number is generated by complementing the binary absolute value and incrementing it by 1. Thus, to express -5: 31

Absolute value 00101 Complement 11010

Increment by 1 11011

If a negative number, identified by the most significant digit equalling 1, results from an addition, its positive value is obtained by performing another 2's complement negation. For example:

00101 ( 5) 00110 ( 6)

11011 (-5) and 11100 (-4) 00000 .( 0) 00010 ( 2) and

00100 ( 4) 11010 (-6) 11110 NEGATIVE 00001 COMPLEMENT +1 INCREMENT 00010 (+2) ABSOLUTE' VALUE

Although 2's complement notation is more convenient to use, some computer manufacturers use l's complement or no convention at all, therefore it is important for the programmer to be aware of whatever conventions are in use and treat negative numbers accordingly.

Binary multiplication and division are carried out in the conventional fashion by shifting and adding, and shifting and subtracting, respectively, e.g.: 32

100 (4) 101 101 x(5) and 100 10100 100 100

loon 100

10100 (20) 100 0

Finally, multiplication and division of binary numbers by powers of 2 can be accomplished by shifting the digits to the left or right, e.g.

101 x 24 = 1010000 1010 x 2-1 = 101

2.2.3 OCTAL NOTATION

The number of digits required to represent a number in binary notation increases rapidly with the size of the number. For example, 1024 in decimal requires 4 digits whereas the same number requires 11 in binary, 10000000000. Since the manipulation of large binary numbers is unwieldy two alternative notations are in common use which allow direct conversion of binary numbers into a more manageable form, octal and hexadecimal.

The eight digits of octal are 0,1,2,3,4,5,6 and 7 which can be represented in binary as a combination of three binary digits, 000, 001, 010, 011, 100, 101, and 111. By separating any binary number into groups of three, starting with the least significant digit, an equivalent number in octal can be expressed for example, the binary number 101010111001 can be directly translated into an octal equivalent 52718. The process is 33 illustrated below:

101 010 111 001 BINARY 5 2 7 1 OCTAL

Translation from octal to binary is accomplished in the same way:

1 3 4 6 0 OCTAL 001 011 100 110 000 BINARY

Thus:

134608 = 10111001100002

2.2.4 HEXADECIMAL NOTATION

The alternative notation whose digits are represented by four binary digits is hexadecimal based on the radix 16. The 16 digits comprising hexadecimal are 0,1,2,3,4,5,6,7,8,9, A,B,C,D,E,F. Table 2.1 contains the binary equivalents of hexadecimal digits, and also representations in octal and decimal. The translation from binary to hexadecimal and vice versa is carried out analogously to that for octal numbers, except that the binary numbers are divided into groups of four, e.g. 1010 0011 BINARY A 3 HEXADECIMAL

Both octal and hexadecimal are used by microprocessor manufacturers to describe machine language codes; the use of hexadecimal predominating since an eight bit code can be 34 represented by only two hex&decimal digits. Hexadecimal is sometimes referred to as simply HEX.

BINARY HEXADECIMAL OCTAL DECIMAL

0000 0 0 0

0001 1 1 1

0010 2 2 2

0011 3 3 3

0100 4 4 4

0101 5 5 5

0110 6 6 6

0111 7 7 7

1000 8 10 8

1001 9 11 9

1010 A 12 10

1011 B 13 11

1100 C 14 12

1101 D 15 13

1110 E 16 14

1111 F 17 15

Table 2.1

2.2.5 BITS, BYTES, AND WORDS

Microcomputers manipulate binary numbers of various lengths. The unit length is a single binary digit or bit. Eight bits are known collectively as a byte and a combination of bits and bytes is called a word. The word size of a microprocessor refers to the number of bits it can process in parallel. Most microprocessors operate with an 8-bit, or one byte, word size while several 4- 12- and 16-bit devices are also produced. 35

2.2.6 RESOLUTION

The resolution, defined as one over 2n where n is the word size stipulates that an 8-bit microprocessor can resolve one part in 256 while a 16-bit device can resolve one part in 65,536. For computational purposes it is more desirable to use a microprocessor that can work with a larger word whereas for most control applications 4- and 8-bit MPU's suffice.

2.2.7 MULTI PRECISION ARITHMETIC

An 8-bit microprocessor is not restricted from using 16- bit or larger words, although it must handle them in 8-bit bytes. Arithmetic performed with two bytes is called double precision and it is possible to program triple and multiprecision. Multiprecision arithmetic increases the resolving power of a microcomputer at the expense of added processing time. Algorithms for multiprecision programming can be found in most elementary computer applications texts. (107). 36 2.3 BOOLEAN ALGEBRA

Boolean algebra, named after the British mathematician George Boole, provides a mathanatical description of logic functions important to the operation of microcomputer systems and associated interfaces. Boolean algebra uses variables whose value can be true of false represented, for example, by 1 and 0 respectively. Three basic operators, AND, OR and NOT enable logic equations important to control logic to be expressed in accordance with certain fundamental theorems of Boolean algebra.

2.3.1 BASIC OPERATORS

The AND operator designated by the symbol "'" states that C is true if and only if both A and B are true for the expression C = A B Table 2.2 summarizes the possible values of A, B and C. Notice that the literal C is equal to 1 only when both A and B equal 1.

C = A ' B

A B C

0 0 0 1 0 0 1 0 1 1 1

Table 2.2. Truth table for the AND function

The OR operator designated by the symbol "+" states that C is true if either A or B is true for the expression, C = A + B. The truth table for the OR operator is presented in Table 2.3, 37 where again a logical true is defined as 1, and a logical false as 0.

C = A + B

A B

0 0 1 0 1 0 1 1 1 1 1

Table 2.3 Truth table for the OR function

The complement, negation or NOT operator, symbolized by a bar over the logical sense of a variable as described by its truth table, Table 2.4.

A 0 1 1 0

Table 2.4 .Truth table for the NOT operator

2.3.2 THEOREMS

The following fundamental theorems applied with the basic operators enable a wide variety of Boolean algebra operations to be performed (107):

1. Uniqueness a. The element 1 is unique b. The element 0 is unique. 38

2. Complementation a. A + Ā = 1 b. A Ā = 0

3. Involution

a. Ā = A

4. Adsorption a. A + A ' B = A b. A ' (A + B) = A

5. Idempotency a. A + A =A b. A A = A

6. Intersection a. A + 1 = 1 b. A • 0 = 0

7. Union a. A + 0 = A b. A • 1= A

8. Commutative

a. A ' B = B • A b. A + B = B + A

9. Associative a. A • (B ' C) = (A ' B) ' C b. A + (B + C) = (A + B) + C

10. Distributive a. A + g . C = (A + B) •(A + C) b. A • (B + C) = A • B + A • C 39

11. De Morgan's Theorem

a. (A + B)' = K. g b. (A B)' = Ā + B

The use of these theorems can often save significant time and effort when faced with a complex logical operation. For example, the expression (A + B)(Ā + B) reduces to simply B.

2.3.3 SPECIAL FUNCTIONS

Another function often used in the design of logic circuits

is the exclusive OR or XOR whose description is illustrated in Table 2.5. The operator XOR is given the simbol "®" and states that C is true only when A equals the complement of B, i.e. when A and B are different; C is false when A and B are the same. Equivalent representations are, C = A • B + B • A = (A + B) (A + B)

C = A • 5 + B •

A B

0 0 1 0 1 0 1 1 _1 1 0 Table 2.5 Truth table for the XOR function

2.3.4 NEGATIVE LOGIC

The defining table for the coincidence function, denoted by "9" is presented in Table 2.6. This function is complementary to the exclusive OR function and is useful in detecting, if variables are equal, whether they are 1's or 0's. 40

So far, logical true has been defined as 1 and logical false as 0. This is often called positive logic. However, it is perfectly acceptable to define logical true as 0 and logical false as 1. This is known as negative logic and its relationship to positive logic can be illustrated be considering the AND operator. The truth table for the AND operator in positive logic as presented in Table 2.2 states: The output is false unless both A and B are true or equal to 1. The positive OR function states: The output is true unless both A and B are false or 0. In negative logic the AND function becomes: The output is true unless both A and B are false or 0 which is a statement identical to that for the positive OR function. The translation between positive and negative logic causes AND functions to become OR functions and vice versa. The concept of positive and negative logic is important to the efficient design of logic systems in that the number of components required to implement design often can be minimized.

C= A• B+ Ā• B

A B . C•

0 0 1 0 0 0 1 1 1 1

Table 2.6 Truth table for the coincidence function 41

2.4 DIGITAL LOGIC

Although microprocessors are constructed with the equivalent of tens of thousands of transistors and perform over 106 operations per second, the kinds of operations performed are few. In fact, there are two basic operations: gating and counting. While there are several types of gate circuits which carry out electronically functions described by Boolean algebra, there is only one type of counting system which is based on adaptations of a basic circuit, the flip flop.

The utility of Boolean algebra to describe electronic switching theory was first recognized by Claude Shannon of M.I.T. is 1938 (112). In recent years a plethora of electronic devices have been manufactured using integrated circuit techniques which perform logic functions quickly, reliably, cheaply and silently, thus enabling almost immediately implementation of any logic expression.

2.4.1 GATES

The five basic gates and their electronic symbols are illustrated in Figure 2.1. In addition to the functions described

in section 2.3.1 are two operators, the NAND and the. NOR.

The NAND operator can be expressed as NOT•AND and the NOR operator as NOT•OR; the truth tables for both operations are shown in Table 2,6. The variable "x" in the truth table is used since its logical sense makes no difference to the output.

A logical 0 at one input of a NAND gate forces a logical 1 at the output, and a logical 1 at an input to a NOR gate forces a O at its output,. A NAND gate can have a logical 0 input only if all Of its inputs are 1, while a NOR gate can 42 have a logical 1 output only if all of its inputs are O. Both gates are used extensively in logic circuit design.

AND

A ~

NOT

NOR

Figure 2.1 The basic logic gates

2.4.2 DIODE-RESISTOR LOGIC

Electronically, logic gates have evolved from simple discrete diode-resistor devices to complex integrated circuits. A simple OR gate is given in Figure 2.2.

= A * B

A B C C

0 X 1 0 1 X 1 1 X 1 1 0 X l 0

(a) (b) Table 2.6 Truth tables for (a)NAND and (b)NOR operators

An output is observed if there is an input at either A or B. Diode-resistor gates suffer from two major problems:' first, a significant fraction of the input signal may be lose across the diodes due to their forward voltage drop (0.7v for silicon, 0.3v for germanium), and second the amount of power delivered through the diodes to the output is limited.

Figure 2.2. Diode-resistor OR gate.

2.4.3. DIODE-TRANSISTOR LOGIC

These limitations can be resolved by adding an amplifier to the output stage, as shown in Figure 2.3. In this design,

the output signal can be amplified by transistor T, although 44 the phase inversion property of the common emitter configuration illustrated inverts the original OR function to a NOR function. The extensive use of NAND and NOR gates over AND and OR gates is partly due to this characteristic. The power supply voltage for diode-transistor logic (DTL) is typically +5 volts producing logic levels of 0 and +5V. The operation of the circuit in Figure 2.3 is straightforward. If either input A or B is at O volts, the base of transistor Tl is reverse biased and the transistor is turned "off". The voltage at C is essentially +Vcc. If both A and B are at +Vcc, or +5 volts in this case, the base of T1 is strongly forward biased and the transistor is turned "on" such that the output C is essentially ground or 0 volts. Using positive logic conventions -.whereby +5 volts equals logical true or 1, and ground equals logical false or 0 a truth table for the circuit can be constructed, Table 2.7, +Vc which is identical to Table 2.6.b. c

B Figure 2.3. Diode-transistor logic (DTL)

A B C Ov (0) Ov (0) +5v (1)

+5v (1) x Ov (0)

x 2.7 +5v(1) Ov (0)

Table 2.7 Truth table for circuit in Figure 2.3 45

2.4.4 TRANSISTOR-TRANSISTOR LOGIC

One of the most extensively used forms of logic today is transistor-transistor logic, TTL, which can operate at higher speeds with.higher drive-current capabilities than DTL. A typical TTL dual input NAND gate logic circuit is illustrated in Figure 2.4, (107).

Figure 2.4 TTL Dual Input NAND gate, positive logic.

Input transistor Ql allows faster switching times. Tran- sistor Q2 is controlled by Q1, and in turn controls the operation of the output transistors Q3 and For all instances except when A and B are both logical 1, Q2 is turned on; thus the output at C equals +Vcc or +5 volts. When both A and and turns B are logical 1, Q2 is turned on which turns off Q3 on Q4 such that C is at ground. The use of the two output transistors, Q3 and Q4, provides higher operating speeds, higher capacitative drive capabilities and lower output impedances than for DTL. 46

One problem which arises with TTL logic occurs when the outputs of two devices are connected together, and the output f one device is high while the output of the other is low.. In this situation one or both devices may be damaged because their current sinking capabilities are exceeded. If a design requires connecting TTL outputs together, then open collector TTL logic shown in Figure 2.5 must be used. A current limiting register, R1 must be connected externally between C and +Vcc, to limit the drive current for transistor Q3.

Figure 2.5 TTL OPEN COLLECTOR NAND GATE

2.4.5 EMITTER-COUPLED LOGIC

Unlike DTL and TTL, emitter-coupled logic, ECL, does not use saturated transistor switching but instead uses small voltage changes to steer current within the device. The logic levels for ECL are also not compatible to TTL: logical true is usually about -0.75 volts and logical false is around -1.55 volts. In some cases a bias voltage of the order of -1.15 volts must be provided. Figure 2.6 shows an ECL NOR/OR gate. The current through transistors Q4 and Q5 are controlled by switching a constant bias current, provided by Q3, between

resistors R1 and R2. When Q1 and Q2 are turned off, Q4 is

turned off and the C NOR output is at the VBE of Q4, or-0.75 volts, i.e. a logical true. Simultaneously, the base potential 47 of Q5 is equal to the voltage drop across R2 providing the D

OR output with -1.55 volts, or logical false. When either Q1 or Q2 is turned on, current is steered from R2 to R1, Q4 is turned on and Q5 is turned off. Similarly, output D, OR becomes true and C, NOR false.

Figure 2.6 ECL NOR/OR gate

Since the logic levels in ECL operate at the characteristic voltages V BE of the transistors used, in no instance do the transistors become saturated, reducing charge storage times and increasing switching speeds. ECL can function at frequencies over 350MHz and requires special considerations when designing printed circuit boards to prevent voltage reflections at track corners from causing false triggering. The current steering approach also reduces internal noise 48 since large surge currents are avoided. The greatest disadvantage to ECL is its incompatibility toTTL and the three- voltage power supply requirements.

2.4.6 CURRENT-INJECTED LOGIC

Integrated injection logic and isoplaner integrated injection logic are two new developments which allow faster operating speeds, dense circuit packing, lower power consumption and multi-state logic designs to be achieved. 49

2.5 LOGIC DESIGN

The operation of the simplest logic circuits can be illustrated by the well worn switch analogy, in which a light is controlled by a series of switches. In Figure 2.7, for example, the light will be turned on if either switch A or switch B is closed. If the states of the switches, open or closed, and the states of the light, on or off, are tabulated, it is readily seen that the circuit performs the Boolean OR operation. Similarly, the AND operation can be simulated as in Figure 2.8, such that the light is turned on only when both A and B are closed.

Figure 2.7 Circuit to perform OR operation

Figure 2.8 Circuit to perform AND operation 50 The situation becomes slightly more complicated if the NOT operator is simulated using the same switch notation whereby a closed switch and a lighted light indicate logical true states, and an open switch and an unlighted light represent logical false states. Figure 2.9 shows a circuit which performs the NOT operation in that when switch A is closed, the current is shunted through resistor Ri to ground, and when switch A is open the current lights the light. It is easy to see that a complicated Boolean expression such as C = (A • B) + (B • A) becomes extremely involved if one is restricted to using

switches.

Figure 2.9 Circuit to perform NOT operation

Digital logic components, discussed in Section 2.4, provide a better means of implementing logic designs than switches. A solid-state circuit which controls the lighting of a solid-state light emitting diode (LED) and its truth table are presented in Figure 2.10 and Table 2.7, respectively. Using a NAND gate, the LED is switched on whenever a logical false, or low, is presented at either input, and switched off whenever a logical true, or high, is present at both inputs. The current required to drive the LED is provided through the NAND gate by its power supply. 51

Figure 2.10 NAND operated LED

B C LED

0 1 ON 1 1 ON 1 ON 1 OFF

Table 2.7 Truth table for circuit in Figure 2.10

2.5.1 EXCLUSIVE OR

The XOR function described in Section 2.3.3 can be constructed from digital logic as shown in Figure 2.11.

The truth table for Figure 2.11.a is shown in Table 2.5. Alternatively, if only NAND, NOR or NOT gates (also called inverters) are available, then the XOR can still be expressed as in Figure 2.11.b. Note that a NOR gate followed by an inverter is equivalent to an NOR gate. 52

Figure 2.11 XOR circuit with (a) AND, OR and NOT gates (b) NAND and NOT gates 53 2.5.2. COINCIDENCE FUNCTION

The coincidence function which is true if all inputs are either true or false, can be implemented with NAND gates and inverters as shown in Figure 2.12.

Figure 2.12 Circuit for coincidence function

The truth table for Figure 2.12 is found in Table 2.6. Coincidence circuits are useful for decoding purposes when it is necessary to know whether two signals are logically equal. For example, if input A in Figure 2.12 is tied to Vcc then C will only be high when B is high; and if A is grounded, then C will be high when B is at ground potential.

2.5.3 ADDER

The symbol for the XOR function is given in Figure 2.13.a. Figure 2.13.b shows an adder circuit which produces the sum and carry of two binary digits. The conditions for this circuit are tabulated in Table 2.7. The simple add circuit forms the basis for more complex addition circuits which handle multi- digit binary numbers.

A oA®B B

sum

carry

Figure 2.13 ( ) XOR symbol (b) Simple adder circuit

A B SUM CARRY

0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 1

Table 2.7 Truth table for Figure 2.13.b

2.5.4. THE FLIP-FLOP

The previous section dealt with circuits and elements which perform gating, arithmetic and logic functions. Digital logic can also be used for data storage and counting. The basic device for these applications is the flip-flop whose circuit is illustrated in Figure 2.14.

a. b.

(a) Circuit for the RS flip-flop Figure 2.14 (b) RS flip-flop symbol

The term RS refers to set-reset which describes the basic property of the flip-flop: it can be set such that Q is high or reset such that Q is low. The output Q is the complement of Q.

The flip-flop is also called a bistable multivibrator because its outputs can change between high and low and remain in either state. The operation of the RS flip-flop is straightforward and can be described with reference to Table 2.8 and Figure 2.14.

tn tn+1 S C Q Q

0 1 1 1 X NC X U

Table 2.8 Truth table for RS flip-flop 56

It is assumed that in the rest state of the RS flip-flop,

both set and clear inputs, S and C, are high or logical 1. When the clear input C momentarily goes from 1 to 0, Q is forced to a 1 which is fed back to the set NAND gate. The set input, logical 1 and Q produce a 0 at Q which is fed back to the clear NAND gate. Thus the flip-flop is locked into a state in which the Q output is 0 and the Q output is 1. Subsequent pulses between 1 and 0 at the C input will have no effect upon either output.

If the set input, S, is momentarily switched to 0 while C is in the rest state, a 1 is forced on the Q output which is fed back to the clear NAND gate producing a 0 at the Q. output. The Q output is fed back to the set NAND gate input which effectively locks the flip-flop. Subsequent pulses between 1 and 0 at S will have no effect on either Q or Q.

If the flip-flop is in a particular state and S and C equal 1, then this state will be preserved.

If both S and C are grounded, both Q and Q are forced to 1 and the state of the flip-flop is said to be undefined, i.e. Q is not the complement of Q. Of course physically, in this state, Q equals Q but this has no logical significance. If S and C are simultaneously restored to logical 1, the outputs will settle into a random configuration governed by propagation delay times and circuit differences between the two NAND gates. The Q output will settle into either a high or low state but which one could only be predicted statistically.

The flip-flop can be used as a data storage device in which one bit of information can be stored as either a 1 or a O. To store a 1, the flip-flop is set by momentarily grounding 57 the set input; to store a 0, the flip-flop is reset by momentarily grounding the clear input. The stored bit appears at the Q output and remains their until altered by a deliberate set or reset operation.

The status of the flip-flop can be represented over a period of time as in Figure 2.15.

I Q

Figure 2.15 Timing diagram for a RS flip-flop

The exact relationship between the S and C inputs, and the Q and Q outputs can be determined by inspection of the states of each at one point in time. For example, the Q output is set by the negative going edge of S and reset simultaneously with the negative edge of C. In order to count a series of negative-going pulses at the S input, it is necessary to clear the flip-flop between pulses or no change will be observed at Q after the first pulse. Additionally, a clear pulse arriving simultaneously with an S input pulse would produce an undefined state which would be useless for counting.

2.5.5 J-K FLIP-FLOP

The J-K flip-flop illustrated in Figure 2.16 overcomes

the inconvenient characteristics of the RS flip—flop by incorporating two important features: synchronous operation and

58 feedback.

J c1k K

IC Figure 2.16 Circuit for JK flip-flop

Synchronous operation is achieved with the CK input which

gates both J and K data lines. When CK is low both J and K NAND gates are disabled and forced into a 1 state, although when CK is high, the states of the gates are enabled and controlled by J and K.

Asynchronous operation which does not have any timing requirements is accomplished by using the direct set and direct reset inputs, S and C.

The timing diagram for the JK flip-flop, Figure 2.17, shows the relationship between the JK inputs and the Q output with respect to the clock which is shown as a narrow positive- going spike. Initially, J is high, K is low and Q is high.

When J goes low, point A, the output is unchanged until K goes high and Q goes low, point B. At point C both J and K are high and Q alternates between high and low with successive clock pulses. The truth table for JK operation is given in Table 2.9.

J C

Q co

0 NC 1 0 1 1 1 1 1 Qn

Table 2.9. Truth table for JK flip-flop

It is important to note that the Q output is synchronized to the clock such that input changes occurring between clock pulses are not reflected at the output until a clock pulse occurs. However, the flip-flop can be set or reset at any time using the direct set-reset input..

Figure 2.16 shows feedback of Q to K and Q to J. This configuration removes the possibility of an undefined state. since either Q or Q must always equal zeros thus the instance of all l's simultaneously at both inputs never occurs. It is usually not necessary to connect a slip-flop in the JK fashion because many integrated circuit (IC) JK flip-flops are available on the market.

Although the JK flip-flop is exceedingly useful in the pulse generating mode with both J and K inputs high, strict timing requirements must be observed to prevent the flip-flop from settling into the wrong state. For example, if Q in Figure 2.16 is low and Q, J, K and CK are high, then the 0 feedback to the K input forces a 0 at Q and the 1 feedback from

Q forces a 1 at Q. This is the normal operation when J and K are both tied to 1, but if CK remains high, the process will repeat. Therefore CK must bean impulse waveform such"that 60 its pulse width is less than the propagation delay of information through the circuit to prevent the flip-flop from settling into the wrong state.

2.5.6 MASTER-SLAVE FLIP-FLOP

The critical timing requirements of JK operation can be minimized by connecting two flip-flops together in master- slave fashion, Figure.2.18. The master and slave flip-flops are clocked out of phase with each other so that data is transferred from master to slave only when isolated from the JK inputs. Figure 2.19 represents a typical clock pulse which would be presented to CK in Figure 2.18. The clock pulse is divided into four points labelled A to D to illustrate the relationship between the pulse and the inputs to the master and slave flip-flops.

At point A the slave inputs are disabled via the inverter.

When the clock is high at point B, data at J and K are transferred to the enabled master flip-flop inputs but blocked from the slave as its inputs are still disabled. During the negative edge of the clock pulse C, the master inputs are disabled, the information on the master preserved, and the slave inputs enabled. At point D, data from the master is reflected at the slave outputs but Q and Q, although connected in JK fashion, cannot affect the master flip-flop because its inputs are disabled. In summary, the outputs of the master-slave flip- flop cannot change until the clock pulse is completed, and the master is isolated from the effects of changes at the output during the clock pulse. 61 A pre

MASTER SLAVE dk

car

Figure 2.18 Circuit. for JK master-slave flip-flop

time

Figure 2.19 Clock pulse for JK master-slave flip-flop

2.5.7 D-TYPE FLIP-FLOP

The symbol for the D-type flip-flop and its timing diagram is given in Figure 2.20. The output of the flip-flop follows the input so long as the clock is enabled, but is latched when the clock is disabled. Although both Q and Q outputs are present, there is only one input: the D or data input.

A D pre Q 62

clk

clr Q 0-

cik

Figure 2.20 D-type flip-flop and associated timing diagram

2.5.10. LATCHES

A data latch is a circuit which allows binary data to be gated to its inputs and stored on its outputs. A 4-bit data latch constructed from D-type flip-flops is illustrated in Figure 2.21. Data bits presented to the four inputs D0 to D3 are clocked to the output by a positive pulse, CK. The relationship between four hypothetical inputs and the outputs at times t before and to+l after clocking pulses is shown in Table 2.10.

Latches with master-slave or D-type characteristics of various storage capabilities can be either constructed from individual components or purchased as single integrated circuits. Most IC latches operated exclusively in the synchronous mode.

2 3 ck 2 k3 k 0 k 1

Fi (11 rr, ") i1 fl_i,; 1 63

INPUT OUTPUT to to+l

1 X X 1 D1 0 X 0 D2 1 X 1 D.3 0 X 0

Table 2.10 4-bit latch operation

2.5.11 COUNTERS

Counters are frequently used in digital logic design. Although both asynchronous and synchronous counters are usually purchased as single integrated circuits, the basis for operation is easily demonstrated by considering counters designed from individual flip-flops.

The asynchronous counter is illustrated by Figure 2.22. Constructed from.JK flip-flops which have the JK inputs tied to 1, the asynchronous counter accepts a clock pulse of frequency f applied to the first flip-flop. Pulses of frequency f/2 are produced as the Q output, which in turn are applied to the

clock of the next flip-flop such that a pulse train of a frequency of f/4 with respect to the master clock frequency results. The number of master pulses at any. time is present on the outputs Q0 to Q3 where Q0 represents the least significant bit. The propagation delay of signals though the sequence of flip-flops limits the frequency at which asynchronous counters can operate rather than the delay through a single flip-flop since the output of the last flip-flop must wait for data to ripple through the preceeding flip-flops. 64

0 1 2 J J J J ck—o clk 0 clk 1 clk 2 clk 3

K K clr clr K clr K clr

`k 1 1 1 1 1 1 1 1 1 1 1 1 . 1 1 1 1 I i 1 1 I I 1 1 111 1 1 f/2 f/4, f/8 a3 f/ 16

Figure 2.22 (a) 4-bit asynchronous counter. (b) timing diagram

This limitation is overcome by the synchronous counter, which clocks each flip-flop simultaneously, shown in Figure 2.23. The timing diagram for this counter is the same as in Figure 2.22.b, but control logic provides the correct relationships between the JK inputs of the flip-flops to produce the desired counting sequence.

CONTROL LOG IC

J J J ck ck ck ck

K clr K clr. —K clr K clr U U U U clk clr QO 01 Q2 03 Figure 2.23 Synchronous counter

It is possible to obtain counters which can be controlled to count down as well as up, count alternative pulses, count repeatedly to a desired number and perform other similar 65 counting operations. In microcomputer systems, counters are used to divide the crystal clock oscillations into timing signals necessary to the operation of the MPU.

2.5.12 SHIFT REGISTERS

A device similar in nature to the counter is the shift register, which inputs and outputs data in serial and parallel. Shift registers are used extensively in teletype interfaces and in other applications where information is generated or received in serial. 66

2.6 TRANSDUCERS

A transducer is a device which is activated by power in. one system and transfers the power in another form to a second system.. For the purposes of microcomputer control of instrumentation, the primary type of transducer is electrical. Electr.i:cal transducers which convert a non-electrical signal into an electrical one, and output transducers which convert an electrical signal into a non-electrical one. The design or availability of input/output transducers is usually a limiting factor for computer controlled experimental or instrumental analysis.

2.6.1 INPUT TRANSDUCERS

In order for a digital computer to acquire directly data about a physical event, non-electrical signals must first be converted into electrical signals. There are many types of input tranducer available of which the following list provides a few examples:

photomultiplier - light to current photodiode - light to current phototransistor - light to current F/V converter - frequency to voltage pH electrode-activity to voltage thermister - heat to resistance thermocouple - heat to voltage microphone - sound to voltage electronic tachometer - angular velocity to inductance electronic timer - time to voltage

strain gauge - pressure to capacitance shaft encoder - position to digital code 67

2.6.2 OUTPUT TRANSDUCERS

Digital control of experimentation and instrumentation requires output transduction of electrical signals, usually a current or a voltage, into non-electrical signals. The following list, although not comprehensive, provides an indication of the types of output transducers available:

stepping motor digital code to position latching valve - digital code to position CRT - voltage to light teletype - digital code to print speaker — voltage to sound resistive heater - current to heat LED - current to light VCO - voltage to frequency 68

2.7 DIGITAL TRANSLATION ELEMENTS

Most chemical experiments and instruments operate in the analogue domain, that is, control and output signals are a continuous function of time. Microcomputers, on the other hand, operate in the digital domain in which signals are treated as a discontinuous function of time, i.e. discrete values. Data acquisition and real time control of experiments and instruments by digital computers, therefore, requires the translation of data and control signals between the analogue and digital domain.

2.7.1 DIGITAL-TO-ANALOGUE CONVERSION

The digital-to-analogue converter (DAC or D2A) converts digital information into analogue information. The block diagram and transfer function for a typical 3-bit DAC are given in Figures 2.23.a and 2.23.b respectively. The basic DAC accepts a digital code and produces a current or voltage level unique for that code. The transfer function shows the output of the DAC to be a discontinuous function where for each binary input code there is one and only one'output level. The most significant bit, MSB, of the binary code is always positioned on the left of the code and has a weight of 2 of full scale; the least significant bit, LSB, is positioned on the right and has a weight. of z of full scale.

The minimum step magnitude of an n -bit DAC , or the value of its LSD, is governed by the resolution of the DAC which is defined as the full-scale range divided by 2n. Thus for an 8-bit DAC with a full-scale range of 1.00 volt, the resolution is 1.0/28 or 3.9 mV. The smallest voltage increment possible by the DAC in this example is 3.9 mV and all other outputs 69 within its full-scale limitations are constrained to integer multiples of 3.9 mV, i.e. 1 bit = 3.9 mV.

The finite transition time from one step to another due to the electronic characteristics of the device is known as the settlingtime, defined as the time elapsed between the application of a step at the input and the stabilization of the output between specified limits around. its final value. If the DAC behaves as an amplifier with an ideal, smooth 6dB per octave frequency roll-off characteristic, then the minimum time

required for the output to settle to within 0.1% of its final value following a step input is seven time constants. For example, a DAC with a closed-loop handwidth of 1MHz would require 1.1 microseconds to settle to within 0.1%. of a final value. In practice, the limits to settling times should be equal to or less than the resolution; DAC's are typically ±Z rated with an accuracy of LSB.

The relative accuracy of a DAC is not determined only by the number of its resolution bits, however, as operating conditions can significantly affect performance. Gain changes due to temperature fluctuations can cause errors several times greater than resolution uncertainties. Long term changes, power supply changes and differential linearity add to the total error figure. Careful control of experimental conditions and proper calibration techniques however, can minimize the effects of these errors. 70

D 0 output D1 D2

V+ Dn V_

offset gnd

a. FS-

314

1/2

114

l 000 001 010 011 100 101 110 111 binary input code b.

Figure 2.23 (a) basic DAC (b) transfer function

2.7.1.1. Weighted Current Source DAC

The schematic of a weighted currentsource DAC is shown in Figure 2.25. A series of transistor current sources has its collector currents governed by resistors with values of R, 2R, 4R... 2n-1R, where n is the number of bits, or logic inputs. A stable reference voltage is used to bias the bases of all of the transistors producing stable emitter currents. The transistors are switched on or off by logic inputs connected 71 to the emitters through diodes. When the transistors are switched on, current flows to the output bus which sums the currents of the transistors, and when the transistors are switched off, current flows through the diodes. Current on the output bus can be used directly, converted to a voltage by a connection to a resistor or converted to a voltage with gain using an operational amplifier.

The advantages of the weighted current source DAC are simplicity, and high speed, although some speed may be lost during voltage conversion if an OP-AMP output stage is used. The disadvantages are the wide range of resistances required. for high resolution devices, temperature effects and typically small full scale output voltage.

o 0 V2

Figure 2.25 Weighted current source DAC. MSB = most significant bit; LSD = least significant

bit

2.7.1.2 R-2R Ladder Network DAC

The R-2R ladder network DAC shown in Figure 2.26 consists of a•network of series resistors R and shunt registers 2R which can be switched between common and a voltage reference source. If a shunt register is switched to the reference source, e.g., LSB in Figure 2.26, the source sees an impedance of 2R, plus 72

2R in parallel with 2R, that is 3R. As the current flows into

each junction it divides equally to become finally part of the total current at the end of the ladder. The total output current is the sum of all the currents from the shunt resistors and may be amplified, Vout, or taken directly as a voltage, E.

V,,.-. VR1, Vom,.,, v VR/6 12 R/48

ZRR R R 2R yout 2R t 2R 2R 2R

lsb msb

Figure 2.26 R-2R Ladder Network DAC

This type of DAC has the advantages of simplicity, easy matching of resistors R and 2R, good thermal characteristics and high speed. In addition, the input impedance to the output

amplifier is always constant.

2.7.2. COMPARATORS

A voltage comparator is an analogue device with two inputs and one output, which is used to compare two voltages and indicate which is larger. For the typical comparator, the difference ,between the input voltages must not exceed limits specified by the manufacturer and the output is usually TTL compatible. The voltage comparator and its timing diagram are shown in Figure 2.27.

2.7.3 SCHMITT TRIGGERS

Schmitt triggers are related to voltage comparators except that two voltage levels, V+ and V-, determine the switching 73 points. The difference between V+ and V-, or hysterisis, provides some noise immunity in environments in which the accurate switching of the compartor is a disadvantage as illustrated in Figure 2.28. Figure 2.28 shows that the Schmitt trigger does not turn on until the V- threshold has been crossed and does not turn off until the V+ threshold has been crossed, unlike the comparator which switches each time its single reference level is crossed.

analogue input. o digital output

voltage reference

Vre f

analogue input

output

Figure 2.27 (a) Voltage comparator (b) Typical timing diagram 74

comparator reference

V- schmitt trigger output

comparator output

Figure 2.28 Comparison of Schmitt trigger and comparator ,operation in a noisy environment.

2.7.4 ANALOGUE-TO-DIGITAL CONVERSION

The analogue-to-digital converter (ADC or A2D) converts analogue information into digital information. The block diagram and transfer function for a typical 3-bit ADC are given in Figures 2.29 and 2.30, respectively (113). The basic

ADC consists of an analogue input, digital otfcputs, a start conversion input and an end of conversion output. When an analogue signal is presented to the analogue input and a start signal presented to the start conversion unit, the ADC begins its conversion. Upon completion, the end of conversion status is indicated by a change in state at the EOC output and the digital representation read directly from the digital outputs. 75

input D1 - V digital 0 V output p gnd D:n 0 0-- cony eoc —0

Figure 2.29 Block diagram for a 3-bit ADC; CONV = convert

Enable; EOC = end of conversion 111 - 110- 101- output code 100- 011- 010- 001 000 1/4. 1/2 3/4 FS analogue input

Figure 2.30 Transfer function for typical ADC.

The resolution for ADC's is defined in the same manner as for the. DAC, expressed in bits since the number of bits determines the degree of resolution. An ideal ADC cannot resolve an analogue difference less than the value of its LSB, thus the output at any point may have an error no greater than LZLSB. The ADC performs the operations of quantizing and therefore is subject to quantizing error. The output of an ADC is restricted to a finite number of discrete values and jumps from one value to another as the analogue input signal passes through its complete range. This effect is illustrated by the transfer function in 76

Figure 2.30. As an analogue signal changes in magnitude, the digital value remains the same until a vertical step boundary is crossed. The error between the true input and the output is zero at the middle of the step, has a peak value is 1,SB, and if the difference between the input and output are plotted over the input range, the resulting sawtooth waveform has an RMS value of LSBIv. Calculation of the signal-to-noise, power ratio, (S/N) of the peak-to-peak signal to the RMS noise shows that for every additional bit of resolution there is a corresponding S/N increase of 6dB. If the inherent quantizing noise of an ADC exceeds the inherent noise on the input signal, however, then this advantage will not be realized. (140)

An ADC converts an input signal into a digital value during a finite time. The conversion time is defined as the time between the start conversion and the end-of-conversion signals. Conversion times vary considerably between ADC's, depending on both the resolution and method of conversion. The conversion time is also called the aperture time, ta. Considering the analogue signal in Figure 2.31, the amplitude uncertainty, 4V, over a period of time may be defined by Equation 2.7.4.1, dV(t)to ( dt

for a sine wave of amplitude V, d (Vsin wt) ta ~V ; (2.7.4.2) dt

and at the point of maximum change, or zero crossing, AV V2Trfta ( 2.7.4.3)

In order for a 10-bit ADC with a conversion time of 5

microseconds to digitize a sine wave to 0.1% resolution, the 77 maximum frequency of the sine wave is restricted to 31Hz.

Many signals in experimental and instrumental situations are considerably, faster than 31Hz, however, and methods of reducing an ADC's aperture time are discussed in section 2.9.

time

Figure 2.31 Relationship between signal uncertainty, V, and aperture time, ta.

2.7.4.1 Counter Type ADC

The most straightforward ADC design is the counter type shown in Figure 2.32 which consists of a comparator, a clock and a counter. An analogue signal is presented to one output of the comparator and the output from the DAC to the other.

When the start conversion signal resets the counter to zero, the counter starts counting up and presents a digital input to the DAC. The output of the DAC increases until it exceeds the level of the analogue input signal, the comparator changes state and control logic generates an end-of-conversion signal. The value of the counter at this point is proportional to the magnitude of the analogue signal: the larger the signal, the larger the count. The maximum conversion time is equal to the maximum count times the clock frequency and is not constant. 78 A continuous counter converter can be constructed using an up-and-down counter controlled by the output of the comparator. The direction of count is then a function of the relative magnitudes of the DAC and comparator and in operation provides a continuous digital representation of a changing analogue signal as shown in Figure 2.34. eoc a control o analogue ov a logic input

clock up DAC counter

cony o 0000b msb lsb

Figure 2.32 Counter type ADC analogue signal

DAC

comparator Figure 2.33 Timing diagram for counter ADC

Figure 2.34 Analogue signal and DAC output for a continuous counter ADC 79 2.7.4.2 Voltage-to-Frequency Converter

A common type of ADC used in many digital panel meters and instruments is the voltage-to-frequency converter. The basic components include an integrator, a comparator with a reference voltage, a fixed-time logic controller, a charge pump and a counter. The input signal is integrated at the first stage and when.the output from the integrator exceeds the reference voltage, the comparator switches state and discharges the integrator through the charge pump. The comparator returns to its rest state, the integrator is re-charged, and the cycle repeated. The frequency of the pulse train output from the comparator is a function of the rate of integration, i.e. the magnitude of the input signal. The pulse train from the comparator is used to drive a counter for a fixed period of time, thus the magnitude of the count is proportional to the frequency of the pulse train which, in turn, reflects the magnitude of the input voltage.

Short period integration of the input signal providing some high frequency noise rejection over long periods of time makes the voltage-to-frequency converter useful For digitizing low level signals of a few millivolts at low frequencies.

2.7.4.3 Dual-Slope Converter

The dual-slop converter is similar to the voltage-to- frequency converter except that the signal is integrated over the entire measurement interval rather than over short periods. Conversion begins when the integrator is switched to the input signal. The integrator capacitor charges up for a fixed time interval, usually equal to 2n times the clock frequency for an n -bit converter, at which point the integrator is switched

to a reference voltage of opposite polarity. The integrator discharges at a fixed rate to zero, detected by a zero-crossing detector which stops the counter through control logic. The output of the counter is proportional to, the input voltage by equation 2.7.4.4.

T2 EIN T REF ( 2.7.4.4 ) 1 where T2 and T1 are the integrating times of the reference source and signal respectively; and V„F is the voltage reference.

The conversion time for the dual-sloprADC is equal to the sum of both signal and reference integrating times and, therefore, varies with the magnitude of the input signal. Conversion times of about four conversions per second for full scale signals are typical.

___11 integrator

47- electronic '--0 switch input ', o control oeoc cony o logic clock counter ww

Figure 2.34 Dual-Slope Integrating Converter 81

k- t1- -1.2 ---'1

Figure 2.35 Timing diagram for dual slope converter; Ti = signal resetting time; T2 = reference integrating time

Dual-slope ADC's are particularly useful in high-noise environments for digitizing low-level signals at low frequency. Specific applications include digital panel meters and pH- millivolt meters.

2.7.4.4 Successive-Approximation Converter

The successive-approximation ADC has both high resolution and speeds but does not use a counter. The components, shown in Figure 2.36, consist of a digital pattern generator, a DAC, a comparator, and a clock. In operation, a digital code from the pattern generator turns on the MSB of the DAC. If the output of the DAC is greater than the input signal, the next code generated reduces the DAC's output by half by turning off the MSR and turning on the next significant bit; otherwise the MSB is left on and the next significant bit turned on, so increasing the output of the DAC by half. This process repeats for each. bit to the LSB; the conversion time is equal to the time required to process each bit times the number of bits and is constant for each conversion regardless of the magnitude of the input signal. The generator code after the LSB has been 82 processed is the digitized value of the input signal. Figure 2.37 is a typical timing diagram for a 4-bit successive approximation ADC.

DAC ref

programmer chock input 0

output register

Figure 2.36 6-bit successive approximation ADC

3/4 signal

1/2

1/4

Figure 2.37 Timing diagram for a 4-bit successive

approximation ADC 83

The advantages of successive approximation ADC's are short conversion times, typically 0.4 - 2ps, combined with high resolution, typically 8 to 12 bits.

2.7.4:5 Flash encoding

Parallel conversion or flash encoding ADC's, capable of conversions at rates of about 25MHz for four bits, are based on 2n-1 comparators each biased one LSB apart, operating simultaneously in an n-bit converter. Although they are particularly useful in situations requiring high-speed conversions, parallel converters tend to be both expensive and offer low resolution, typically 3 to 8 bits. 84 2.8. ANALOGUE TRANSLATION ELEMENTS

2.8.1 OPERATIONAL AMPLIFIERS Operational amplifiers, or op-amps, were first used in the computing field as amplifiers that performed various mathematical functions. The observation that negative feedback applied around a high gain DC amplifier would produce a circuit with a specific gain characterized completely by the type of feedback used enabled designers with minimal experience to build useful and versatile circuits. Feedback components could be selected to construct circuits which could, for example, add, subtract, multiply, divide, integrate, differ- entiate and average.

The application of op-amps to instrumental design is well represented in the chemical literature of the mid-1960's and has now become a standard practice (112).

2.8.1.1. The Ideal Op-Amp

The relationship between gain and feedback components in op-amp circuits is based on the characteristics of an ideal op-amp, which are: _

1. Infinite gain (A) 2. Infinite input impedance (Zi) 3. Zero output impedance (Zo) 4. Zero response time 5. Zero offset between inputs and output 6. Zero drift 7. Infinite bandwidth

The basic open loop amplifier circuit is shown in Figure 2.38. The inputs have infinite impedance and hence draw no current, therefore, there is no voltage drop across Rs. If 85

Es is zero, the output is zero; and if Es is any other value, the output increases rapidly to saturation since the gain of the amplifier is inifinite. The open loop circuit is of limited utility restricted to switching and voltage comparison applications.

Figure 2.38 Basic open loop op-amp circuit; Rs = source

resistance; RL = load resistance; Es = source voltage; V = supply voltage.

Figure 2.39, the voltage follower, is the simplest circuit employing negative feedback. When negative feedback is applied around the ideal op-amp, the differential input voltage Es becomes zero.

In this configuration the output, Ec, of the op-amp is defined as minus the product of the gain, A, and the differential input voltage Es. Therefore:

(. 2.8.1.1) -AE s

(2.8.1.2)

From Kirchhoff's voltage laws:

E' = El + Es ( 2.8.1.3) 86 and substituting 2.8.1.2 into 2.8.1.3 yields E (2.8.184 ) Eo E A

If A is infinite

Eo = E (2.8..1.5)

The input impedance of the ideal voltage follower is infinite, the output is zero and the output voltage is equal to the input voltage. Thus the voltage follower can act as an impedance buffer in circuits which require zero-current voltage measurements.

A large proportion of op-amp circuits use the inverting amplifier configuration shown in general form in Figure 2.40.

Figure 2.39 Voltage follower

Figure 2.40 Inverting amplifier; Zi = input impedance Zf = output impedance

87 From Kirchhoff's current laws:

( 2.8.1.6 )

but the ideal op-amp does not draw current, therefore is = 0. Also E s ii = ( 2.8.1.7 )

and

( 2.8.1.8 )

Using the definition of infinite gain and equation 2.8.1.2, Es = O. Therefore, E. -E 1 = o (2.8.1.9 ) z. Z 1 o and- rearrangement gives . Eo = E.Zf (2.8.1.10) Z.i The output voltage for this circuit is equal to minus the input voltage times the ratio of the feedback-impedance to the input impedance.

2.8.1.2 Real Op-Amps

The relationships derived using the characteristics of an ideal op-amp hold to within certain tolerances for circuits using real op-amps as well. Although the specific characteristics vary considerably between real op-amps, the typical values quoted overleaf can be used to describe an average op-amp: 88

1. Gain: 105 2. Input impedance:. 106 OHMS 3. Output impedance: 100 OHMS 4. Response time: 400 ns 5. Offset: 5 m 6. Drift: 2 011V/°C 7. Bandwidth: 20MHz

The deviations from ideal behaviour are not as great as may first be expected. For example, substitution of finite gain into equations 2.8.1.2, 2.8.1.7, and 2.8.1.8 leads to the relationship

E. + Eo/A = -Eo - E/A (2.8.1.11) Zf which upon rearrangement becomes Eo = -E (Z /Zi) i f 2.8..1.12 ) 1+A(1+Zf) i For a Zf to Zi ratio of 100, the percent error between real and ideal behaviour is only 0.01%. Furthermore, in order to maintain an accuracy of 0.1%, the ratio of.AZ1 to Rf should be greater than or equal to 103.

The input impedance-of real op-amps is described in terms of common mode, CM, and differential mode, DM, impedances as illustrated in Figure 2.41. The differential mode impedance is between the two inputs whereas the common mode impedance is between each input and ground or common. The common mode rejection ratio, CMRR, is defined as the ratio of the difftir- ential mode. gain to the common mode gain. If the inputs of the amplifier in Figure 2.41 are tied together and a small voltage applied, a voltage will appear at the output since the CMRR is 89

not ideal. A differential voltage typically' five orders of magnitude less applied between the inputs can produce the same output voltage as that in the common mode case. The CMRR'is an indication of the ability of an amplifier to reject a signal common to both inputs and is generally expressed in decibels; typical values lie between 70 and 120dB.

Figure 2.41 Representation of common mode Rcm, and differential mode, Rdm, impedances

2.8.2 TRACK-AND-HOLD AMPLIFIER

Track-and-hold, T/H, amplifiers are used to shorten the aperture times of ADC's by rapidly sampling the input signal and holding its value until conversion is completed. Referring to Figure 2.42, an electronic switch is used to gate the incoming signal onto a storage capacitor. When the switch is closed, the capacitor charges up to the voltage of the incoming signal and track it. When the switch is open, the capacitor retains the voltage of the incoming signal prior to the switch opening. 90

output

input

electronic switch t/h

Figure 2.42 Track-and-hold amplifier.

The operation of a T/H amplifier is illustrated in Figure 2.43 in which a logical 1 causes the switch to open,3 and a logical 0 causes it to close.

Track-and-hold amplifiers are characterized basically by three important parameters: acquisition time, aperture time and droop rate. The acquisition time is defined as the time required for the amplifier output to slow to and remain within a specified error band around the input value. Acquisition times vary between 0.035 and 4.0 microseconds (113).

The aperture time refers to the time elapsed between the application of a hold command and the complete opening of the switch between the input and output amplifiers. Aperture times for T/H amplifiers which are much shorter than for ADC's vary between 0.2 and iOns.

The droop rate is the maimum change in the output signal with time in the hold mode. Droop rates are greatest for ultra- fast T/H amplifiers and vary from around 20nV/us to 50pV/jzs. 91

signal

t/h output 1 - 0

Figure 2.43 T/H amplifier operation; 1 = track; 0 = hold

2.8.3 SAMPLE-AND-HOLD AMPLIFIER

The sample-and-hold amplifier S/H, is functionally similar to the T/H amplifier except that a provision is made for shorting the holding capacitor to ground. The operating characteristics of the S/H amplifier are similar to those of the T/H amplifier. The circuit and timing diagrams for the S/H amplifier are shown in Figure 2.44.a and 2.44.b.

output input sample/hold -r>__ -

signal

s/h 1 0

Figure 2.44 (a) S/H circuit (b) timing diagram 92

2.8.4. RANGING AMPLIFIER

A ranging. amplifier as shown in Figure 2.45 allows various gains to be digitally selected, thus enabling the user to either increase or decrease the dynamic range of a sampling system. The circuit consists of an op-amp in the inverted-gain configuration with solid state switches used to control the value of the feedback resistance. The amplifier can be controlled - by discrete logic or directly by a microcomputer to amplify or attentuate input signals which are outside normal operating ranges.

An automatic ranging amplifier was recently used by Hoffman and Pardue (108) to improve the signal-to-noise characteristics of a vidicon-based rapid scan spectrometer.

By autoranging it was possible to take advantage of the intrinsic dynamic range of the silicon target vidicon of four orders of magnitude.

a digital inputs

input

Figure 2.45 Ranging amplifier 93

2.8.5 MULTIPLEXERS

A multiplexer (MPX) has several inputs each of which may be switched at random to one output. Multiplexers are useful in situations which require the sequential sampling of several input signals by one device. For example, the outputs of a number of GC detectors could be multiplexed to a single ADC, rather than providing each GC with its own ADC, reducing significantly the hardware requirements of a GC-computer monitoring system.

Multiplexers for both digital and analogue signals can be constructed or purchased. .94

2.9 TIMING AND SYNCHRONIZATION ELEMENTS

It is often convenient and sometimes necessary to use hardware timing elements instead, of direct software control. In many instances, the precision and simplicity of software timing routines is offset. by the real-time constraints imposed Upon other processing needs. A processor tied-up in a wait loop, for example, is generally not available for other arithmetic or logical operations which may be pending. In other cases, however, the nature of the experiement or instrument under control may be such that further processing is

unnecessary until certain timed events occur; software timing may then be more straightforward to implement than hardware. There are a number of devices designed for timing applications which are simple to use and warrent consideration when designing computer-instrument interfaces.

2.9.1. ONE-SHOT

The one-shot or monostable multivibrator has one stable state, either high or low. When a pulse is applied to the input, which is usually edge sensitive, the output changes state for a period of time usually determined by an external RC circuit, then returns to the stable state. As is shown in the timing diagram, Figure 2.46, triggering during the unstable. state has no effect on the output. One-shots can be programmed with pulse widths from approximately 40 nanoseconds to several minutes; precision is limited by the tolerances of the external RC timing elements. 95

trigger

Figure. 2.46 One-shot, OS, timing diagram

2.9.2 IC TIMERS

There are a large number of integrated circuit timers which can be purchased to perform both simple and complex timing operations. The 555 timer, for example, can be used as a one shot, comparator, zero-crossing detector and free-running oscillator as well as a timer. Although both the one-shot and the 555 timer uses an external RC timing network, the 555 can be configured not to change state after a trigger pulse but at the end of the specified interval.

Other IC timers do not rely on an RC timing network but rather a pulse train from a free-running oscillator or precision crystal clock. Programmable timers, for example, allow a timing interval to be coded digitally and stored within the timer. An internal counter then increments with each clock pulse until the value of the interval is reached.

One or more timers are usually incorporated into one-chip microcomputers as an added feature. Such timers are programmable and operate from either the microcomputer's crystal clock or an external soace. As well as providing timing facilities, one-chip timers can serve as event counters in control applications. 96

2.10 PERIPHERAL INTERFACE ELEMENTS

Much of the work involved in interfacing microcomputers to experiments, instrumentation and peripheral devices has been lessened in recent years by the introduction of programmable peripheral'interface elements. These are large- scale integrated circuits which perform all. of the computer/ interface timing and synchronization operations and many of the interface/peripheral operations as well. Programmable interfaces relieve the systems software of many of the bookkeeping, I/O and timing functions common to any computer/. peripheral system. Peripheral interface elements fall into two categories: general, including communications interfaces, interval timers, general purpose, and interrupt control; and dedicated, including floppy disc controllers, CRT controllers, keyboard interfaces and data encryption units (114). 97

CHAPTER 3 MICROCOMPUTER ASSISTED EVALUATION OF A SODIUM ION-SELECTIVE ELECTRODE

3.1 INTRODUCTION

The application of ion-selective electrode (ISE) potentiometry to chemical analysis has become popular recently with the availability of low-cost, accurate and robust sensors; new electrode materials and methods have been reported fre quently in the literature. In an early review, Ross noted there was a "growing awareness" that measurements of chemical activity were of equal, and sometimes greater, importance to concentration measurements. (141)

The roles of sodium and potassium in physiological processes, for example, are largely determined by their free ionic activity which may vary by several percent from their total concentration. Whereas flame photometry, the standard procedure for analysing sodium and potassium, yields a concentration measurement, the activity can be quickly and easily determined using the appropriate ISE.

The most successful type of ISE in terms of applicability, sensitivity, response time and selectivity are the membrane electrodes which include glass electrodes, liquid-membrane electrodes and solid-state precipitate electrodes. Figure 3.1 illustrates the apparatus comprising a membrane electrode

measurement system. Ideally, the sensing membrane permits one ionic species to pass from the sample solution to an internal solution; the migration of interfering ions is opposed. The momentary flux of ions across the membrane from the solution of higher activity to the one of lower activity of the mobile ion,.sets up an electrical potential which opposes further

98 migration. Once equilibrium is established the potential across the membrane prevents further net movement of ions. The membrane potential can be measured as a potential difference between a reference electrode internal to the ISE and an external reference electrode in contact with the sample solution. This potential, E, can be related to the activity, a., of the mobile ion by a form of the Nernst equation (139),

E = constant + RTln(a) (3.1) nF where the constant is a collection of terms representing the standard chemical potentials and activities of the reference solutions; this form of the Nernst equation is valid for the equilibrium established at the membrane/solution interface represented as. membrane • ion ion (3.2)

voltmeter ISE REF internal half cells

ISE membrane liquid junction

sample solution

Figure 3.1 Membrane electrode system. 99

A significant parameter for a membrane electrode is its selectivity over interfering ions. For several competing equilibria the potential, E, in equation 3.1 can be described as a function of the sum of the activities of the mobile ions such that

E = constant +2 RT (a) (3.3)

For ions of the same charge, this equation can be rearranged to

E = constant + nFln (a) 3.4)

The selectivity of the membrane is described by a weighting factor which relates the relative contribution of each activity in the summation term. The Eisenman-Nicolsky equation relates the selectivity. of ion i over ion j in, the following relationship E = S In (ai + K13. .a.) (3.5) where S is a collection of terms approximating the Nernstian coefficient RT/nF, (usually determined empirically), and K is the selectivity ratio of the membrane for i over. j. The selectivity ratio can be evaluated experimentally by constructing a calibration graph for species i in the presence of a fixed concentration of j. The slope of the calibration

curve is controlled by the slope factor S until the . .a surpasses the magnitude of the product of the term K13 3 activity of i at which point the curve becomes horizontal with the potential approximated by E = constant + S in K. (3.6)

As illustrated in Figure 3.2, the intersection of the two straight line portions of the graph describe the condition where equation 3.6 is equal to equation 3.1 so that 100

-.350 —

-.325 —

-.300 — -.275 — E -.250 - ( v) -.225 —

-200 — -.175 —

-. 150 —

1 1' -6 -5 -3 10 10 10 10 10-2 10-1 CI

Figure 3.2 Determination of the selectivity coefficient S InKi.a. = S in a. and K can be defined as

a. K - 3.8) ij a.

The graphical solution of the value of K is much more reliable than the use of measurements in pure solutions of the individual ions since it simulates real analytical situations. The selectivity coefficient is often represented as a pK value such that a hundred-fold selectivity of -.01 is equal to a pK of 2.

3.1.1 SODIUM AND POTASSIUM MEMBRANE ELECTRODES

The wide applicability of ISE potentiometry to the analysis of sodium and potassium has been documented in. several reviews. (142 - 144) An often cited application is the measurement of blood electrolytes which for sodium and potassium is carried out routinely by flame photometry; a well established and highly automated method. The elimination of the flame from the analysis of sodium and potassium by substituting ISE measurements would enable analyses to be performed in environments where open flames are prohibited, ie. operating theatres and intensive care wards. The work by Eisenman and co-workers in the development of sodium electrodes has clearly defined the limits attainable in the direction of glass membrane sensors (145). The limitations of these sensors stems from poor response times, low precision in physiological environments and high 102 drift characteristics. An alternative approach has been towards liquid ion-exchange membranes.

The combination of liquid ion-exchanges and polymeric membranes has opened up the field of ion-selective electrode technology. Polymeric ion-selective membranes can be constructed consisting of a polymer matrix, a plasticizer and ligand; polyvinyl chloride (PVC) has been shown to be a particularly versatile polymer for these applications (146). A variety of electrode designs can be utilized by casting PVC membranes in the shape of discs or tubes, or coating solid supports such as wires and unglazed ceramics: The choice of the ligand to be incorporated into the membrane is particularly important.

Numerous ion exchanges have been examined as possible ligands for ions such as sodium, potassium, calcium, lead and nitrate although the poor selectivity exhibited by these devices severely limits their applicability (141).

The substitution of naturally occurring ligands as the ion-selective agent has overcome many of the inherent disadvantages of ion-exchange materials; the potassium valinomycin

electrode is the classic example, exhibiting both high selectivity towards potassium and low response time (156) .

Recently, Simon and co-workers have synthesized neutral. carrier ligands based on the properties of naturally occurring

ligands which are designed to be, selective to specific ions Cā2+, Mg2+ (147). Ligands for K+, Na+, Ba2+, and NH4+ have been produced (148 - 153) and several theoretical descriptions of the behaviour of neutral carrier membranes have been put

forward (154-156). 103

The sodium selective neutral carrier ligand developed by

Simon is of particular interest because of its comparatively high selectivity over potassium. This is an important consideration to physiological measurements since the potential response over the typical potassium concentration of 3.1 to 5.5 mM is nearly five times that for sodium at 135 to 155 mM. Considerable errors in sodium activity measurements can occur if an electrode with poor selectivity over potassium is used.

In this work, the neutral carrier illustrated in Figure 3.3 was incorporated into a PVC based membrane electrode of the type used by Band and Treasure (157) and evaluated with respect to its selectivity to potassium. Measurements of small potential changes were aided by a microcomputer controlled data acquisition system specifically designed for use with ISE's. The discussion of the electrode evaluation is divided into three parts including a description of the hardware used, the controlling software and applications.

Ō ~ Ō

Figure 3.3 Sodium selective neutral carrier ligand 104

3.2 HARDWARE

Computer controlled monitoring of potentiometric analysis with ISE's'has been described for both static solutions (158, 159) and flowing streams (160). In addition to direct measurement techniques, computer control has been applied to automated titration (161, 162) and end-point detection (163). In one instance, real-time feedback has been used to optimized an on- line matrix matching analysis in which a control solution was altered in concentration to yield an ISE signal equal to that from a solution of unknown concentration (164).

The use of microcomputers can provide to some experimental problems solutions which would be otherwise overly complicated to effect. In this study, a hierarchical computer system was used as a simple data logger to record measurements from selectivity experiements involving a sodium sensitive membrane electrode. The experiments required that signals from the electrodes be acquired at intervals of one second and a moving average maintained. Additionally, the system was to calculate the slope of the electrode response versus time and determine when the slope was stable to within 1%. The location of this plateau region was to be noted and the electrode signal identified as being the 'final value'.

3.2.1 HIERARCHICAL COMPUTER SYSTEM

The block diagram in Figure 3.4 shows the hierarchical computer system used to acquire and display data from the electrode selectivity experiments. The system consisted of a minicomputer (Computer Automation Alpha-16) interfaced to a teletype (ASR 33), and a micro-computer (SDK-80, Intel Corporation) interfaced to the Alpha-16, a VDT (EAL C-101) and a 14-bit dual 105 slope ADC (Analog Devices 1105-K).

The Alpha-16 had 8k of ferrite core memory and was interfaced to the teletype via a 110-baud serial link. The SDK-80 had 256-bytes of RAM and used three interfaces to its peripherals: an 8-bit parallel link to the Alpha-16, an 18-bit parallel interface to the ADC and a 330-baud serial link to the VDT.

The interface between the Alpha-16 and the SDK-80 consisted of address and function decoding logic for the Alpha-16 I/O architecture, and handshaking logic for data transfer to the

SDK-80. The SDK-80 communicated to the interface through an 8255 Programmable Peripheral Interface chip which was configured by software (166). The interface between the SDK-80 and the 14-bit ADC was through a second 8255 chip also configured by software. The schematic diagram in Figure 3.5 shows the data I/O between the ADC and the 8255. Sixteen lines were used to input the 14 data bits, polarity and overflow bits from the ADC, one line to input the EOC and one line to output the CONY. 106

n t C r ALPHA-16 SDK-80 <-> a 14-bit ADC e

ISE cell tty vdt

Figure 3.4 Hierarchical computer based data acquisition system.

port A0 bit 0

analogue in A 7 r bit 7 bit 8 B0

B 7 4 bit 15 (+1-) CO eoc C4 cony

8255 1105 K

Figure 3.5 Schematic diagram for ADC interface. 107 3.2.2 14-BIT ADC

The ADC used in this study was selected on the basis of two criteria: resolution and noise rejection. In order to resolve 3% of the potential response of the sodium ISE over the physiological concentration range, approximately 0.1 mV, 14 bits of resolution over a 1V range were required. The LSB for the ADC over this range actually represented 0.06 mV.

Elimination of high frequency noise was achieved by selecting a dual-slope ADC which integrated the input signal over the entire sampling interval.

The input to the ADC was buffered by a FET op-amp in a voltage follower configuration with an estimated input impedance of 1015 ohms.

The reference electrode and all electronic grounds were connected to one point and all electrode connections were made using shielded co-axial cable. Random background noise was measured as less than 0.04 mV p-p.

3.2.3 ELECTRODE PREPARATION

The electrode and cell-chosen for selectivity measurements were based on the designs of Band (157) as shown in Figure 3.6. The sample solution (200 p1) was injected into the cell chamber and the outflow brought into contact with the reference electrode junction (Corning double junction reference electrode, CaCl2/KC1).

The electrochemical cell studied was HgIHg2C12IKC1(sat)II

CaCl2(0 . IM) I (sample solution I membranel NaCl (0 . 1M) I AgCl I Ag.

The electrode construction is. shown in Figure 3.7. The 108 basic electrode consisted of a liquid membrane-coated ceramic plug in contact with an internal reference solution and electrode. A typical electrode was constructed as follows: 1. An unglazed ceramic plug 1 mm in diameter by 3 mm was inserted into a 9 cm length of PVC tubing (i.d. lmm) such that 1 mm of the plug remained exposed.

2. The exposed edge of the plug was rounded using fine- grained emery paper.

3. A 9.5 cm length of bi-lumen nylon tubing (o.d. lmm)

was inserted into the PVC tubing to within 1.5 cm of the ceramic plug. The bi-lumen tubing, which contained the Ag/AgCl reference electrode in one lumen, enabled the space behind the plug to be filled with reference solution via one lumen while allowing an exit route for trapped air via the other lumen.

4. The electrode was dipped into a membrane mixture such that the mixture sealed the plug.

5. A PVC mounting washer was fixed near the end of the electrode to enable a solution tight seal to be made

in the electrode cell.

6. A 10cm length of 30 AWG varnished silver wire of which 2cm was stripped and anodized in a 0.1M NaCl reference solution was inserted into one lumen.

7. The electrode was filled with 0.1M NaCl reference solution by injecting enough solution down one lumen to force out any air trapped in the end of the

electrode of in the plug itself. 109

ISE membrane ceramic plug .

outflow 4---

— internal sample in didig 1111111111111 reference electrode

Pr PVC washer PERSPEX jackets

Figure 3.6 Band-type electrode cell.

internal reference ISE solution . Ag wire membrane

ceramic outer tube plug bi-lumen tube PVC washer

Figure 3.7 Electrode construction. 110

The membrane composition used was 1.0% (WW) ligand, 65.9% solvent (THF, tetrahydro furan), 33% PVC and 0.1% N a SCN. All reagents were reagent grade and used without further purification.

Fielder has reported that the membrane composition can affect the selectivity of the electrode (167). In her study the effects of various solvents on a membrane composition similar to the one used in this work was documented, although THF was not mentioned. In four of the five cases cited the selectivity of sodium over potassium was approximately 0.25+0.1; the best case was KNa/K = 0.17. With respect to selectivity over potassium reported, the advantage of using the optimized solvent was not significant.

The relatively high selectivity of sodium over potassium for the ligand described in Figure 3.3 precluded optimization of the membrane components in this study. 111

3.3 SOFTWARE

Two sets of software were written to control the data acquisition/display system: one in Computer Automation Assembler and the other in Intel 8080 machine code. The software for the Alpha-16 was designed to initiate data acquisition, read data from the SDK-80, display the data on the teletype and print a message when ten consecutive data points were within a range of 1%. The one percent range indicated that the electrode was stable and equilibrium had been established.

The software for the SDK-80 was designed to receive an 'initiate' message from the Alpha-16, start an ADC conversion once each second, sense the EOC and read the ADC data lines, mask the polarity and overflow bits and transmit to the Alpha-16 a 14-bit integer signed in 2's compliment notation.

In operation the SDK-80 program first configured the two peripheral interface chips by writing the relevant control byte to the appropriate chip.

The chip designated 8255-1 was set up to communicate with the ADC thus the two 8-bit ports A and B were configured as inputs for the ADC data bits; 4-bits of port C were configured as inputs and the remaining 4-bits as outputs although only one bit from each half was used.

The chip designated 8255-2 was set up to communicate with the Alpha-16 by configuring port A as bi-directional; the handshaking logic was controlled by hardware. The interrupt output from 8255-2 was linked to the interrupt input of the 80P0 microprocessor to enable the Alpha-16 to interrupt the SDK-80 by simply writing to the interface. 112

Once the SDK-80 was initialized, the program idled in a loop until an interrupt signal was sensed. Then, a bit was written to port C of 8255-1 to start an ADC conversion and a one-second wait loop entered. Upon exiting the wait loop, the EOC bit was. read from port C of 8255-1 and if the bit was not set an error message (bit 14 set) was sent to the Alpha-16. Since the maximum conversion time for the ADC was well below one second, the failure of EOC to be set would indicate that a hardware error had occurred. If EOC was set, the two data bytes were read from ports A and B of 8255-1. The overflow bit was tested and if it was set an error message (bit 14 set) was sent to the ADC; otherwise the polarity bit was checked. If the polarity was negative, a double precision 2's compliment routine converted the data and in either case both bytes were output to the Alpha-16. The program continued to acquire data at one second intervals until the SDK was reset manually.

The program for the Alpha-16 initiated data acquisition by writing a null byte to the SDK-8.0 interface. It then polled the input buffer until it detected that data had been written into the buffer and read the first byte. The input buffer was polled again until the second byte had been written by the SDK-80. The two bytes were packed into a word and the overflow bit 14, and polarity, bit 15, were checked. If bit 14 was set and b?_t 15 reset, an 'overflow' message was printed on the teletype. Otherwise a 10 second moving average was calculated.

The data display portion of this program was designed to look for a potential change from the electrodes and issue a message when the electrode signals stabilized. After detecting a change in slope of the data versus time, data acquisition 113 continued until incoming data fell within a 1/ range of the most recent mean. Each data point was converted into a 5- digit signed ASCII integer and printed on the teletype until the range criteria were met; a 'stop' message was then printed. 114

3.4 APPLICATION

Five electrodes were prepared according to the procedure outlined in section 3.2.3 and evaluated for:

1. Response to sodium ion 2. Response to potassium, calcium and magnesium ions 3. Selectivity of sodium over potassium 4. Behaviour in whole blood (human)

The experimental procedure was identical for each evaluation as follows:

1. The cell was injected with a wash solution of 10-6M NaCl. 2. The data acquisition program was started and the electrode signals monitored on the teletype printout. 3. When the output was - LSB indicating stabilization, the cell was flushed with approximately 500 pl of the sample solution. 4. When the printout indicated that the electrode had stabilized to within 1/, the SDK-80 was reset and the sample solution flushed from the cell with the wash solution.

3.4.1 RESPONSE TO SODIUM ION

The data logging system was used to collect data for calibration curves constructed for each electrode for standard sol utions of sodium chloride. The slopes of each curve, tabulated

in Table 3.1, were linear from 0.001 M Na+ which includes the physiological range for sodium ion. The deviations f the slopes of the electrodes is attributed to daily variations in solution temperatures. Although thermostatted 115 the solutions would eliminate this source of error, it was found that the effects of temperature variations could be minimized sufficiently for the purposes of this study by re-calibrating the electrodes daily.

The automated data logging system enabled a six point electrode calibration to be carried out in less than ten minutes by using the procedure outlined in section 3.4 and injecting successive standard solutions into the cell in lieu of the wash solution. The plateau response from one standard then became the baseline for the next standard.

ELECTRODE SLOPE (mV/decade) 1 57.2 + 0.1 2 57.3 + 0.1 3 57.5 + 0.1 4 57.5 +.0.1 5 57.3 + 0.1

Table 3.1 Calibration curve slopes for sodium ISE's.

500 — 450 — 400 -, 350 — 300 —

250 — E(mV)

4 3 2 1 p[ Na Figure 3.8 Typical calibration curve for Na ISE; E expressed as

relative value. 116

3.4.2 RESPONSE TO POTASSIUM, CALCIUM AND MAGNESIUM

Calibration curves were constructed for standard solutions of Kt, Ca2+ and Mgt+ over the range of 10-5 to 10-1M. As shown in Figure 3.9, the response of the electrode to Ca2+ and Mgt} is negligible although there was some response to K+. The negligible response to calcium and magnesium was expected based on the predictions of Simon concerning the design of ion selective neutral carrier ligands (147). As complexing agents, the ligands were designed to complex ions of a specific size and charge-to-size ratio. The relevant parameters for the ions studied are listed in Table 3.2.

0 ION r(A)

Na+ 1.0 1.0 + K 1.4 1.4

Ca2+ 1.06 2.0. Mg2+ 0.78 3.1

Table 3.2. Ionic parameters

Presumably, a high charge : ion radius ratio opposes com- plexation with Ca2+ and Mg2+. This seems to be consistent with the behaviour of potassium which is complexed to a greater extent than the divalent ions although it is sterically less favourable.

117

300 - 0 0

250 A - 0 0 200 - 0 0 ❑ Ca2+ 150 - A Mgg+ 100 - +,. E(m1/1 K

5 2 1 p[M]

Figure 3.9 Sodium ISE response to Ca2+, g.2+

300 -

250 _

200 -

150 100 _ E (my)

5 3 p[ N a+]

Figure 3.10 Na+ calibration curve with 1 x 10-2M KCl; E expressed as relative value. 118

3.4.3 SELECTIVITY OF SODIUM OVER POTASSIUM

The method of determining Kij described in Section 3.1 was used here. Measurements on standard solutions of Na+ in a 2 constant background of 10_ M K+ were obtained using the computer assisted electrode monitoring system. All standard NaCl solutions were prepared using a stock solution of 10-2M KCl. A typical calibration curve is shown in Figure 3.10 and the selectivity coefficients for each electrode tabulated in Table 3.3.

ELECTRODE PKN a/K

2.01 + 0.02

2 1.96 + 0.01

3 1.97 + 0.03

4 1.95 + 0.02 1.96 + 0.02

Table 3.3

The response of the electrodes to changes in sodium ion concentration was rapid, typically less than a second, although the timeto reach a stable signal, the 1% value, was approximately 30 seconds. Unidirectional drift from this point was typically 0.2 mV/hr and negligible over the experimental measurement period.

3.4.4 BEHAVIOUR IN WHOLE BLOOD

The object of this evaluation was to observe the response time and drift characteristics of the sodium ISE in whole blood. Consequently the activities of the blood electrolytes were not determined by an alternative method. 119

Samples of whole blood (heparinized) were injected into the cell following a three point calibration over the physiological range for sodium of 135-155 mM. The response time of the electrode was similar to that in aqueous solutions, averaging 30 seconds although the long term drift characteristics were excellent: 0.06 mV/hr.

The reproducibility of the electrode response was examined by successively injecting aliquots of the same sample solution followed by a wash cycle. Over the initial test period of 30 minutes the precision of the electrode response expressed as a standard deviation was 0.02 mV. The precision of the response seems to be limited by long term drift characteristics although during a short measurement period the effect is negligible. Precision could be maintained at 0.02 mV by recalibrating the electrodes periodically. The measured sodium activities for the blood samples analyzed fell consistently within the physiological range for sodium as illustrated by Figure 3.11.

The response and drift characteristics for this electrode offered a significant improvement over those reported for the glass membrane electrode (156) and the three point calibration was infrequently required. Sequential measurements on whole blood samples were separated by a wash cycle using 10-6 NaCl. The effect of the wash cycle in removing debris from the membrane and the cell was essential to obtaining consistent results.

The behaviour of the sodium ISE in whole blood is en- couraging in light of performance of sodium glass-electrodes in physiological environments. Rapid response times and reproducible measurements make the liquid membrane type sodium elec- 120 trode an attractive alternative in the analysis of sodium activity in physiological environments. Considering the progress in the development of neutral carrier ligands for sodium, it seems likely that ligands with lower selectivity coefficients for sodium over potassium than.the ligand used in this study will be synthesized.

2390 _ o sample 2380 _ p standard

2370 _ E (mV) 2360 _

2350 _

2340

135 140 145 150 155 mM Na+

Figure 3.11 Response in whole blood

With highly selective ligands the optimization of membrane consituents becomes less important although still desirable. Of more importance, however, is the proper construction and

maintenance of the reference electrodes. In this study,. high drift rates and spurious signals were eliminated by optimizing the performances of the internal and external reference electrodes. This involved two basic procedures: first, the external reference electrode was connected to the computer system ground at a•point which was common to the ADC. This reduced offset potentials to less than a microvolt. Second, both reference electrodes were equilibrated with their internal 121

reference solutions for a minimum of 12 hours, and not allowed to dry-out. By maintaining the internal filling solutions at a constant concentration, reference drift was held to 0.06 mV/h r . In summary, The hierarchical computer system provides a useful facility for electrode calibration and for selectivity and response time studies. The ability to alter the data acquisition rate and slope parameters enabled subjective errors to be minimized by constraining the precision between

known limits. In this initial study, the liquid membrane sodium selective electrode based on Simon's ligand demonstrated selectivity over potassium and response times which are an improvement over the performance of existing sodium ISE's. Further work needs to be done to determine the long term behaviour of the ligand and the optimum parameters for membrane construction. 122

CHAPTER 4. BACKGROUND SUBTRACTION IN VOLTAMMETRIC ANALYSIS

4.1 STATIONARY ELECTRODE POLAROGRAPHY

Stationary electrode polarography (SEP), or linear sweep chrono-amperometry, is an electroanalytical technique which can be applied using a three electrode polarographic cell under potentiostatic control. In operation, a potential applied to the polarographic cell is varied linearly with time and the

current resulting from the oxidation or reduction of electro-

active compounds at.the working electrode is monitored (109).. Unlike conventional DC polarography which uses a dropping mercury electrode, DME, as the working electrode, SEP employs a static working electrode, either a hanging mercury drop electrode, HMDE, or a solid electrode. The voltage/time and current/time profiles for a typical SEP analysis are shown in Figure 4.1. For the purposes for discussion the voltage scan in Figure 4.1 (a) will be considered in the cathodic direction ERhough an anodic scan may be treated similarly. The resulting current/time profile in Figure 4.1 (b) is attributed to the faradaic current accompanying the reduction of an electroactive species at the working electrode as follows;

Ox t ne- Red (4.1)

where n represents the number of electrons transferred during. the reduction step. —The standard electrochemical half-cell potential Eo, appears in the region where the current is controlled by the applied potential and the peak potential, Ep, marks the point where the current is limited by mass transfer. The current in the region of the curve cathodic to,Ep represents the depletion of the oxidized species near the working electrode. Here the

current is a function of 1/t , typical of diffusion controlled 123 processes. The relative peak height is proportional to the bulk concentration of the Ox species in solution and can be used for the determination of concentrations between 10-3 and 10-6 molar with an accuracy of 2%. In addition to faradaic current, there is a contribution of charging current resulting from the double layer capacitance effects near the surface of the working electrode. The charging current is continuous and directly proportional to the sweep rate. The charging current/time profile for a typical'supporting electrolyte solution containing no electroactive compounds is shown in Figure 4.2. Assuming a cathodic voltage sweep, the charging current changes significantly as the potential becomes more cathodic. Since the faradaic and charging current are additive, an SEP waveform may become dis- torted as shown in Figure 4.3. If the faradaic process occurs near the cathodic end of the sweep, the faradaic current may be masked completely. This poses a limitation to SEP for qualitative and quantative analyses.

f(1/iff )

a) (b) E(t)

Figure 4.1 (a) SEP voltage/time relationship (b) current/time profile 124

Ich

E (t)

Figure 4.2 SEP Current/time profile for charging current

E(t) Figure 4.3 SEP waveform with faradaic and charging current

The sweep rates for SEP are fast relative to DC polarography, in the order of 50mV/sec. Fast sweep rates shorten analysis times making SEP an attractive technique for the routine analysis of large numbers of samples. Whereas the magnitude of the charging current is proportional to the scan rate the faradaic current is proportional to the square root of. the scan rate. Thus for a scan rate V, the ratio of the peak current to the charging current is

ip V 2 (4.2) ich V

V .z

For example, if the scan rate is set at 50mV/sec then 125 the peak current for a solution containing an electroactive species at a concentration level of 10-6M in a cell with a working electrode double layer capacitance of 2 microfarads is between 0.01 and 0.02 microamp while the charging. current contribution is between 0:05 and 0.1 microamp. The peak current to charging current ratio is approximately 0.2. By increasing the scan rate to 1V/sec, the ratio is reduced by a factor of 5 to 0.04. Therefore, the speed at which an SEP analysis can be performed depends upon the acceptable level of resolution, the concentration of the electroactive species, the double layer capacitance of the working electrode and the ability of the SEP instrumentation to discriminate faradaic current from charging current.

4.1.1 BACKGROUND SUBTRACTION

A method for reducing the effects of high charging currents in SEP analyses involves simply subtracting the charging current contribution from the stationary electrode polarogram. Back- ground subtraction is carried out in three steps. First, an SEP scan of the supporting electrolyte solution is recorded. The current recorded in the background scan is the charging current contribution since the electroactive species is absent.

Second, the electroactive species is added to the supporting electrolyte solution and another SEP scan recorded. The current in the analysis scan is the sum of the charging current and the faradaic current.

Third, the background scan is subtracted from the analysis scan resulting in a curve representing the faradaic current contribution. This presupposes, of course, that the charging current contribution is constant between the two scans. 126

The applicability of background subtraction to SEP analysis using a glassy carbon working electrode is discussed below in more detail. 127

4.2 THE WALL-JET. CELL

The wall-jet cell is a polarographic cell designed for use with a solid working electrode in a flowing stream. The original design by Fleet and Little (115). has been used and modified by several, workers, notably Das Gupta (116), Berger (110) and Gunasingham (111). Figure 4.4 shows a schematic diagram of the wall-jet cell. In operation, a flowing stream passes through the inlet port (IN) and impinges upon the surface of the working electrode (W) placed perpendicularly to it. A reference electrode (R), either Ag/AgC1 or a SCE, is located opposite a metal tube counter electrode (C) which also serves as the solution exit port.

glassy carbon

inlet jet W

outlet

Figure 4.4. Schematic diagram of the wall-jet cell

Using a conventional three-electrode potentiostat the cell can be applied to hydrostatic and hydrodynamic voltammetric studies. In the hydrodynamic mode, the solution flow through the cell is continuous whereas in the hydrostatic mode the flow is halted during the analysis.

Gunasingham (111) has demonstrated the utility of the wall-jet cell as a detector for high pressure'liquid chromatography. In these studies, the working electrode was a disc of 128 glassy carbon. The extended anodic range of glassy carbon, to +1.5V versus SCE, makes it a useful material for the study of the oxidation of organic compounds, for example phenols in acid medial steroids and polynuclear aromatic hydrocarbons.

As a detector for HPLC the wall-jet cell is used in the hydrodynamic mode. A fixed potential is applied to the cell to exceed the standard cell potential for the compounds to be analysed so that any current detected is diffusion limited. As electroactive compounds are eluted from the HPLC column onto the surface of the working electrode their concentration/time profiles are monitored as current/time profiles by the detector. By plotting current as a function of time a conventional liquid chromatogram is obtained.

In addition to fixed potential operation, the wall-jet cell can be used to obtain detailed electrochemical information on electroactive species present in the HPLC eluent by stop-go operations. In this mode of operation the carrier solvent flow is halted and a SEP analysis performed. The procedure is outlined by the flowchart in Figure 4.5 and a typical SEP curve for the analysis of ortho-amino phenol is illustrated by.

Figure 4.6. 129

Figure 4.5 Flowchart for stop-go analysis.

0.5 E vs SCE

Figure 4.6 Typical SEP curve for 2x10-5 M orthoamino phenol in 70/30 hexane/methanol. 130

4.3 EXPERIMENTAL

. Three separate computer systems were used to evaluate the applicability of background subtraction to voltammetric analysis. Although the computer systems varied in design and organization, the overall function of each system was similar. In general, the experimental arrangement consisted of a three electrode polarographic cell, a polarographic analyzer and a computer. The function of the polarographic analyzer was first to provide an SEP. waveform to the polarographic cell and second, present the computer a voltage related to the current between the counter and working electrodes. The function of the compute_- was to acquire voltage data from the polarographic analyzer, perform the background subtraction and display the results. Each system is discussed below with respect to the hardware employed, the software required and applications.

4.3.1 MINICOMPUTER SYSTEM

4.3.1.1 Hardware

A block diagram of the minicomputer based system is shown in Figure 4.7. The minicomputer (Alpha-16, Computer Automation) is directly interfaced to a teletype (ASR 33, teletype corporation) and the general purpose interface (GPI, Appendix 1), and indirectly interfaced to a storage oscilloscope (Hewlett- Packard 141B , Hewlett Packard Corporation) and a 14-bit dual- slope ADC (ADC 1105K, Analog Devices). The ADC is connected to the recorder output of the polarographic analyzer (PAR-174, Princeton Applied Research).

In Figure 4.8 the connections between the GPI and ADC are detailed. The 1-Hz output from the decade clock is

131 connected to the convert socket of the ADC. A conversion is initiated by a 1-to-0 transition of the clock. The end-of- conversion signal from the ADC is connected to the FLAG input of the GPI such that a 0 to 1 transition sets the FLAG bit.

The ADC mode switch is set to manual and the range is set to • 10 volts. On the 10 volt scale the ADC can resolve 0.6mV.

PAR-174 0 ADC

alpha-16 cell GPI

- tty logic scope \ / panel

Figure 4.7 Minicomputer system block diagram

1 Hz cony

GPI flag c eoc 1105 K

16-bit input analogue in e--

-15 V -15V +15 V +15V gnd +5V +5 V gnd

Figure 4.8 GPI-ADC detail 132.

The interface to the storage oscilloscope is shown in Figure 4.9. Eight bits from the Alpha-16 are sent through the GPI to an 8-bit DAC (ZN425E, Radio Spares) mounted on the Logic Panel (Appendix 1). The analogue output from the DAC is connected to channel A,of the oscilloscope which is triggered internally.

4.3.1.2 Software

The software was written exclusively in Computer Automation Assembly language and consisted of three basic modules: a data

acquisition routine, a data handling routine and a display routine. The data acquisition routine was designed to acquire 16-bits of information from the ADC when operating under external control, extract the 14-bit magnitude, and determine the polarity and overflow status. A flowchart which describes the operation of this routine is shown in Figure 4.10. The 16-bit data word from the ADC, composed of a 14-bit digitized analogue magnitude, one polarity bit and one overflow bit is shown in Figure 4.11. The operation of the data acquisition routine is as follows: first, the routine inputs the status of the FLAG bit from the GPI. If the FLAG bit is zero, the routine inputs

the status again. If the FLAG bit is equal to 1, it indicates an EOC signal from the ADC and the data word is then input for, decoding. The format of the data word is such that bit 15, when set, indicates an overflow and bit 14 when set indicates negative polarity. To the computer, bit 15 is, by- convention, 'the sign bit; thus an ADC overflow is seen by the computer as a negative number. The routine, therefore, tests the ADC data word for polarity, if the data word is negative,.the X register of the Alpha-16 is set to one. If the data word is positive the X register is set to zero. The data word is then shifted to the left by one bit and the data word polarity bit is tested . 133 similarly. If the data word is negative, the magnitude is negated, if it is positive, the magnitude is unaltered. After the data word has been decoded, the FLAG bit is cleared.

GPI~ ZN425E DAC 8-bit> scope 141B output A +5V

gnd gnd

Figure 4.9 Storage oscilloscope interface detail

The data handling routine performs the background subtraction operation and scales the information for display purposes. The flowchart for the data handling routine is shown in Figure 4.12. The data handling routine maintains three data buffers in memory, one for each type of operation performed during the analysis, background, scan and difference. Operator keyed commands are interpreted by the data handler to store a background . scan, store an analysis scan, perform a background subtraction or enter the display routine. Buffer pointers and buffer-full status flags are used by the data handler to access correctly the required information. The scaling of data for display on the oscilloscope requires the largest datum to be reduced in magnitude to eight bits. This is accomplished by taking the largest value and shifting it to the right until its magnitude is less than or equal to 255. All remaining values are equally shifted to the right. 134

ov pot 13 12 11 10 9 8 hi byte

7 6 5 4 3 2 1 0 to byte

Figure 4.11 16-bit ADC data word

The data display routine allowed the operator to display the contents of any buffer graphically on the oscilloscope with eight bits of resolution or numerically on the teletype with 14 bits of resolution. The oscilloscope display was accomplished by cycling through the scaled data buffer and sending the data through the GPI to the DAC located on the

Logic Panel. The 8-bit byte was converted into a voltage which was presented to channel A of the oscilloscope. By adjusting the horizontal sweep rate and vertical magnitude on the oscilloscope, a relatively sharp stationary waveform was displayed which reflected the appearance of the original analogue waveform.

The teletype display consisted of a five digit. signed integer for each data word converted into decimal from binary by a subroutine, ODEC, one of several supplied by Computer Automation in the Teletype Utility Package, TUP. 135

4.3.1.3 Application to SEP

The procedure for applying background subtraction to SEP. was as follows:

1. A backgroiril solution, the supporting electrolyte, consisting of either 0.1M or 0. O1M KNO3 for aqueous analyses or 0.05M tetrabutyl ammoniumfluoroborate in an appropriate organic solvent for non-aqueous analysis was prepared and transferred to the polarographic

cell.

2. A working electrode, removed from a wall-jet cell and consisting of a disc of glassy carbon 4mm in diameter a platinum counter eletrode and a Ag/AgC1 reference electrode were placed in the polarographic cell.

3. The solution was deoxygenated by bubbling oxygen-free nitrogen through the solution for 15 minutes and a layer of nitrogen maintained over the solution during the analysis.

The initial potential, polarity, scan rate, scan

direction, scan range, sensitivity and output polarity were set on the PAR-174 according to the nature of the analysis, the PAR-174 was placed in the initialized mode and connected to the external cell.

5. The decade clock was disabled and the FLAG bit reset.

6. The data acquisition program was initiated and a "background" command issued. 136

7. The decade clock and PAR-174 scan were simultaneously enabled.

8. A data conversion was made once each second for 100 seconds at which time the program printed an "end of acquisition" message; the decade clock and the PAR-174 were disabled. At this point the information in the background buffer could be examined by teletype or by oscilloscope.

9. The analyte was then added to the polarographic cell, the solution deoxygenated and the hardware initialized as in 4 and 5.

10. A "scan" command was issued to the data acquisition program and 100 data points collected at one second intervals as in 8.

11.. The background was then subtracted from the scan and the resulting waveform displayed on the oscilloscope and teletype. The original background and scan were also available for display. 137

(start

read flag bit

clear X reg

:read data word

es set X reg L to 1

shift left 1 bit

shift right negate 1 bit

shift right 1 bit

clear flag

(eturn).

Figure 4.10 Flowchart for data acquisition routine 138

(start

initialize no buffer obtain location pntr data

no initialize obtain buffer data

subtract background

call display routine

end )

Figure 4.12 Flowchart for data handling routine. 139

(start)

initialize buffer

read command

read flag

read data word no process word

yes

( stop)

Figure 4.13 Data acquisition flowchart

Although the SEP waveforms could be viewed.on the oscillo-. scope immediately after the scan, the teletype output provided information with a higher resolution and in a form which could be scaled, plotted on graph paper and kept as a permanent record. The dynamic range of the 14-bit ADC made it possible to extract details that were lost by conventional recording 140 devices such as the chart recorder with a resolution of only one part in 800. Figure 4.14 illustrated a typical background scan of a 0.1M KNO3 solution. The absolute magnitude of the current is not relevant to the discussion, however, the range is indicated as approximately 100mA.

Figure 4.15 shows an uncorrected SEP scan of 2 x 10-5MCd2+ in the same electrolyte solution used to obtain the background scan in Figure 4.14. The scales of both figures are the same and appear as they would on a chart recorder.

Figure 4.16 shows the scan of Figure 4.15 after the background has been subtracted. The scale has also been greatly expanded as indicated. The increased dynamic range of the data acquisition system enabled information over the entire scan range to be analyzed which was not convenient with a conventional recording system. The analytical sensitivity of SEP was not improved, however.

Figure 4.17 illustrates the application of background subtraction to the analysis of mixtures and Figure 4.18 shows an example of a non-aqueous analysis.

By increasing both the conversion rate and the scan rate by a factor of five, analyses were made with no loss in resolution over the scan range. The 10Hz clock output was divided into two using a J-K flip-flop as illustrated in Figure 4.19.

The increase in background current as produced by SEP theory was observed as shown in Figure 4.20. 141

100 ma

-1.0 E (V)

Figure 4.14 Background scan of O.1M KNO3

-1.0 E (volts)

Figure 4.15 SEP scan of 2 x 10-5MCd2+ 142

10 ma

E (volts)

Figure 4.16 Background subtracted SEP scan of 2 x 10-5MCd2

-0.3 - 0.6 - 0.8 E (volts)

Figure 4.17 Background subtracted SEP scan of a mixture:

2 x 10-5M Cd2+, 2 x 10-5MT1+ and 2 x 10-5MPb2~ 143

10ma

+.5V +.6V

Figure 4.18 Background subtracted scan of orthoamino phenol in 70/30 Hexane/Ethanol

+5 V

10 Hz

Figure 4.19 5Hz clock

0 +0.6 V

Figure 4.20 Rapid scan example 145

4.3.2 MICRCOMPUTER SYSTEM

4.3.2.1 Hardware

The microcomputer system was bsed on the Intel system design kit SDK-80. The kit consisted of an 8080-A microprocessor, lk RAM, one 8251 USART chip, a system resident monitor and two 8255 peripheral interface chips. One 8255 was configured to interface to the Alpha-16 minicomputer and an 8-bit ADC while the other 8255 was configured to control a PAR-174 through a purpose built control/timer unit (110).

The interface to the control/timer unit is detailed in Figure 4.21. The control/timer unit was designed by Berger (110) to control the Initialize, Scan and Hold pushbuttons on a PAR-174 by using electronic relays activated by digital logic circuitry. In order to override the control/timer unit functions an external digital signal was OR'ed to the logic signal controlling its respective relay. Thus, either the control/timer unit circuitry or an external signal could control the PAR-174. The added logic enabled any sequence of push- button operation to be applied to the PAR-174 wheareas the original control/timer unit was restricted by design to a single sequence of operations.

The external control signals were provided by the SDK-80 interfaced to the control/timer unit as shown in Figure 4.22. Although functionally similar to the system depicted by Figure 4.7, this system uses an 8-bit ADC with a maximum conversion time of 1 ms and controls the operation of the polarographic analyzr_=r directly. The advantage of this system is its precise synchronization of data acquisition and scan initiation and a 200 fold increase in data acquisition rate. The disadvantage of 146

Figure 4.21 Control/timer unit modification for external control.

the system is the limited resolution of 8-bits.

The interfacing of the SDK-80 to the 8-bit ADC and the control/timer unit is straightforward. The 8255 peripheral interface chip can be tailored by software commands to act as an input port, an output port , a combination input/output port, and a bi-directional I/O port. Two 147

HPLC WJ CELL

R W C scan s controller hold PAR-174 gnd gnd

eoc SDK-80 ov 8- bit conv ADC analogue in digital input recorder

VDT

Figure 4.22 Block diagram of the microcomputer system. 148

8255's were used in this design, one to interface the control/ timer unit, and the other to interface the Alpha-16 and 8-bit ADC. The interface to the Alpha-16 will be discussed in the next section.

The interface to the 8-bit ADC consisted of eight data lines, one EOC line, one convert command line, one overflow line and one line to control the track/hold amplifier at the ADC analogue input. The interface to the Alpha-16 required all but eight input lines and three output lines, thus the

EOC and overflow bits were multiplexed with data bits 6 and 7, respectively; the multiplexer controlled by one. output line. This arrangement is illustrated in Figure 4.23.

CO conv Cl t/h I C2 mpx M • eoc P • ov B7 eoc/bit 7 • X bit-7 ov/ bit 6 • R 4 8255 ADC t• E BO bi't 0 c bi t O

Figure 4.23 8-bit ADC to 8255 interface.

The interface to the control/timer unit required three lines which were selected from Port C and configured as output lines. Each of the three bits of Port C, PC-O, PC-1 and PC-2, were associated with a relay which in turn activated either the PAR-174's Initialize, Scan, or Hold, respectively.By outputtinc 149 a digital code to Port C, any of the relays could be activated at random. Table 4.1 lists the binary codes sent to Port C and their significance.

BINARY.CODE (HEX) ACTION.

06 INITIALIZE

05 SCAN

03 HOLD

Table 4.1 Binary codes sent to Port C to control PAR-174 functions.

As illustrated in Figure 4.22, the electrochemical end of the system consists of an HPLC employing a wall jet cell as .a detector. The HPLC system has been described previously by Gunasingham (111). In this work all separations were'carried out on a silica. column (Dupont, 10 micron particle size) with a solvent consisting of 70/30 hexane/4nethanol. The supporting electrolyte used was tetrabutyl ammonium fluoroborate.

4.3.2.2 Software

The software consisted of three sections, data acquisition, data handling and PAR-174 control, written in Intel machine language. All routines were assembled without the aid of an assembler by the following method:

1. The source code was written using assembly language

mnemonics

2. The absolute addresses for instructions and data were assigned taking into account multibyte instruc-

tions. 150

3. The machine codes for instructions, and data were filled into the. addresses.

4. The resulting object code was keyed into the microcomputer RAM memory.

The data acquisition section consisted of two routines, one for controlling the 8-bit ADC and one for detecting HPLC peaks. The ADC controlling routine is outlined by the flowchart in Figure 4.24. Similar to the data acquisition routine in Figure 4.13,, the routine waited for the EOC to be set, switched the multiplexer to the data word mode and read the data. Although the ADC possessed an overflow indicator bit, it was configured to accept only positive values and therefore did not have a polarity bit.

The peak detecting algorithm is shown schematically in Figure 4.25. Essentially, the routine read a byte from the 8-bit ADC, pushed it onto a three byte stack and compared it to the previous byte acquired. If, for example, three bytes were acquired such that each byte was greater than the previous byte, then a flag was complemented. Thus to look for the beginning of a peak, the stack and flag were cleared and the routine called; when the flag was set a positive slope change had been detected.

The data handling routine was responsible for converting binary data into decimal numbers for display on the video display terminal, maintaining a moving average, data acquisition timing and peak detection. Binary to decimal conversion was accomplished by modulo arithmetic using magnitudes of ten from 10,000 to 10. Remainders from each operation were used in the next lower stage. The number of loops required for each

operation were coded into ASCII for display. 151

(start

set error flag

delay

write ADC convert

read eoc

set error flag

set to read data

read data

(re turn)

Figure 4.24 Data acquisition flowchart from 8-bit ADC 152

clear counter

read byte

push on stack

compare to previous byte

up flag set smaller

larger

increment counter

compare o threshold

exceed 4

complement up flag

Figure 4.25 Flowchart for peak detection routine 153

A moving average was maintained selectable between four, eight and 16 points depending upon the amount of noise present, the rate of data acquisition and the severity of changes.

Data acquisition was either externally controlled by a 100Hz clock or internally controlled by a timing routine. External control was used primarily in background subtraction algorithms where a strict timing relationship between background and scan data is important.

Peak detection was accomplished by first looking for a set of increasing data values then a set of decreasing data values. The resolution of peak inflection point detection was limited by the number of data points required for the moving average and the data acquisition rate. Peak detection was optimized by. adjusting the moving average as the slope approached zero. The algorithm for this procedure is shown in Figure 4.26.

The control of the PAR-174 was based on information received from the data handling section. At the beginning of the experiment the code 03 was sent to Port C to place the PAR- 174 in the hold mode. Data was acquired from the PAR-174 until a peak was detected at which point the code 06 was sent to initialize the PAR-174. A scan was then initiated by sending the code 05 to Port C. The procedure is illustrated by the flowchart in Figure 4.27. 154

freeze moving average

Figure 4.26 Flowchart for optimizing peak detection 155

t) (star

send hold to PAR

wait

look for peak

initialize PAR

wait

o a scan

(stop )

Figure 4.27 Flowchart for PAR-174 control. 156

4.3.2.3 Application to HPLC

The microcomputer controlled PAR-174 system was evaluated as a computer aided HPLC detector system in two stages. The first stage involved straightforward peak detection. The average of four data values acquired at a rate of 100Hz was calculated every second. A typical LC peak required between one and two minutes to elute, giving a peak detection window of approximately five seconds. Within this window, the slope change was significantly large to be a good indication of the approaching inflection point. The data acquisition rate increased to one point per each 0.01 second interval and 16 successive points averaged. The increased density of data values enabled a peak to be detected to within 1% of its true value. Due to the small memory size of the computer system, however, only the retention time and a few data points could be saved; the data points were transmitted to the VDT display as they became available until the data acquisition rate exceeeded. the transmission rate. A maximum of 56 values could be retained for queued transmission to the VDT. A sample separation illustrating the peak detection method is shown in Figure 4.28.

• 0 1 2 3 min Figure 4.28 Typical liquid chromatogram illustrating the peak detecting operation. ( A = o-aminophenol, B = p-aminophenol; 60/40 hexane/methanol ) 158

The second stage of the evaluation involved a stop-go procedure for obtaining SEP data on eluting compounds. As a peak was detected, the operator was signalled to stop the HPLC solvent flow. A SEP sweep was then made at a high rate, the background subtracted and the solvent flow re-started. Although this procedure is not recommended for quantitative analysis or for separations involving large numbers of compounds, it provided a rapid method for detecting overlapped peaks. Although two compounds, assuming both to be electroactive, may have similar or identical retention times, they seldom exhibit a similar response to a SEP sweep.

A stationary electrode polarogram for phenol and 3-isopropyl phenol is shown in Figure 4.29. The solvent is 70/30 hexane/ methanol with t'trabutyl ammonium fluoroborate. The electrodes employed were as described previously.

A liquid chromatogram for a 50/50 mixture of phenol/ 3-isopropyl phenol separated.in the same solvent as above is also shown in Figure 4.29.

.pne iso •

0 2 min +0.4 +0.6 V

Figure 4.29 (a) Liquid chromatogram (b) SEP curve for phenol/3-isopropyl phenol mixture

159

Background subtraction was accomplished by saving a 56 point SEP curve of the solvent and subtracting point-by-point the background from the scan in real time. Although no additional memory was required, the background and original scan data were destroyed. The background subtracted scan data were displayed on the VDT and plotted on graph paper. Figure 4.31 shows the background subtracted scan for the phenol/3-isopropyl phenol mixture.

1 1~ • t iso 1 phe

0.4 0.6 V

Figure 4.31 Background subtracted scan for 50/50 mixture of phenol/3-isopropyl phenol 160

4.3.3. HīERARCHICAL SYSTEM

The limitations of the microcomputer system of the previous section stemmed from the small memory size of the system. In. order to improve the overall performance of the system the processing requirements were distributed between two computers, the Alpha-16 and the SDK-80. The Alpha-16 was designated the master, responsible for the control of the experiment and data handling.

The. SDK-80 was designated the slave computer accepting instructions from the master and executing the actual control and data acquisition tasks.

4.3.3.1 Hardware

The elements of the two systems described previously were configured into a hierarchical system as shown in Figure 4.32. The Alpha-16 was interfaced to the SDK-80, GPI and TTY directly and to the oscilloscope and PAR-174 indirectly. The SDK-80 was capable of transferring data at a rate of 64,000 bytes per second. Thus a typical program 256 bytes in length could be transmitted in 4 ms.

4.3.3.2 Software

The algorithm for the operation of the slave computer is illustrated by Figure 4.33. The operating system of the slave computer consisted of a loop in which the computer sampled continuously the data link to the Alpha-16. A program command issued by the master caused the slave to enter the program receive routine. This routine would read from the master two bytes containing the length of the application program in bytes and then the application program. The application program, 161 written as a subroutine would then be called and executed. At the end of execution, the application program would return control to the program receive routine and the slave would continue to wait for a command from the master.

8080 interface vdt °(-16 SDK-80

GPI a

logic control / w crt panel PAR-174 IC

Figure 4.32 Alpha-16 / SDK-80 hierarchical system.

initialize stack pointer etc.

yes

return from

Figure 4.33 Slave computer operating algorithm. 162

The software for the master was divided into three categories, experiment control, SDK-80 send and receive, and display. The experiment control routines were adapted from the routines used in the previous sections.. A peak detection routine acquired data from the experiment via the SDK-80 and performed the optimized peak detection algorithm employed earlier. In this instance, however, data points were simultaneously displayed on the oscilloscope by the display software.

A background subtraction routine acquired experimental data on background and scan trials and performed the actual subtraction. Three data buffers, one each for background, scan and background subtracted data were maintained and could be displayed individually.

The SDK-80 send and receive routines were designed to send program information to the SDK-80 and receive experimental data from the SDK-80. The machine code for application programs written in 8080 assembler was stored as data in the Alpna-1f memory al^d therefore only direct transmission to the SDK-80 was necessary.

4.3.3.3 Application to HPLC

The application of the hierarchical computer system to HPLC followed a generalized procedure as outlined below:

1. The computer system was initialized by resetting all interrupt, buffer and ADC flags. The external clock was reset and the PAR-174 configured to the desired initial

conditions. 163

2. Solvent was eluted from the HPLC column and monitored on a chart recorder until the output from the wall-jet cell detector stabilized. The flow was then discontinued.

3. The master program was run and the background option selected. The master downloaded the background application program to the SDK-80 which then proceeded to initiate a scan, enable the 100 Hz external clack, acquire data and transmit averaged values to the master. Upon completion of the background application program, a "done" message was printed on the TTY and a command prompt issued.

4. A sample was then loaded onto the column, the HPLC flow started and the peak detect option selected. The master downloaded the peak detection' program to the SDK-80 and displayed the returning data on the oscilloscope as it was received. Upon detection of a peak the master printed a "peak" message on the. TTY and the HPLC flow halted.

5. The scan option was then selected, the scan application program downloaded to the SDK-80. The scan data was saved in the scan buffer, processed by the background subtraction routine and the corrected scan displayed on the oscilloscope. Upon completion of the scan a "done" message was printed on the TTY. The master issued a command prompt and waited for a command.

6. The remaining command options enabled the display of each of the three data buffers and initialization which cleared the buffers and reset all of the system flags. 164 The hierarchical approach improved the resolution of the HPLC detection system by a factor of two since a greater number of data points could be collected and processed, although the peak detecting ability was unaffected. Similar results could have been obtained by increasing the memory size of the microcomputer system and allowing it to control the experiment completely and process the data. There would be a concbmmitant loss in flexibility, however. Ideally, in an hierarchical system, the influence of the master computer should be minimized and the slave computer should be transparent; the functions of the master computer should be limited to read/write operations to the slave computer with the slave performing the control and data acquisition. As peripheral chips can be configured to handle simple I/O tasks, the slave computer can be considered as an expanded peripheral device which can execute more complicated functions. The master computer can then operate in a simple read/write mode with the slave without involvement in the actual experiment. In the system described in this section, the master issued instructions to the slave but did not otherwise involve itself in the operation- of the experiment. The instructions, in the form of program segments, could have instructed the slave to execute a variety of procedures, although the information read from the slave was viewed independently of the method of acquisition. Changes in experimental procedure could, therefore, be made via the slave computer without altering the programming in the master. 165

CHAPTER 5 MICROCOMPUTER CONTROL AND OPTIMIZATION OF STAIRCASE VOLTAMMETRY

In 1960 G. C. Barker reported that the performance of polarographic analysis could be improved by the application of potential-step techniques (117). The subsequent development of several potential-step based methods, in particular pulse polarography and differential pulse polarography, has broadened the utility and increased the sensitivity of polarography as an electroanalytical tool, confirming Barker's predictions.

Experimentally, the most direct potential-step technique is staircase voltammetry, or SCV. The first results of SCV experiments were published by Mann in 1961 (118). In this work the similarity between SCV and stationary electrode polarography as discussed in Chapter 4, was noted. Further experimental studies of SCV were completed by Mann in 1965 (119). In both of his studies, Mann applied a voltage waveform in the shape of a staircase to the polarographic cell. Unlike SEP in which a linear voltage ramp was applied and the cell current monitored continuously, the current from Mann's experiments was sampled only at the end of each step. Thus the resulting staircase voltammogram consisted of a sequence of current values the number of which was equal to the number of steps comprising the staircase waveform.

The first theoretical treatment of SCV appeared also in 1965 by Christie and Lingane(120),. and considered the sampling of current at the end of each step for reversible reactions. The result of their work will be discussed subsequently.

The theory of SCV remained virtually unchanged until 1973 when Ferrier and Schroeder (121) extended Christie's work to 166 include the sampling of current at points along the step (not just at the end), for diffusion controlled, rate controlled and mixed diffusion/rate controlled reactions; as well as for reversible, irreversible and quasi-reversible reactions. Experimental support for the extended theory was also provided by Ferrier, Chidester and Schroeder in the same publication (122).

Additionally, a theoretical and experimental evaluation of SCV using computer controlled instrumentation was published in the same year by Zipper and Perone (123). Here, the advantages of digital instrumentation to SCV experimentation were stressed.

An extension of SCV to cyclic voltammetry was provided by Miaw et al.(126), who considered the use of SCV as a means for studying basic electrode processes, and demonstrated the complexity of cyclic staircase voltammetry and the electrochemical effects caused by the shape of the applied waveform.

In the next section of this chapter a review of the theory behind SCV is presented and the parameters affecting the shape of the staircase voltammogram are discussed. The following sections describe a novel microcomputer based SCV instrument and the software used to control it. A method for optimizing the scan time is also presented. 167 5.1 STAIRCASE VOLTAMMETRY

The waveform applied in SCV is a staircase as shown by Figure 5.1. The height of each step is E and the length of a step is denoted by t; the scan rate in volts persecond is determined by these two parameters. The current flowing between the working and counter electrodes is sampled at a time, t', after each step. A sampling parameter, °(, has been used (123) to describe the relationship between the step length and sampling time such that:

0 - 1 - tr (5.1) t

For the case of current sampled near the beginning of the step, « approaches one, whereas if the current is sampled near the end of the step, olr approaches zero (123) .

The theoretical equations of Christie and Lingane (120) provide a description of the current, i, for the jth step, here for a reduction process:

i = nFACo*Do 2 I/ (j, A E, t) (5.2) where n is the number of electrons transferred, F is the Faraday, A is the electrode area, Co* is the bulk concentration of the reducible species, Do is the diffusion coefficient for 0 and 's is the function of the step parameters. A general evaluation of 1s by Christie and Lingane yields a series of factors each containing an exponential term

Ej = exp -RT(Ei + jAE - E2) ; j = 1.2.3... (5.2a) where Ei is the initial potential at which the sweep began and the other terms have their usual meaning. 168

Christie and Lingane's general solution dealt only with current sampling at the end of a step in which the time from the kgining of the sweep, t, was measured as

(5.2b)

Perone and Zipper (123) while retaining the exponential relationship of. equation 5.2a modified the time dependence to apply to current sampling at any point along the step, including the beginning and end. This relationship appears as simply

ts = ( j -0()t (5.2c). The effect of this substitution on describing the behaviour of the current during an SCV scan is shown by equation 5.2d.

S or , E) i [(j -vr)ti = nFACo *Do 27 (J , (5.2d)

In this relationship, the sampled current at time t' on the jth step is a function of both the step length and the sampling time.

Equations 5.2 and 5.2d, although similar in nature, predict subtle differences in the shape of SCV Traveforms which will be discussed in greater detail below.

In addition to the faradaic current generated by the oxidation or reduction of an electroactive species there is a contribution from the charging current. When a potential step is applied to the polarographic cell, the diffusion layer, or double layer, extending from the surface of the electrode charges. If the potential is held at a fixed value, the double layer capacitance can discharge as a current through the cell resistance. Ferrier, Chidester and Schroeder (122) related the charging current, i,‘to the cell parameters as 169 follows:

_ (A E/Ru)exp((-t/RuCd)(t'/t)) (5.3) where Ru is the uncompensated cell resistance and Cd is the double-layer capacitance. The combined parameter RuCd represents the cell time constant.

time

Figure 5.1 SCV waveform

Figure 5.2 compares the current response to a potential step between the faradaic and charging currents. The total current measured at any point along the step is the sum of the faradaic and charging current contributions. For analytical puposes, the charging current is an undesirable quantity which distorts the faradaic current. The rate of decay for charging current, however, is greater than that for the faradaic current; the ratio of faradaic to charging current increases with time. Therefore, by sampling the current at a point along the step where the charging current has decayed to a negligible value, the faradaic components can be extracted virtually free from the primary background interference of charging current.

Initially it would seem appropriate to sample at a point many multiples of the time constant of the charging current 170 decay, thus avoiding its effects completely. In practice, however, this is not possible as constant systemic noise, ie instrumental noise, has a finite value that becomes significant with respect to the faradaic signal as sampling times increase; the faradaic signal decays whereas the systemic noise remains constant resulting in an overall loss in signal-to-noise with time. The optimum sampling time, therefore, is a point at which both the effects of charging current and systematic noise are minimized.

k. f

—ich time Figure 5.2 Charging current, ic, and faradaic current, if, in response to a potential step

As mentioned above, the shape of the SCV waveform, the staircase voltammogram, is a function of the sampling parameter 0(. ; this effect has been documented (123, 126) and is illustrated in Figure 5.3. As o approaches one for a specific value of E the.SCV peak becomes sharper and the peak potential becomes anodic as predicted by theory. The tendency for the peak height to "level off" at small values of is due to the lessening of the rate of decay of the faradaic current.

Experimentally, occan be varied in two ways: the step duration, t, can be held constant and the sampling time t' varied, or t' can be held constant and t varied. The shape of the SCV polarogram is constant for a particular value of regardless of the technique used, although the magnitude of

171

the current decreases as a function of the step duration.

r.A r

r / ~. , I ; .~ \ , • I ∎ 4- I I / •∎ ■ C ■ CJ r / ∎ a:4 1

Il, • ~. \ L) • I/ //1 /./r

//// //•7 /ji • ■

Figure 5.3 The effect of the sampling parameter o

The duration of an SCV sweep is controlled by the number of steps used multiplied by the step duration. A 256 step sweep lasting one second, for example, requires a step duration of approximately four milliseconds. The choice of step duration must be made considering the effect of the charging current on the faradaic current. To minimize the sweep time the current is sampled at the optimized sampling point described earlier. Traditionally, this point has been four cell time constants after the potential step (123). The value of four 172 cell time constants allows the charging current to decay to approximately 2% of its initial value.

Examination of equation 5.3 reveals that the cell time constant can be determined empirically by measuring the current as a function of time. If the current is measured at the end of the step such that the ratio of t' to t is unity, then a plot of the logarithm of the current versus time should yield a straight line with a slope equal to the negative reciprocal of the cell time constant. This calculation could be carried out on a single step prior to an SCV scan using fast data capture techniques. In most instances, however, the cell time constant is too . short (ca. 0. lms) for this method to be successful.

An alternative approach would be to monitor the background current during a single step or several steps and locate by direct measurement the region in which the charging current is deemed to be negligable. This region would be near or at the "end" of the charging current decay curve and represent a period equal to several time constant. This approach would be particularly appropriate to situation which precluded the collection of a large amount of data in a short time frame or involved computations.

In the following sections the techniques used to implement the latter method of 'background estimation' will be discussed. 173

5.1.2 OPTIMIZATION TECHNIQUES

The process of optimization involves the examination of a local region of operation in a system followed by a prediction of how the system parameters should be adjusted to bring the system near the optimum. In an analytical laboratory, for example, it might be desirable to maximize the number of samples run during the day while simultaneously minimizing reagent consumption. The local region of operation may the number of calibration runs necessary or the amount of buffer solution required by each sample. Consequently by reducing the number of calibrations and diluting the samples more time can be made available for sample analysis and less buffer solution is required per sample.

For many years, optimization has involved value judgements based on experience and cause-and-effect relationships. By gathering data and noting trends,intelligent guesses could be made regarding the effects of changes to a particular system. This technique is satisfactory in many instances although it becomes cumbersome for complex systems. In gas chromatography, for example, experience is often a poor substitute for a plot of HETP versus flow rate to determine the optimum flowrate for a particular separation.

The use of computers has led to the development and use of the theory of optimization enabling single and multivariate optimization problems to be solved more rapidly and with greater precision than attainable by 'rule of thumb' judgement. This is not to say that all optimization problems can be solved by computing methods. Simple optimization problems requiring . little human judgement can fail to converge even in elaborate computing algorithms. 174 In chemistry, general optimization methods (128-131) and in particular applications to chromatography have been reported (132-134). Recently, computer-controlled and computer-assisted optimization have been applied to a variety of analytical instrumentation (135-137).

Computer-assisted anodic stripped voltammetry, for example, was described by Thomas, et al. (138). In their system, an initial ASV scan was performed and a signal-to-noise parameter calculated. The optimum plating time and. stirring speed were then calculated using the experimental information and predefined performance criteria to achieve a desired S/N. The calculation 'and implementation of control functions were handled by the computer whereasthe performance criteria were supplied by the operator.

5.1.2.1 SCV Optimization

The SCV system described in this chapter was optimized on- line for faradaic current sampling by a binary search method, the principle of which has been described in the section on successive approximation ADC's in Chapter 2. The binary search was controlled by two parameters, the defined optimum value and the search range. The former parameter enabled the search algorithm to decide when the optimum had been reached and the latter parameter limited the scope of the search.

In operation, the binary search algorithm was initialized by entering a "guess" for the experimental system parameters which should produce the optimum value. Experimental data were gathered under these initial conditions and compared to the 175 optimum value. This process of obtaining experimental data, comparing the results to the optimum and redefining system parameters was repeated until the results were within an acceptable tolerance of the optimum. 176.

5.2 MICROCOMPUTER SYSTEM

The microcomputer system used for the SCV experiments consisted of two microcomputers, a computer-controlled waveform generator and potentiostat, a video display terminal and a cassette recorder used to store utility programs. The system was based on a closed-loop design as illustrated by Figure 5.4. In this design the computer system acquired digital information on the nature of a physical property and produced an analogue signal in response to that information. This configuration

minimized operator interaction and maximized experimental consistency.

5.2.1. HARDWARE

The hardware for this sytem can be divided into two components, digital and analogue. This digital side consisted of the two microcomputers, the digital staircase generator and the data acquisition/display modules; the analogue side consisted of the potentiostat.

5.2.1.1. Hierarchical Computer System

Two microcomputers were used in a hierarchical experimental system. The master computer was the SDK-80 described in Chapter 4, and the slave computer was an SDK-85 based on the. Int01 8085A microprocessor. Functionally similar to the SDK-80, the SDK-85 contained a microprocessor, a resident monitor controlling a 25-key keyboard, a 6-digit LED display, 256 bytes of RAM, 60 I/O lines, and a 14-bit timer/event counter.

The serial I/O feature of the 8085A was exploited as a means of providing access to utility programs through a cassette interface. The cassette interface schematic diagram 177

cell

c w r potentiostat ADC

DAC

Cony t/h VDT SDK-85

8-bit I/O SDK-80

Figure 5.4 Microcomputer controlled SCV system 178 is shown in Figure 5.5. The interface design was based on a phase locked loop tone detector. The PLL locked onto a reference frequency controlled by an RC network. This reference frequency was set to about 5000 Hz. When a frequency was detected with a certain tolerance around the reference frequency, a logical 1 was produced. .Otherwise, a logical zero was present on the output line.

The tones for recording digital information were produced by two separate tone generators which were multiplexed.• The tone equal in frequency to the PLL reference frequency was selected to record a logical 1, and the other tone, adjusted to minimize harmonic interference, was selected to record a logical 0. The process of recording and decoding digital information is illustrated in Figure 5.6.

The 8085A serial output port can be addressed by software. By controlling the state of the serial output portl digital information was sent in serial. to the cassette interface. Similarly, serial digital information was received by the serial input port and decoded into parallel.

The serial I/O ports on the 8085A were used to read and

write program information wheareas the ditial I/O ports on the peripheral chips were used to control the SCV experiment., The digital staircase generator constructed from an 8-bit DAC (RS Componnents) is illustrated in Figure 5.7. The full-scale output of the DAC was adjusted by the output amplifier Al to. 1.28 V. Thus 256 steps could be produced with a O.E of 5 mV by applying a digital counting sequence to the DAC's input. 179

05000 Hz osc 1

4011 3911 Hz osc 2

10k 200k osc adjust 100 k 10 nF

7405 V osc .1 .7405 .01 u F t o 8085 S0 0 • CO.! 7405

osc 2 o---

l k 7451 1k 15k -VVAr-0+ 5 V 0 to 8085 SI

PLL 567 1 22 nF

25k

.nuF I

Figure 5.5 Schematic diagram for cassette interface 180

play/rec

SI/SO._

Figure 5.6 Cassette interface I/O

The data acquisition module consisted of the 8-bit counter- type ADC described in Chapter 4, controlled by the SDK-85. The analogue input to the ADC was provided by the difference amplifier of the potentiostat described in Section 5.2.1.2.

The master computer controlled the display of data on the VDT. Experimental information was Obtained from the SDK-85, scaled and displayed in graphical form on the VDT. as a 20 x 80 matrix.

5.2.1.2 Potentiostat Design

The potentiostat used for the SCV experiments is shown in Figure 5.8. The staircase waveform, offset by the circuit in Figure 5.9, was shaped by the variable bandpass low-pass filter, amplifier Al. This filter removed the switching spikes on the staircase waveform which can be of particular annoyance at the

z and ā full scale switching points. The amplifier A3 was the actual potentiostat. A reference voltage from the voltage follower A2 was summed with the input waveform at the inverting input of A3. The potential across the cell was a function of the feedback resistor Rf, the input potential and the input resistor R.. Any current drawn by the cell from faradaic or non-faradaic processes was supplied by the potentiostat 181

amplifier A3. The bandpass limiter around amplifier A3 prevented instabilities due to rapid current demands during potential steps. The effect of the limiter was to lower the response of the potentiostat to potential changes. The bandpass of the potentiostat was adjusted to comply with the data acquisition requirements of SCV experiments of. around 20 kHz.

The cell current was measured as an iR drop across resistor Rm by a differential amplifier A6. The value of Rm was selected to provide a maximum voltage drop of 0.05 V for a 40µA current signal. A gain of ten was provided by A6 although a booster amplifier also with a gain of 10 was used to provide an analogue signal of sufficient magnitude for the ADC.

The differential method of current sampling was chosen for two reasons. First, voltage sampling is easier to implement than current sampling. The gain of the sampling stage can be changing by altering the value of Rm or by adjusting the resistor networks around A6 or A7.

Second, potentiostats which sample the current through the working electrode, Figure 5.10, suffer from instabilities resulting from thermal drift, and imperfectly adjusted input offsets. Current drawn by the current sampling amplifier in

this configuration is the cause of instabilit.y In addition, •floating the working electrode provides an ambiguous reference point, as opposed to the potentiostat in Figure 5.8 with a

grounded working electrode.

The bandpass of the differential amplifier A6 was limited by the capacitors to provide as much stability as possible while producing an undistorted signal. The optimum values of the capacitors were determined empirically. 182

1 uF

74.1 A7

JVV` 10 k

0 out

3130S

47 pF 741S II A3 75k 75k 20k I 47pF :01uF==

Wv 68k 68k 741 500 k in Al I 56pF

Figure 5.8 SCV potentiostat

183

Figure 5.9 SCV waveform offset circuit

o ext in

.4 r

o output

Figure 5.10 Working electrode current sampling potentiostat

SDK-85 47nF bit 0 o bit 8 o ~ o ~ o 5k o- 10k o- bit 7 o- bit 1 (msb) + 0---1.28V logic select 531

ZN425E DAC

Figure 5.7 Staircase generator. 184

5.2.2 SOFTWARE

The software for the SCV system was divided into five modules: audio cassette interface, data acquisition, VDT display, staircase generation and SCV optimization. All of the software was written in INTEL assembly language, assembled by hand and entered into RAM on the SDK-80 or SDK-85 using the appropriate resident monitor. Utility programs which handled I/O between the two computers and the audio cassette recorder were resident in RAM whereas application programs were loaded into memory from cassette tape as

necessary.

.5.2.2.1 Cassette Interface

Software was written to enable program information to be written to and read from a standard audio cassette recorder (National Panasonic S-29), by the SDK-85. Data bytes were recorded using a 10-bit format consisting of a start bit, eight data bits and a stop bit as illustrated by Figure 5.11; each recorded bit is referred to as a frame. The read and write routines made use of the special serial I/O ports on the 8085-A microprocessor and the two masking instructions RIM (Read Inter- rupt Mask) and SIM (Set Interrupt Mask). The interrupt mask is a byte of which the most significant bit is either written to the serial output port (SIM), or read from the serial input port (RIM) .

The operation of the write routine is shown by the flowchart in Figure 5.12. First the start bit was written to the serial output port by setting the carry bit equal to 1, rotating the carry bit into the MSB of the interrupt mask and executing a SIM instruction. After a p-eset delay of 2.5 ms the MSB of the data byte was rotated into the carry bit, the carry bit rotated 185 into the MSB of the interrupt mask and a SIM instruction executed. This process was repeated for each of the eight bits in the data byte. Finally, the carry bit was cleared to zero, rotated into the MSB of the interrupt mask and output as the stop bit.

start stop hex 32

Figure 5.11 Cassette data byte format

The read routine described by the flowchart in Figure 5.12 operated similarly. The RIM instruction was executed repeatedly and the MSB of the interrupt mask examined after each execution until a zero-to-one transition at the serial input port was detected. The routine then entered a wait loop for 3.75 ms or 1.5 frames in order to position the next read in the centre of the first bit-frame.

A RIM instruction was executed next, the MSB of the interrupt mask rotated into the carry bit, the carry bit rotated into the LSB of a holding byte and a wait loop entered for 2.5 ms or one frame. This process was repeated for eight cycles by which time the original LSB of the holding byte had became the MSB. After the last bit had been read, the final wait loop positioned the next read near the middle of the stop bit frame.

Sequential data bytes were detected by the zero-to-one 186 transition between ,stop and start bits. This had the advantage of automatically re-aligning the read algorithm with each byte thus minimizing errors resulting from fluctuations in tape speed.

5.2.2.2 Data Acquisition

Data acquisition was controlled by software for all SCV experiments. The software interface to the 8-bit ADC was achieved by direct use of the I/O ports on one of the 8155 Memory/I/0 chips on the SDK-85. In this application, Port A was used to input the eight data bits from the ADC, Port B was used to output the convert/reset signals and control the T/H amplifier. The ADC control software consisted of a subroutine that switched the T/H to the hold mode, initialized a conversion, waited for the EOC (setting the carry bit in case of an over- range), read the ADC data byte, switched the T/H amplifier to the track mode and reset the ADC. The ADC was always in a known state at the end of each conversion.

5.2.2.3 VDT Display

An interface between the SDK-80 and the SDK-85 enabled recently acquired data to be displayed during the course of an experiment. The interface consisted of a parallel link between an 8255 peripheral interface chip on the SDK-80 and an 8155 memory/interface chip on the SDK-85. Unlike the interface between the Alpha-16 and the SDK-80, no additional components were required; the interface was initialized by software and all handshaking signals were processed by the interface chips.

Graphic display of data points was accomplished by using the VDT cursor control characters which enabled the cursor to 187

write start bit yes

delay shift 1%z frame

write data bit read data bit

shift load hold byte delay

read write stop end bit bit

delay (exit)

(exit

Figure 5.12 Flowcharts for cassette write and read routines. 188 be positioned at any point in a 20 x 80 matrix. The cursor control characters, although non-printable characters, were treated as display characters. Thus, to move the cursor from position (1,3) to position (6,5), for example, five "move up" characters would be "displayed" followed by two "move right" characters. An arbitrary zero-zero point was defined as the first display character on the bottom row. The X-axis extended 80 characters to the right and the Y-axis extended 20 lines vertically above this character. Data points were scaled to fit within a 20 x 80 matrix and their coordinates calculated with respect to the current cursor position. The cursor was then incrementally moved by non-display characters along each axis to the specified position, at which a display character was written.

5.2.2.4 Staircase Generation

The flowchart for staircase generation is shown in Figure 5.13, and is straightforward. The value of a counter incremented at a preset rate was output to the 8-bit DAC. The rate of incrementation determined the step duration and the incrementing constant was equal to one, allowing 256 steps to be applied.. By increasing the incrementing constant to two, E could be doubled, reducing the number of steps possible by half. 189

zero counter

output to DAC

,r increment counter by constant

compare to counter max. delay

(exit

Figure 5.13 Flowchart for staircase generation. 190

5.2.2.5 SCV Software

The software for the microcomputer controlled SCV experiments consisted of two sub-routines, the zero-current routine and the scan routine. The purpose of the zero-current routine was to determine the extent of the charging current contribution and optimize the sampling time by a binary search technique. The flowchart for this routine is shown in Figure 5.14. The binary search was designed to operate for a preset number of iterations. If the search failed to produce an optimum sampling time by the final iteration, the experimental system was re- initialized and a message was displayed on the VDT indicating. the resultant sampling time and its associated current value which allowed the operator to change the parameters required. by the routine and start another search. If the search succeeded in finding an optimum sampling time, this value was returned to the calling program.

The zero current routine was initialized by entering three parameters interactively: the optimum current range acceptable the number of iterations for the binary search and an initial guess for the optimum sampling time. The experimental system was then initialized, the ADC reset and the T/H amplifier placed in the track mode. A potential step was applied to the cell and a delay, equal to the initial guess for the optimum sampling time in milliseconds, executed. At the end of the delay, a current value was obtained from the data acquisition routine. If this value was less than the optimum range, the sampling time was decreased by one half; if the current value was greater than the optimum range, the sampling time was within the -optimum range; the search was halted. Assuming that the first attempt 191 was not successful, the next potential step was applied to the. cell and another current value obtained from the new sampling point. The same search criteria were applied to the new value but the sampling time was increased or decreased by one half the difference between its present value and its previous value, rather than by one half of its present value.

Progressing in this manner, each step moved the sampling time towards the optimum by increasingly smaller steps. Figure 5.15 illustrates the binary search on an hypothetical charging_ current delay. The optimum range is marked by the solid vertical bars and the sampling point from each iteration is numbered. Notice that if the specified range is too narrow, the search would oscillate for several iterations around the optimum. Also a poor initial guess would increase the probability of non-convergence within a small number of iterations.

The SCV scan sub-routine, -outlined by the flowchart in Figure 5.16, consisted of a step generation and data acquisition procedure for a single step which were repeated for each step in the sweep. In the work described in this chapter, the sweep was equal to 255 steps.

Prior to the first step of the sweep, a value of t was calculated from the optimum sampling time produced by the.zero- current routine. Typically, t was set equal to the optimum sampling time. The staircase generation routine was called to output the first step to the cell. After a wait of t, the data acquisition routine was called to capture the cell current. A delay of t - t' seconds followed; data was passed to the SDK-80 The first step procedure was repeated for each step in .the staircase. 191 was not successful, the next potential step was applied to the cell and another current value obtained from the new sampling point. The same search criteria were applied to the new value but the sampling time was increased or decreased by one half the difference between its present value and its previous value, rather than by one half of its present value.

Progressing in this manner, each step moved the sampling time towards.the optimum by increasingly smaller steps. Figure 5.15 illustrates the binary search on an hypothetical charging current delay. The optimum range is marked by the solid vertical bars and the sampling point from each iteration is numbered. Notice that if the specified range is too narrow, the search would oscillate for several iterations around the optimum. Also a poor initial guess would increase the probability of non-convergence within a small number of iterations.

The CV scan sub-routine, -outlined by the flowchart in Figure 5.16, consisted of a step generation and data acquisition procedure for a single step which were repeated for each step, in the sweep. In the work described in this chapter, the sweep was equal to 255 steps.

Prior to the first step of the sweep, a value of t was calculated from the optimum sampling time produced by the zero- current routine. Typically, t was set equal to the optimum ! sampling time. The staircase generation routine was called to output the first step to the cell. After a wait of t, the data acquisition routine was called to capture the cell• current. A delay of t - t' seconds followed; data was passed to the SDK-80 The first step procedure was repeated for each step in the staircase. increase delay

Figure 5.14 Flowchart for cell time constant approximation.

'window'

II 3 4 .2 Figure 5.15 Binary search example; convergence on the fourth iteration. 193

optimize

step

wait to t'

acquire data

send to SDK-80

Figure 5.16 SCV scan flowchart 194

5.3 APPLICATIONS

The software routines described in the previous sections were linked into one main program which controlled the optimized SCV system. This program enabled the operator to key in the values for the binary search, start and stop the SCV scan and. display the staircase voltammogram on the VDT. The execution of a typical SCV experiment, Figure, 5.17, was as follows:

1. The utility routines were loaded into the SDK-80 and SDK-85 from the cassette tape. recorder.

2. Similarly, the main program was read into the SDK-85.

3 The ele trochemical cell was prepared and the solution degassed.

4. The main program was started and the binary search parameters entered interactively. After the parameters were entered, the program entered a hold mode until. the SCV scan was started.

5. The SCV experiment was started and from this point was controlled exclusively by the system. First the zero current routine was executed and the binary search performed. By specifying the scan to start in an electro- chemically inactive region, the charging current was sampled without interference from faradaic processes.

Once the optimized sampling time was determined the scan routine was called which, after initializing the staircase ramp, generated 255 steps, acquired data at the optimized sampling point for each step, and transferred the data to a buffer in the SDK-80. At the end of the experiment, the system was re- 195 initialized and control was returned to the operator.

If the optimized sampling time was not located by the binary search, however, the sampling time and cell current for the final iteration were displayed on the VDT, the system re- initialized and control returned to the operator.

6. The experimental data in the SDK-80 buffer could be displayed on the VDT graphically or numerically and the sequence could either be repeated from step three or four, or terminated 196 key in bootstrap to initialization SDK-85 routine

read utility reset programs to staircase SDK-85 Jr reset key in ADC bootstrap to SDK-80 Jr t/h to track read utility programs to SDK-80 (return)

read SCV program to SDK-85

prepare electrochem cell

key in optimization parameters

1 execute main program no no, mēSEERge yes

display display sample time data on and current VDT yes call initialization routine

Figure 5.17 Optimized SCV main program 197

5.3.1 REAGENTS AND ELECTRODES

The chemicals used in the experimental trials were of analytical reagent grade (Analar) and were used without further purifiction. All solutions were prepared with distilled water purified by passage through a mixed bed ion-exchange column. Solutions were de-oxygenated with oxygen-free nitrogen for 15 minutes prior to analysis and a layer of nitrogen maintained over the solution during the analysis.

The working electrode was a disc 4mm in diameter composed of Tokai glassy carbon. (The working electrode from the wall- jet cell of Chapter 4.) A silver-silver chloride reference electrode (1MKC1) and a platinum counter electrode completed the three electrode polarographic cell.

5.3.2 EXPERIMENTAL

The first phase of the experimental work consisted of examining the charging current to determine the characteristics of its delay in the absence of electroactive compounds by using a series of electrolyte solutions containing between 0.05 M and 0.1 M potassium chloride. In order to obtain a sufficient number of data points on the charging current delay using the 8-bit ADC with a conversion time of about one milli- second, a series of delays were generated and sampled sequen- tially. A square wave pulse train with a frequency of 0.5 Hz an amplitude of -10 mV versus the silver-silver chloride reference electrode, was applied to the cell. By sampling the current from 200 successive pulses at intervals increasing by 100 us for each pulse, it was possible to reconstruct a scan for the charging current over a period of 20 ms. The technique is illustrated by Figure 5.18. 198

For the electrolyte solutions used, it was found that the charging current decayed to a negligible value of less than 150 nA within 12 ms. By plotting the negative logarithm of the current versus time, the time constant for the cell was found to be typically between 0.9 and 1.1 ms. An approximation of the cell resistance as 200 ohms led to a double layer capacitance between 4.5 and 5.5 pF which agreed with the high capacitance effects of glassy carbon electrodes as mentioned by Gunasingham (111).

1 3 4

reconstructed 0`2 curve 3 0\4 o\ S

Figure 5.18 Staggered data acquisition

The zero current routine was then tested using identical electrolyte solutions. Typical parameters entered into the routine were as follows: . current range: 0.5 - 0.6 pA sampling time: 8 ms iterations: 8 For this example, the last iteration would alter the sampling time by 60 yis; the.smallest delay possible by the delay routine ,ii ed in the binary search was 20. ps. The optimized sampling

time resulting from these parameters ranged between 9.6 and 199

9.8 ms. These values, relative to the cell time constant, were in good agreement with reported sampling times (123, 126).

It was found that the optimized sampling time decreased. from solutions of low electrolyte concentration to those of higher electrolyte concentration but this effect was expected as the cell time constant decreases across this series primarily due to the reduction in the cell resistance.

The final stage of the experimental work consisted of running a series of SCV scans on solutions containing electro- -5 active compounds. A 2.0 x. 10 M Cd2+ solution with a 0.1 M Kel supporting electrolyte was used initially. The SCV system was set up to scan from zero to -1.28 volts versus a silver-silver chloride (1 M KC1) reference electrode in 5-millivolt steps.. For a typical analysis the following parameters were entered into the zero-current routine:

current range: 0.5 to 0.7 pa sampling time: 7 ms iterations: The solution was de-gassed and the SCV system started. For this concentration of cadmium the binary search consistantly located the optimum sampling time at approximately 6.0 ms and completed the scan in approximately 1.5 seconds. The peak current for this solution was 35 jaA and the FI was -0.60 V versus the reference electrode used.

A second series of solutions containing various metal ions was prepared and examined with the automated SCV system; the results are tabulated in Table 5.1. 200

SUPPORTING SAMPLE CONC. E1 (V) ip (uA) ELECTROLYTE TIME (MS) 2

Cd 2 x 10-5M 0.1M KCl 6.0 -0.60 35+.9 -5M Zn+2 2 x 10 0.1M KCl 6.1 -0.92 24+.7 T1+ 2 x.10-5M O.1M KCl 5.8 -0.48 28+.9 Pb+ 2 2 x 10-5M O.1M KCl 6.4 -0.28 31+.8

Table 5.1 Comparison of SCV scan features

The half-wave potentials from the SCV voltammograms are listed to show the,variation which can be obtained. _Calculated from standard reduction tables (139) , the halfwave potentials versus the silver-silver chloride reference electrode are:

Cd2+ -0.62 V Zn2+ -0.98 V T1+ -0.55 V .Pb2+ -0.34 V

It was found that the experimentally determined half-wave potentials varied as much as 5% from day to day which reduced the applicability of SCV to the qualitative analysis of mixtures. The relative positioning of the half-waves, however, varied only 1%. In accordance with SCV theory, the peak potentials were shifted consistantly in an anodic direction.

Variations in peak current between 2 and 3.5% could be attributed to two sources. First the optimized sampling time was not constant between individual analyses. As shown by Figure 5.20 typical sampling times increased over several days.

The trend showed only a random increase and no adherence to

201 either a linear or a non-linear relationship was observed. The cause of the trend, although certainly the result of many factors, can be attributed primarily to changes of the surface of the glassy carbon working electrode. The dynamic nature of the surface or the glassy carbon electrodes used in electrochemical analysis has been previously noted (110, 111, 115, 116). Modifications to the surface of glassy carbon can have several sources, for example oxidation and reduction of surface groups and chemisorption. The net effect is to increase the double layer capacitance thus extending the cell time constant.

0 0

O 0 0

O 0 _ 6 0

ms 3 4 . 5 6 7 8 9 10 days

Figure 5.20 Long term variations in optimized sampling time 202

A longer time constant in turn leads to an extended sam-, . pling time and corisinndingly lower peak current values.

By physically cleaning the working electrode (abrasion) its surface can be 'renewed' although it is not possible to produce identical surfaces each time. Chemical modification of the surface as reported by Gunasingham (111) may prove to be a more satisfactory approach to obtaining reproducible surfaces although the research in this area is still in its initial stages. Physically cleaned surfaces yielded sampling times within a range of 3% for a particular electrolyte. For 0.1M KC1 the value was 6.0+0.3ms; this value was valid only for 5 mV steps with larger steps resulting in longer sampling times.

The second possible source of variation in peak current could be attributed to a combination of competing faradaic processes and a reduction in the ability of the working electrode to exchange electrons with electroactive species. Both of these effects could result from modification to the surface of the working electrode. Although specific competing faradaic reactions have not been characterized the oxidation and reduction of surface groups on the working electrode could cause current to be subtracted from or added to the peak current of the primary reaction of interest. As surface groups became established, less electrode area would be available for use by electroactive species entering the double layer thus causing an overall

decrease in peak current as observed.

For semi-quantitative analysis, the lengthening of the sampling time was used as an indicator of the state of the

working electrode. It was found that between five and ten analyses could be performed between electrode cleanings depen- 203 ding on the nature and concentration of the analyte. A single analysis consisted of preparing a calibration curve based on the peak heights for a set of standard solutions and matching the peak height from the scan of an 'unknown' solution to the curve. It was found that both the calibration curve and unknown analysis had to be performed on a particular working electrode surface over a period during which the sampling time had not varied more than 2%. The matching of unknown solution peak heights to calibration curves prepared on a different electrode surface proved to be unreliable as shown in Table 5.2.

TRUE VALUE CALIBRATION CALIBRATION CALIBRATION CURVE A CURVE B_ CURVE C

. 1.5 x 10-5M 1.5 x 10-5M 1.9 x 10-5M 1.2 x 105M

Table 5.2 Variations in analyses using unrelated calibration curves

The agreement between the true value and the value determined from calibration curve A which was produced on the same electrode surface is excellent. Serious deviations occur, however, when calibration curves generated from different electrode surfaces (altered by cleaning) are used.

The automated SCV system enabled changes in the electrode surface to be detected independently of the concentration of electroāctive compounds. Although the peak height for a staircase voltammogram could decrease by two mechanisms, lower concentrations of electroactive compounds and longer sampling times, only the latter mechanism was important in determining the state of the working electrode. As the ability of the working electrode to support reduction of the analyte decreased, 204 a point was reached where the relevant calibration curve became unreliable. For semi-quantitative analysis this point was identified by a 2% increase in the optimized sampling time.

At the 2% point the working electrode was cleaned and a new calibration curve constructed. The speed of the analysis, which averaged 1.5 seconds, reduced the tedium of continual calibration to a minimum. In a more advanced SCV system, automatic calibration could be initiated as the performance of the working electrode fell to an unacceptable level. This would

increase the utility of the working electrode between cleanings.

Although not investigated here, chemical modification of glassy carbon electrodes should prove to be an attractive alternative to physical cleaning. By creating a chemically defined surface, an electrode could be produced which would have consistant features, reducing the need for frequent calibration. As the surface became altered through repeated use the accompanying decrease in performance would be detected and the surface could be regenerated perhaps in situ. Until the glassy carbon is examined in more detail and suitable chemical modifiers found, this concept will remain hypothetical.

5.3.3 VDT DISPLAY

The VDT display, although providing a rapid means of viewing the results of an experiment, had the disadvantage of being a temporary display. In order to save the results of an experiment it was necessary to copy either the raw data from the data buffer or the scaled data from the VDT display buffer. A further disadvantage was the effect on the display of the severe quantization imposed by a vertical resolution of 20; smooth curves were transformed into square-edged graphs.

205

4*** __ *4#4*4*4*4

-4 ------4* #*#

--.Z) =T60, -.71)

30 1 4* * * 1 1 I0 1 1

10 #

~ # . 1 # ### ## ####

t I -.50 -.60 -.70

Figure 5.21 Staircase voltammogram from VDT ( a5); 2selective elimination of data ( b ). 2 x 10 Cd . 206

Although hardware limitations prevented a solution to the first disadvantage, a simple procedure was used to overcome the second. By selectively omitting display points, a curve could be re-constructed with "apparently" greater resolution; the eye supplied the missing resolution. Figure 5.21 demonstrates the effect of the procedure for a SCV voltammogram of 2 x 10-5M Cd2 .

Figure 5.22 shows the effect of the sampling time on the same cadmium solution of the previous figure. The curve representing the shorter sampling time is shifted anodic and has a higher peak potential than the curve for a relatively longer sampling time.

A Ti+ solution of 2 x 10-5M in Figure 5.23. is included in comparison to Figure 5.21 to shown the variation in peak shape between different species of the same concentration.

207

30 # 1 00 1 0 0 or=.7

120 Oog =.3 0

0 10 *0

-. 40 -.50 • -.60

Figure 5.22 Effect of O( on staircase voltammograms.

I 20

-.40 -.0 -!60

Figure 5.23 SCV scan of 2 x 10 - T1. 208

CONCLUSIONS AND SUGGESTIONS FOR FURTHER WORK

Microcomputer control offers a significant advantage to electrochemical instrumentation in the inherent ability to manipulate information, a concept which is central to modern analytical chemistry. In any chemical analysis, the original information is transduced into another physical form for interpretation: a chemical signal or event from a source is translated into an analytical signal by a detector and finally into a numerical quantity. The three electrochemical systems described in this work shared the common feature of experimental control based on the on-line evaluation of information acquired at precise intervals. This process involved three steps. First, information was obtained from the experiment and translated into digital form. Second, the digital information was processed by applying various arithmetic functions to arrive at what can be called the decision. Finally, the decision was translated into a control signal which was then fed back to the experimental system. The most complex aspect of this three step process was the manipulation of the acquired data to produce the control signal. It is significant that the physical feature common to the three experimental systems was the computer network which performed this function. Traditionally, the use of digital computers in chemical experimentation has involved a rather daunting whole problem approach; that is, the chemist had to consider each aspect of the experimental design from 209 the digital acquisition of the analytical signal to the digital-to-analogue conversion of the control signal. In many instances the advantages of moving into the digital domain were outweighed by the difficulty of implementation. The new generation of microcomputers and associated digital devices are removing this obstacle by incorporating into themselves many of the timing, control and synchronization elements which once needed to be handled externally in the computer/experiment interface. The greater simplicity in experiment design afforded by these improvements has already manifested itself in a flood of commercial digital analytical instrumentation, the impacf of which on electroanalytical chemistry should be substantial. It would be possible with current technology to design a programmable electrochemical instrument which would feature interactive experimental design. An experiment could be set-up such that all of the experimental parameters such as applied waveform, data acquisition times, potentiostat bandwidth, scan range and sensitivity were specified under software-control. Experiments could be run and optimized on-line, storing the resulting data on some suitable medium for future analysis, possibly by the same instrument. Of parallel importance with the use of digital techniques in electrochemistry is the development of an adequate theoretical basis for application. Although theoretical descriptions have been put forward for a variety of potential step voltanvmetric techniques, primarily ones involving dropping or hanging mercury drop electrodes, a number of problems- remain unsolved. With respect to the SEP and SCV experiments described in chapters 4 and 5 210 a promising avenue of investigation would be the development of a theoretical model for potential step processes along hydrodynamic lines. This would further the utility of the wall-jet cell in particular to analyses in flowing streams by providing a firm basis for the application of digital methods. Feasibility studies into the behaviour of the ring-disc electrode in flowing streams have indicated. that this approach could be successful. "Finally, the power of the computer could be united with the theoretical model using optimization techniques to determine the best condition for a given analysis. For example, the current produced during SEP analyses under hydrodynamic comditions is a function of the scan rate, flow rate, and the distance of the working electrode from the end of the jet. By enabling the computer to control these parameters, an optimum configuration could be achieved during the analysis which would serve to minimize the use of resources and analysis time while providing the maximum amount of useful information: a step closer to THE ANSWER at no cost. 211

APPENDIX 1

General Purpose Interface ( GPI )

The general purpose interface ( GPI ) was designed to facillitate the rapid interfacing of data and control signals between the Alpha-16 minicomputer and laboratory experimentation. The following features were incorporated into the design:

2-to-1 multiplexed 16-bit input channel 16-bit output channel command bit output flag bit input conditional I/O control 3 monitor led's decade frequency clock, 1MHz to 1Hz TTL buffered switch +5 volt bus +15 volt buses digital ground

The GPI used TTL. compatible,- positive true logic externally and negative true'logic internally for the Alpha-16 I/O bus. All inputs and Outputs were buffered with open collector logic; the 16-bit I/O,ports were latched. Connections to the GPI were made using standard 4mm plugs ( RS 444-179 ) or 4mm in-line. stackable plugs ( RS 444-539 ). The connection to the Alpha-16 was made via a 43-way edge connector attached to the control card of the GPI. The following figures illustrate the design considerations. 212

The GPI was controlled or monitored using the I/O commands available in the Alpha-16 instruction set.. mnemonic operand code function

RDA :61 :5961 read word to A conditionally RDX :61 :5B61 read word to X conditionally INA :62 :5862 input word. to A unconditionally INX :62 :5A62 input word to X unconditionally WRA :63 :6D63 write word from A conditionally WRX :63 :6F63 write word from X conditionally. OTA :64 :6C64 output word from A unconditionally OTX :64 :6E64 output word from X unconditionally SEL :65 :4065 set control bit SEL :66 :4066 clear control bit SEL :67 :4067 clear flag bit SEN :60 :4960 Skip if flag is set SEN :61 :4961 if set, input buffer full SEN :63 :4963 if set, output buffer full SEN :64 :4964 skip if control bit set

•213

1k +5V PBOo-

7404 7401

PB to-

7404 7401 +5V 1k PB 2o PD .yam0 oPERC I 7401 7410

PB3o

7401

PB 4o-

• 74 04 o+5V 7401 exec o IOX in o out o 74.10

Figure A1.1 Device decode logic. This circuit decodes the device address assigned to the GPI. The device address is present on the Alpha-16 P-bus during the execution if I/O instructions. GPI address, :OC 214

7404's

~O FCO 7404's FBO 74141 >0-- FC 1

FB1 2 FC2

FB2 FC3

FC4

PERC FC5

>0--FC6

FC7

Figure A1.2 Function decode logic. This circuit decodes the function specified by certain I/O instructions. Function information is present on the Alpha-16 F-bus.

function description FCO none FC1 conditional data input FC2 unconditional data input FC3 conditional data output. FC4 unconditional data output FC5 set control bit FC6 reset cōntrol bit FC7 reset flag bit 215

bit() }

data input in latch 7475x4 bit15

enable cn tl enable

bit0

data output out latch

7475 x 4

bit15

+5V

Figure A1.3 16-bit I/O latch logic. Notes the input latch is disabled during data transfer to the Alpha-16. The output latch is disabled during data transfer from the Alpha-16. Output latch control resets D-bus for output to GPI. 216

WINIMNIMMI channel A

A B MPXR DECADE CLOCK channel B

1 MHz-1Hz

1MHz

-16 control- I/0 CONTROL CARD

latch control and 16-bit input 16-bit I/O

0 in I/O 0 <16-bit 16-bit I/O LATCH

115 15 15 out

Figure A1.4 GPI interconnection diagram.

217

APPENDIX 2

Useful op-amp circuits Several useful op-amp circuits are presented below with their respective input/output relationships. It is assumed that power supply and offset connections are made. by the user according to the manufacturer's recommended specifications for the particular op-amp employed, and are therefore not shown.

Voltage follower

E = E.i

Inverting buffer

Rf = R. R = 10%Ri•

218

Difference amplifier

R1 + Rf Eo l R2 + R3 ) E2

! E1

Eo = - E1

Inverting amplifier if R1 = R2, and R3 = R4

-R E = f E,1 R.1 Rf R i Rf+Ri

R2 minimizes drift.

Differentiator

-R0 C dEi / dt

high frequency cutoff F = 1 / 21TR . C 1

low frequency cutoff F1 = . 1 / 2ITR0C 219: Current-to-voltage converter

Eo = -iR

Differentiator with high frequency cutoff

C o

E Eo = -RoC. dEi/dt

R = 100k C _ .001uF

R.1 = lk C1 = . 01uF = 100k

High-pass active filter

cutoff frequency 1 / 2ifR1C 1 - 220

Peak follower

Eo = E i max

Non-inverting amplifier

R. + Rf R. E. 1 1

Summing amplifier

+E2 +E3 )

Rb / 4 221

Low-pass active filter, second order

cutoff frequency fo 2i / R1R0C1C2

Integrator

-1 E E.dt 0 R.0i o 1 Jo 222

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