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Device Models for Reference Design Pallavi Sugantha Ebenezer Iowa State University

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Device Models for Reference Design Pallavi Sugantha Ebenezer Iowa State University Iowa State University Capstones, Theses and Graduate Theses and Dissertations Dissertations 2018 Device models for reference design Pallavi Sugantha Ebenezer Iowa State University Follow this and additional works at: https://lib.dr.iastate.edu/etd Part of the Computer Engineering Commons, and the Electrical and Electronics Commons Recommended Citation Ebenezer, Pallavi Sugantha, "Device models for reference design" (2018). Graduate Theses and Dissertations. 16768. https://lib.dr.iastate.edu/etd/16768 This Thesis is brought to you for free and open access by the Iowa State University Capstones, Theses and Dissertations at Iowa State University Digital Repository. It has been accepted for inclusion in Graduate Theses and Dissertations by an authorized administrator of Iowa State University Digital Repository. For more information, please contact [email protected]. Device models for reference design by Pallavi Sugantha Ebenezer A thesis submitted to the graduate faculty in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE Major: Electrical Engineering (Very Large Scale Integration) Program of Study Committee: Randal Geiger, Major Professor Degang Chen Doug Jacobson The student author, whose presentation of the scholarship herein was approved by the program of study committee, is solely responsible for the content of this thesis. The Graduate College will ensure this thesis is globally accessible and will not permit alterations after a degree is conferred. Iowa State University Ames, Iowa 2018 Copyright © Pallavi Sugantha Ebenezer, 2018. All rights reserved. ii DEDICATION I would like to dedicate this thesis to my parents and to my sister Nivetha without whose support I would not have been able to complete this work. I would also like to thank my friends and family for their loving guidance and financial assistance during the writing of this work. iii TABLE OF CONTENTS Page LIST OF FIGURES ............................................................................................................ v LIST OF TABLES ............................................................................................................ vii NOMENCLATURE ........................................................................................................ viii ACKNOWLEDGMENTS ................................................................................................. ix ABSTRACT ........................................................................................................................ x CHAPTER 1. INTRODUCTION: ...................................................................................... 1 Background and Motivation .......................................................................................... 2 Objectives ...................................................................................................................... 8 Thesis Outline ................................................................................................................ 9 CHAPTER 2. DISCRETE IMPLEMENTATION OF KUIJK BANDGAP CIRCUIT WITH EXPERIMENTAL VALIDATION: ..................................................................... 10 Simulation Results For Generic Spectre Models ......................................................... 12 Simulation Results With Ideal Diodes And Practical Resistor (TC) Model ............... 13 Simulation Results With 1N4148 Diode Model .......................................................... 14 Measurement Results Using Low Offset Opamp LTC1150CN8 ................................ 16 Results and Discussions ............................................................................................... 17 Conclusion ................................................................................................................... 19 CHAPTER 3. IMPLEMENTATION OF KUIJK BANDGAP CIRCUIT WITH EDU1000 MOS ARRAY JUNCTION DIODES AND EXPERIMENTAL VALIDATION:................................................................................................................. 20 Characterization Of EDU1000 .................................................................................... 20 Measurement Results ................................................................................................... 22 Measurement Results Using Low Offset Opamp LTC1150CN8 and EDU1000 ........ 23 Results and Discussion ................................................................................................ 25 Conclusion ................................................................................................................... 26 CHAPTER 4. UNAUTHENTIC IC COUNTERMEASURES FOR FUTURE INTEGRITY OF THE SEMICONDUCTOR SUPPLY CHAIN ..................................... 28 Classification Of Unauthentic Parts ....................................................................... 28 Challenges Posed .................................................................................................... 30 Contribution of This work ...................................................................................... 30 Trigger Circuit ........................................................................................................ 35 Clock Generation Circuit And Non-overlapping Clock Generator ........................ 36 4T Memory Cell Based PUF Circuit ...................................................................... 38 Generation Of PUF Code And Comma Sequence ................................................. 40 iv CHAPTER 5. CONCLUSION.......................................................................................... 45 REFERENCES ................................................................................................................. 46 v LIST OF FIGURES Page Figure 1.1 Basic concept of Bandgap reference circuits .................................................. 1 Figure 1.2 Kuijk Bandgap reference circuit ..................................................................... 6 Figure 1.3 Output voltage reference Vref: (a) Sensitivity to n (b) Sensitivity to m ........ 7 Figure 1.4 Sensitivity to alpha ......................................................................................... 8 Figure 2.1 Kuijk Bandgap Reference circuit design ...................................................... 10 Figure 2.2 Simulation results with ideal resistors and diodes ........................................ 12 Figure 2.3 Simulation results with ideal diode and practical resistor models ............... 13 Figure 2.4 Simulation results with 1N4148 diode model .............................................. 15 Figure 2.5 Simulation results with 1N4148 diode and practical resistor models .......... 16 Figure 2.6 PCB and laboratory setup ............................................................................. 16 Figure 2.7 Measurement results in the Laboratory ........................................................ 17 Figure 2.8 TC of Bandgap reference circuit .................................................................. 18 Figure 3.1 Layout of EDU1000 MOS array .................................................................. 20 Figure 3.2 I-V characteristics of Single transistor ......................................................... 22 Figure 3.3 Laboratory setup using EDU1000 ................................................................ 23 Figure 3.4 Kuijk Bandgap Reference circuit using EDU1000 ...................................... 24 Figure 3.5 Measurement results using EDU1000 .......................................................... 24 Figure 3.6 TC of Bandgap reference .............................................................................. 26 Figure 4.1 Two-level classification of unauthentic parts ............................................... 29 Figure 4.2 Block diagram of proposed PUF circuit ....................................................... 33 Figure 4.3 4T Memory cell ............................................................................................ 34 Figure 4.4 Threshold Trigger Circuit ............................................................................. 35 vi Figure 4.5 Transfer curve of the supply threshold trigger circuit .................................. 36 Figure 4.6 Ring oscillator for clock generation ............................................................. 37 Figure 4.7 Non- overlapping clock generation .............................................................. 37 Figure 4.8 Non-overlapping clock signals ..................................................................... 38 Figure 4.9 Sub-Threshold PUF Generator; (a) Circulating Shift Register (b) Components of the Shift Register ................................................................. 39 Figure 4.10 Operation of Shift Register; (a) T1 is ON and T2 is OFF (b) T1 is OFF and T2 is ON ................................................................................................ 40 Figure 4.11 Memory cells with deterministic offset; (a) Skewed inverters (b) Memory cells generate zero and one at the output respectively ................... 41 Figure 4.12 Simulation results of the PUF Code ............................................................. 43 vii LIST OF TABLES Page Table 2.1 Comparison of performance using 1N4148 diodes . .................................... 18 Table 3.1 Comparison of performance using EDU1000 junction diodes . ................... 25 viii NOMENCLATURE BGR Bandgap reference circuit CMOS Complementary
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