University of South Carolina

From the SelectedWorks of Kang Peng

Winter November 26, 2016

Modeling of Wide Bandgap Power Semiconductor Devices—Part I Kang Peng, University of South Carolina

Available at: https://works.bepress.com/kang-peng/2/ IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 2, FEBRUARY 2015 423 Modeling of Wide Bandgap Power Semiconductor Devices—Part I Homer Alan Mantooth, Fellow, IEEE, Kang Peng, Student Member, IEEE, Enrico Santi, Senior Member, IEEE, and Jerry L. Hudgins, Fellow, IEEE (Invited Paper)

Abstract— Wide bandgap power devices have emerged as an frequency of operation. This has created a growing need for often superior alternative power switch technology for many power device technologies that can deliver high temperature, power electronic applications. These devices theoretically have high-power density, and high-frequency operation. For excellent material properties enabling power device operation at higher switching frequencies and higher temperatures compared example, a variety of applications in the aircraft, automotive, with conventional silicon devices. However, material defects and energy exploration industries require power conversion can dominate device behavior, particularly over time, and this systems to operate at an ambient temperature significantly should be strongly considered when trying to model actual > 200 °C, far beyond Si material limits. Consequently, a new characteristics of currently available devices. Compact models generation of so-called wide bandgap semiconductor devices of wide bandgap power devices are necessary to analyze and evaluate their impact on circuit and system performance. has emerged as viable replacements for the current Si-based Available compact models, i.e., models compatible with circuit- power devices. level simulators, are reviewed. In particular, this paper presents A substantial amount of research and development activity a review of compact models for silicon carbide power diodes and has occurred over the past 20 years in the silicon carbide (SiC) MOSFETs. and gallium nitride (GaN) fields. These efforts have deliv- Index Terms— Gallium-nitride (GaN), modeling, power device ered several classes of power semiconductor devices, with modeling, power semiconductor devices, silicon-carbide (SiC), voltage ratings from 30 V to 15 kV and growing, for a wide wide bandgap. variety of applications. Circuit and system researchers have collaborated in parallel to demonstrate the efficacy of these I. INTRODUCTION device technologies in demonstration designs ranging from OWER electronics can be defined as the application of laptop chargers (200 V) to plug-in hybrid electric vehicle Psolid-state electronics to condition, control, and convert battery chargers (1200 V) to fault current limiters for the electric power. With increasing concern for energy delivery electric power grid (10 kV). The ability of these devices to and environmental protection, power electronics is playing an switch at higher frequencies than their Si counterparts has increasingly important role in human society. Power semi- led to system-level benefits in volume or efficiency even at conductor devices are the core solid-state components in operational temperatures where Si is suitable. the overall power conversion system, and they most often At present, SiC and GaN are the most promising among consume the largest portion of power losses in that system. all wide bandgap semiconductor materials [1]. Table I [2] Therefore, the development of power semiconductor devices compares the material properties of Si, SiC, and GaN. The SiC has been the driving force in the progress of power elec- and GaN have almost a three times larger bandgap (∼3eV) tronics systems. Recently, silicon (Si)-based devices have compared with Si (∼1 eV). The breakdown electric field of dominated the power device market due to mature and well- SiC and GaN is one order of magnitude higher than that established fabrication technology for Si. However, there of Si. The higher breakdown electric field enables the design have been applications where Si power electronics have not of wide bandgap power devices with thinner and higher doped made the inroads necessary for widespread deployment due voltage-blocking layers. For unipolar power devices, this can to insufficient thermal capabilities, voltage breakdown, or yield a lower ON-state voltage drop and conduction loss. For bipolar power devices, this can lead to a shorter switching Manuscript received August 12, 2014; revised October 20, 2014; accepted October 23, 2014. Date of publication November 26, 2014; date of current time and lower switching loss. The high thermal conductivity version January 20, 2015. This work was supported by the Office of Naval of SiC, together with the large bandgap, allows SiC-based Research, Arlington, VA, USA, under Grant N00014-08-1-0080. The review devices to operate at temperatures easily exceeding 200 °C. of this paper was arranged by Editor N. Ohtani. H. A. Mantooth is with the University of Arkansas, Fayetteville, AR 72701 All of these properties make wide bandgap semiconductor USA (e-mail: [email protected]). devices a promising alternative to Si-based devices. K. Peng and E. Santi are with the Department of Electrical Engineer- Substantial improvements in GaN and SiC material quality ing, University of South Carolina, Columbia, SC 29208 USA (e-mail: [email protected]; [email protected]). over the past several years have led to the availability of J. L. Hudgins is with the Department of Electrical Engineering, University commercial SiC and GaN power devices. In particular, SiC of Nebraska—Lincoln, Lincoln, NE 68588 USA (e-mail: [email protected]). Schottky diodes, MOSFETs, and junction gate FETs (JFETs) Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. have reached the market. Although GaN-based devices can Digital Object Identifier 10.1109/TED.2014.2368274 theoretically offer better performance than SiC, the lack 0018-9383 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. 424 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 2, FEBRUARY 2015

TABLE I turn-OFF thyristors, and IGBTs, were modeled in addi- MATERIAL PROPERTIES tion to bipolar junction transistors (BJTs) and SiC junction transistors [6]. This paper presents a survey of recent progress on SiC- and GaN-based power semiconductor devices along with their device models. In Section II, an overview of device mod- eling requirements is given, and five different device model levels are described. An SiC power devices are described in Section III, while GaN power devices are presented in Section IV. Throughout this paper, a description of reli- ability issues associated with these wide bandgap devices is provided. Some assertions regarding outstanding issues and future trends of power device modeling are provided in the of good-quality substrates hinders the development of high concluding section. voltage vertical GaN power devices. However, the interest in GaN power devices by industry is increasing. II. COMPACT DEVICE MODEL REQUIREMENTS Nevertheless, material defects are a root cause of device failures. These defects and corresponding secondary effects The basic objective in compact device modeling is to are exacerbated by additional energy from high electric fields, achieve a predictive description of the current flow through large current densities, increasing temperature, and interface the device as a function of the applied voltages and currents, stress of material layers. For example, nonmicropipe defects in environmental conditions, such as temperature and radiation, the bulk and epitaxial layers of SiC have been reported to limit and physical characteristics, such as geometry, doping levels, the current and voltage ratings in devices and have contributed and so on. Understanding this objective and the mathematical to degraded performance and failure [3]. The bottom line formulation that is consistent with the numerical algorithms question is whether SiC and GaN can meet or exceed Si used by circuit simulators to analyze circuits and systems, Failure In Time (FIT) (10−9 failures per device operation hour) is the first step in understanding how to create compact levels to take advantage of a projected significant increase models that are predictive of device behavior and also run at in power density in wide bandgap devices. This improved computationally attractive speeds. For device models, at least power density typically means higher operating temperatures, a good approximation to the actual relationship of the elec- greater thermal cycling, higher impressed electric fields - trical variables needs to be obtained. A compromise between all in opposition to device reliability. Yet presently, some computational speed and model accuracy is usually made. The second-generation SiC Schottky diodes are reported to have required accuracy and simulation time are crucial factors con- a failure rate of < 0.15 ppm. In addition, some SiC junction- sidered by device model designers when making this tradeoff. barrier Schottky (JBS) diodes have achieved a failure rate A very simple device model generally provides fast simulation of <0.5 failures per billion of operational hours (0.5 FIT) [4]. speed but loses physics insight into power device behavior and Meanwhile, looking at comparison with silicon devices, simulation accuracy. In contrast, a very complicated physics- Si insulated gate bipolar transistor (IGBT) modules are around based model is usually preferred for accurate simulation of tens to a few FIT. Gate drivers now have a higher FIT device behavior, but is very time-consuming and not very (and, therefore, worse reliability) than Si IGBT devices, and suitable for circuit simulation. Si Integrated Gate Commutated Thyristor (IGCT) operation in The predictive nature of a good compact model varies rail inverter applications has indicated > 45 years mean time depending on the intended use of the model. In the case between failures and an associated low FIT [5]. Therefore, of power semiconductor device models, the intended use is SiC diodes have been shown to meet the reliability levels of typically as a power switch in power electronics applications. Si; but because material defects can dominate device behavior, Therefore, it is not necessary to model first derivative particularly over time, this should be strongly considered when characteristics, such as device transconductance and output trying to model actual characteristics of wide bandgap devices, conductance, to the degree of accuracy expected in a Berkeley particularly devices other than diodes. short-channel insulated gate FET model for analog integrated The commercially available wide bandgap semiconductor circuit design. The primary considerations are predicting the power devices indicate that a significant breakthrough in power dc I–V characteristics of the device along with switching electronics has been achieved over the past decades. As power characteristics resulting from attributes, such as device capaci- devices have progressed, power device simulation is becoming tances, carrier lifetimes, and conductivity modulation of lightly an increasingly significant method for studying device perfor- doped, voltage-blocking regions. mance. Significant work has been devoted to the creation and A basic device model selection procedure is shown in Fig. 1. validation of compact device models for the purpose of power As a first step, the device model requirements are determined electronic circuit simulations. As many of the SiC devices based on the balance between model accuracy and simulation were created, researchers developed SiC models, starting with time. According to the device modeling requirements, an diodes and static induction transistors and then proceeded appropriate device model is chosen for characterization. Static to MOSFETs and JFETs. Others, such as thyristors, gate I–V and C–V measurements are performed to extract model MANTOOTH et al.: MODELING OF WIDE BANDGAP POWER SEMICONDUCTOR DEVICES—PART I 425

1) Behavioral Models: These models simulate power devices without considering their physical mechanism of operation, and usually they are implemented using mathematical fitting methods. Their relevant model para- meters have no direct physical meaning. The advantage of these behavioral models is that they are simple and less time-consuming, although their accuracy is low, Fig. 1. Device model selection procedure: measurements, parameter extrac- especially when the device operates under conditions tion, and model validation. different from those used for parameter curve fitting. 2) Semiphysics Models: Such models are partly based on parameters that determine the accuracy of the device model. device physics. For simplicity, in many cases, the stan- Pulsed I–V measurements are used to avoid self-heating dard low voltage device models, which are available in issues. Based on these measurements, model parameters are circuit simulation tools, such as SPICE and SABER, are extracted to achieve a best fit to the measured data. Model val- adapted to address high-voltage power device modeling. idation is performed to check the effectiveness of the resulting Therefore, the physical meaning of some device model device model. For power devices, a double-pulse test circuit is parameters and equations might be lost. Some behavioral often used to validate the dynamic behavior of device models equations may also be included in these semiphysics and is sometimes used for device characterization. Based on models. the validation against experimental results, the selected model 3) Physics-Based Models: These models are based on may be either accepted or rejected. If the device model is semiconductor physics. The description of electrical rejected, a new device model needs to be chosen; and the and thermal behavior is obtained by solving physics same process described above must be repeated. equations with some simplifications. High computational speed and accuracy are required for 4) Seminumerical Models: These models are in between compact models of power semiconductor devices. For the physics-based and numerical models. For example, for development of power device models, it is critical that certain some power devices, especially bipolar power devices, prominent device features be captured in the model if they carrier distribution in different regions of the devices is dominate the static or switching device performance. For determined by the ambipolar diffusion equation (ADE) example, MOS capacitances have significant impact on the under high-level injection. The solution to the ADE is dynamic behavior of devices with isolated gates (MOSFET, obtained using a numerical method, such as Fourier IGBT, and MOS-controlled thyristor). These inherent capaci- series, Laplace transformation, or other methods, so tances vary strongly with device terminal voltages. In addition, that the spatial carrier distribution is calculated by the for bipolar power devices (p-i-n diodes, IGBT, BJT, and model. thyristor), conductivity modulation is a key effect that reduces 5) Numerical Models: Numerical simulation tools the resistance of the thick, lightly doped semiconductor layer. (SILVACO, Sentaurus TCAD, MEDICI, etc) are During its conduction period, the large injected carrier con- available for power devices and circuit simulation [10]. centration exceeds the background doping concentration; and The 2-D numerical simulation greatly contributes to the resistance of the region is reduced dramatically. Therefore, the development of power devices. These numerical the conductivity modulation effect should be considered for models can provide very accurate results, but they are bipolar device modeling. Due to high power loss, power complicated, computationally intensive, and require devices heat up during operation. The device characteristics are detailed information on material properties and device typically a strong function of junction temperature, so that an geometry. accurate model must capture this relationship. For this reason, The most commonly used levels are behavioral and electrothermal device models are sometimes used, while static physics-based models. Ideal switch models are often used thermal models (i.e., device characteristics are temperature to simulate overall circuit behavior when perhaps comparing dependent, but temperature is constant during simulation) circuit topologies. Once the topology is selected and detailed are sufficient for most instances. Moreover, breakdown in converter design begins, a physics-based model is soon desir- power devices might occur, typically under extreme tran- able when component interactions, switching waveforms, and sient conditions. The most common breakdown mechanism thermal management considerations need to be addressed. Any is avalanche breakdown, due to impact ionization; but punch- model-based design flow will employ different device models through breakdown and Zener breakdown are also possible in at different stages in the design process [11]. some cases [7]. The process of developing a physics-based model is shown Depending on the modeling method used, available mod- in Fig. 2. The initial phase involves device characterization els of power semiconductor devices can be categorized into through experimental evaluation of samples along with numer- five different levels, starting with the simplest behavioral ical device simulations of a representative device structure. models and then moving to more complex physics-based Through the analysis of these results, model equations are models [8], [9]. Assuming such models exist, then the model formulated from physics principles of charge transport and selection procedure of Fig. 1 can be exercised to obtain the storage, field effects, junctions, depleted regions, interface appropriate model for the task. traps, and so on. These relationships are simplified to a 426 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 2, FEBRUARY 2015

imperfections in SiC material. Stacking faults originate from the BPD and have been shown to cause an increase in the forward voltage, under constant current, in bipolar SiC devices and an increase in reverse-biased leakage current, and a decrease in forward-biased conduction current in unipo- lar devices. The main source of BPDs in the epitaxial layer is from propagation of BPDs present in the substrate. At present, the density is < 10 cm−2 due to improvements in bulk and epitaxial growth [19]. The TED are usually 1-D defects on the wafer surface that occur by insertion or removal of an extra half plane of atoms between two lattice atomic planes. Typically, the density of these defects is several Fig. 2. Model development methodology for physics-based models (Level 3). thousands per cm2. Diodes with higher TED densities have higher leakage current and slightly lower breakdown voltage compared with devices without dislocations [20]. lumped version or to a 1-D version for computational speed. Overcurrent during the ON-state causes an increase in the Sometimes 2-D effects are captured in a simplified manner, recombination energy being absorbed that then creates and fur- giving rise to so-called 1.5-D models. A large-signal model is ther extends existing material defects. These increased defects constructed and the equations parameterized based on observ- lead to more charge carrier recombination, thus delivering ability from experimental measurements. The model is then more energy to the crystal and increasing the effective forward implemented in the appropriate format for the target simulator. voltage drop (increasing the power dissipated in the device). Modeling tools such as ModLyng are very useful at this stage In particular, BPDs expand into triangular-shaped stacking because they allow for graphical construction of the model faults [21]. The 4°–8° off-orientation of the crystallographic and subsequent code generation into a variety of formats for c-axis for the epitaxial layer can cause BPD growth that is various simulators, such as Saber, HSpice, and Spectre [12]. inclined to the surface, originating from the epilayer, and sub- Then, the model is parameterized by fitting it to the measured strate interface with a growing stacking fault. For a SiC BJT, data through model parameter extraction and then simulating interface states near the emitter act as recombination sites and it under test configurations, such as clamped-inductive load, affect the current gain. Stacking faults grow from the surface to compare the measured with the simulated results. If the and degrade the current gain by up to 50% after a few hours requisite effects are captured, then the model is complete. of operation. This can be mitigated by proper processing of If they are not, then the model must be enhanced and part surface passivation layers [21]. Failure of Schottky diodes has of the process repeats. been reported from dv/dt stress that causes breakdown due to excess charge generation in the space charge region, under III. SiC POWER DEVICES AND THEIR MODELS reverse bias, in an area with dislocation defects [22]. The JBS Due to the significant improvements in SiC material diode structures have been shown to handle surge current den- growth technology, SiC-based power devices are available for sities at least twice as high as for Schottky diodes [23], [24]. high power, high temperature, and high frequency applica- However, operation of JBS diodes has shown an increased tions. Micropipes in SiC have been nearly eliminated (now forward voltage over time due to stacking faults increasing < 2.5 per cm2). Other defects are likely to be resolved within charge carrier recombination and impeding charge flow, just several years. These include threading screw dislocation (TSD) as in other SiC bipolar devices [21]. (TSD density is currently ∼1000 cm−2) [13], basal plane Problems exist with aluminum (Al) at operating tempera- dislocation (BPD) (BPD density is currently a few to tens tures > 200 °C [4]. There is a phenomenon termed interlayer of cm−2) [14], and threading edge dislocation (TED) (TED dielectric erosion (IDE) where Al electrodes erode and pene- density is presently 100–1000 s of cm−2) [15]. Comparatively, trate the underlying interlayer dielectric and finally reach the GaN can have bulk defect densities exceeding 106 cm−2. poly-Si gate contact, resulting in a gate–source short-circuit. Currently, several manufacturers have produced SiC diodes The erosion progression depends on the temperature and the that have a FIT of < 0.5 [16]. However, all non-Si devices are quality of the silicate glass. To prevent IDE, Si doped (1 wt%) conduction-current limited in their ratings because of material Al can be used to effectively reduce dissolution and movement; quality. or use of a barrier metal can prevent the movement of Al into Substrate screw dislocations can propagate into an adjoining the underlying material. An example of this is to deposit 50 nm epilayer depending on the epitaxial growth method. One dislo- of tantalum (Ta) and 150 nm of tantalum nitride as a barrier cation has been shown to reduce the breakdown voltage rating dielectric over the silicate glass interlayer. by 5%–35% and soften the breakdown characteristic. Highly Another problem is Al spearing in poly-Si. The Al spears localized current may concentrate in the dislocation resulting (or spikes) are observed in the gate located between the in microplasmas. The defects may also cause a reduction Al-interconnect and the gate after storage at an elevated in the charge carrier lifetime. The density of these types of temperature. This is caused by massive movement of Al of dislocation defects is currently ∼1000–3000 cm−2 [17], [18]. the gate interconnecting with the poly-Si gate. The Al spears Basal plane defects (BPD) are one of the troublesome extend to the channel region along the poly-Si gate and MANTOOTH et al.: MODELING OF WIDE BANDGAP POWER SEMICONDUCTOR DEVICES—PART I 427

TABLE II PUBLISHED SiC POWER DIODE MODELS

Fig. 3. Cross-sectional views of (a) SiC Schottky diode, (b) SiC p-i-n diode, and (c) SiC hybrid diode. compromise the gate oxide, causing a dielectric breakdown failure and finally a gate-to-source short circuit. Nickel silicide (Ni2Si) contacts have low resistance and are used as ohmic contacts on n-type 4H-SiC. A com- mon technique for fabricating these contacts is to deposit a thin nickel (Ni) film followed by rapid thermal annealing at 950 °C–1050 °C. Surface segregation of carbon due to this annealing causes the upper metallization layer to sep- arate from the semiconductor, thus delaminating the entire contact. To avoid this reaction, the surface segregated carbon is removed before the metallization process can be performed. However, delamination can still occur probably due to move- ment of carbon back to the surface over time. Ni2Si contact degradation also occurs when the Ni–Si-based ohmic contacts interact with the Al interconnects due to Al reacting with Ni2Si, decomposing it and forming NiAl and Si.

A. SiC Power Diodes The power diode is a key component in power electronics applications. Basically, SiC power diodes can be classified into three types: 1) SiC Schottky diode; 2) SiC p-i-n diode; and 3) SiC merged p-n-Schottky diode (MPS), also called JBS. 1) SiC Schottky Diodes: The Schottky diode is a very attractive unipolar device formed by an electrically nonlinear contact between a metal and a semiconductor bulk region, as shown in Fig. 3(a). It has low ON-state voltage drop, almost zero reverse recovery charge and extremely high switching speed, but its reverse leakage current is large, especially at high temperature, due to its lower built-in potential barrier. In addition, the max- imum breakdown voltage of practical Schottky diodes is limited by the increase in drift region resistance with breakdown voltage in the absence of conductivity mod- ulation effects. The commercially available Si Schottky diodes are usually rated at maximum breakdown voltages < 100 V. Beyond this limit, Si Schottky diodes cannot compete with Si p-i-n diodes due to the unac- ceptably large ON-state resistance of Schottky diodes. In comparison with their Si counterparts, novel SiC Schottky diodes can block thousands of volts because SiC material has a much larger breakdown electric field. carrier injection in the epitaxial drift region result- 2) SiC p-i-n Diodes: SiC p-i-n diodes consist of a highly ing in conductivity modulation. However, conductivity doped n-type substrate, a lightly doped n-type epitax- modulation causes significant reverse recovery current ial layer with specified thickness, and a highly doped during switching, which is undesirable because it causes p-type region for the anode, which is shown in Fig. 3(b). additional turn-ON loss in the active switch. The advantage of the SiC p-i-n diode is low ON-state 3) SiC JBS/MPS Diodes: Hybrid diodes (JBS or MPS) voltage drop in high current conduction, due to minority combine the attractive benefits of the low ON-state 428 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 2, FEBRUARY 2015

TABLE II curve fitting equations as a function of temperature. However, (CONTINUED.)PUBLISHED SiC POWER DIODE MODELS no dynamic characteristics were validated with this model. Another electrothermal behavioral model for SiC MPS diodes has been reported in [48]. Mathematical equations with no direct physical meaning and several curve-fitting parameters were used to describe the static behavior of the diode under forward and reverse bias voltages, and thermal network mod- eling is based on the analysis of the thermal constant spectrum of the temperature response of the diode.

C. Semiphysics-Based Models In [44], the conventional p-n junction Shockley equation was used to model forward conduction and reverse leakage currents for SiC JBS. The temperature dependence of series resistance was modeled as a second-order relationship with the difference between the device junction temperature and ambi- ent temperature. However, the reverse recovery characteristic was not included in this model. The charge-controlled model was used in [35] to accurately model the dynamic effects of parasitic device capacitance. In [47], the Shockley equation was also applied to model a SiC Schottky diode; and the effects of image force barrier lowering and tunneling on reverse leakage current were considered. In [36], the forward current– voltage characteristic of a SiC Schottky diode was modeled voltage drop of a Schottky contact and the high blocking using standard Schottky diode equations based on thermionic voltage of p-i-n diodes and have become common- emission theory. Note that the parameters used, such as place starting with the second generation of SiC diode Schottky barrier height and effective Richardson constant, structures. Hybrid diodes have Schottky-like ON-state have a clear physical meaning. The reverse leakage current and switching behavior and p-i-n-like OFF-state char- was modeled using a parallel conductance. Zhang et al. [41] acteristics at the same time. An MPS or JBS presented a SiC Schottky diode model using the standard diode consists of interleaved Schottky and p+ doped Schottky diode equation, including the temperature effect on regions [Fig. 3(c)]. For very small ON-state voltage carrier mobility. The parameter extraction procedure of this drop, only Schottky contact areas are active. On the approach to model a SiC Schottky diode was presented in [49]. other hand, when the diodes are reverse-biased, Schottky However, this model was not complete, because the tempera- contact conduction areas are electrically shielded by ture and reverse bias voltage effects on reverse leakage current p-i-n junction depletion regions. An additional advantage were not included. In [38]–[40], modified Schottky diode of hybrid diodes is increased surge current capability, models were proposed, considering the dependence of the due to the conduction of the p-i-n areas at higher forward reverse leakage current on the electric field and temperature. voltages. To evaluate the behavior of power electronics systems, D. Physics-Based Models accurate power diode device models are required for power converter designers. Consequently, accurate and reliable power The Mantooth unified diode model is capable of describing diode models are necessary. Most of the SiC power diode SiC p-i-n, Schottky, and MPS diodes under different models published have been reviewed, and they are listed simulation conditions, including forward bias, emitter chronologically in Table II. recombination, conductivity modulation, breakdown behav- ior, reverse recovery, and temperature effects [26]–[30]. The temperature dependence of the forward series resistance, B. Behavioral Models semiconductor material bandgap, and carrier mobility was In [43], the linear model of a SiC Schottky diode, including considered in this model. In [31], the lumped charge method a dc voltage drop and a series resistor, has been reported. was used to model SiC p-i-n diodes. The main idea of this Linear equations have been used to approximate the tem- approach is that the n-drift region is divided into a number perature effects on the dc voltage drop and on series resis- of small subregions, and charge control equations are applied tance. In [34], the exact same method has been applied to to each subregion. For a high voltage JBS diode, a novel estimate power loss characteristics of a SiC Schottky diode. physics-based model was developed in [42]. The forward A behavioral model of SiC merged p-i-n Schottky diodes was ON-resistance was more accurately approximated, consider- presented in [32] and [33]. The forward and reverse current ing the current spreading from anode to cathode due to versus voltage relationships were described using exponential the presence of nonconducting p+ regions on the anode equations, and model parameters were approximated using side [Fig. 3(c)]. The electric field at Schottky contact and MANTOOTH et al.: MODELING OF WIDE BANDGAP POWER SEMICONDUCTOR DEVICES—PART I 429 the Fowler–Nordheim tunneling currents were considered to This high blocking voltage was achieved using an 85-μmthick model the reverse leakage current. and 8 × 1014 cm−3 doped n-type drift epilayer. A specific ON-resistance of 123 m·cm2 was obtained with a gate E. Seminumerical-Based Models voltage bias of 18 V, and an effective channel carrier mobility of 22 cm2/Vs was measured. However, 10-kV SiC MOSFETs The forward I–V characteristics of 4H-SiC p-i-n diodes are not mature enough to be commercially available now. were investigated using an analytic model describing the For oxides in SiC, the electric field stress is determined by minority carrier distributions in different diode regions the oxide thickness and gate voltage. Choices are limited due (high-doped regions and low-doped drift region) [46]. In this to targets for threshold voltage and transconductance. Due to model, the solution to the ADE in a lightly doped drift permittivity differences between SiO2 and SiC, the electric region was derived under high injection conditions. The field strength in the oxide is typically three times higher than doping dependence of bandgap narrowing, incomplete dop- in the SiC. Control of the pitch in p-body modifies this field ing ionization, carrier lifetime, and mobility have been distribution. Various intrinsic defects not related to dopants or considered. The accuracy of this model has been verified impurities are observed at the SiC/SiO2 interface. An SiC has a by comparisons with numerical simulations and experimen- higher surface density of atoms per unit area compared with Si, tal results under different temperature and conduction cur- resulting in a higher density of dangling Si- and C-bonds, and rent conditions. However, this model is inconvenient for carbon cluster at the interface. Defects located in the near- implementation into circuit simulators, due to its com- interfacial oxide layer may appear in the energy gap of SiC plicated carrier distribution solution. In [45] and [50], and act as traps for electrons. Low channel mobility in 4H-SiC a Fourier-based solution to the ADE was used to develop is directly linked to very high interface state densities at the p-i-n diode models. The second-order partial differential car- SiO2/SiC boundary. Interface state density reduction plays a rier diffusion equation was turned into an infinite number of critical role in increasing channel mobility and improving high first-order linear differential equations with series coefficients temperature performance, as well as the reliability of power implemented by equivalent R–C components. The Fourier SiC MOSFETs and IGBTs. series of first-order equations is truncated to implement this Reduction of the interface state density and improvement in model. device reliability can be achieved by the use of nitric oxide postoxidation annealing. This reduces carbon clusters at the F. Numerical Models interface, thus increasing the channel mobility and the dielec- The finite-element simulation tool SILVACO was used to tric quality. One promising solution is to create a carefully simulate a 10 kV SiC p-i-n diode in [37], and simulation formed oxide-nitride-oxide dielectric on 4H-SiC [4], [21]. results have been compared with test results from the actual An accurate model of a SiC MOSFET is necessary for device. A good agreement between the SILVACO model and device evaluation, system design, and power converter behav- the experimental results was demonstrated. ior prediction. Therefore, much effort is needed to model SiC MOSFETs. A few SiC MOSFET models have been published and are listed chronologically in Table III. G. SiC Power MOSFET A SiC vertical power MOSFET is a next-generation H. Behavioral Models switching device expected to replace conventional Si power To model the turn-ON dynamic characteristics of a switching devices in many applications because it can operate SiC MOSFET, a behavioral MOSFET model has been with lower power loss, at a higher switching frequency and at proposed in [71]. The SiC MOSFET model consists of a higher operating temperatures. In the past ten years, a lot of drain–source resistance and three constant interelectrode effort has been devoted to developing SiC power MOSFETs; capacitances. The drain–source resistance can be switched and great progress has been achieved. The first SiC power from infinity to a finite small value and vice versa, according MOSFET was demonstrated in 1994 in the form of a vertical to the transistor’s gate voltage. The parasitic inductances from trench gate structure (UMOSFET) [51]. The reported device device packages have been considered to accurately simulate had 150 V blocking voltage and 3.3 m·cm2 specific the transient ringing. A behavioral SiC MOSFET model is ON-resistance. It suffered from a high electric field in the gate built in [72] using polynomial functions to create a model oxide at the trench corner and low inversion carrier mobility. that estimates device loss. To avoid these drawbacks in a UMOSFET, a SiC planar gate MOSFET was fabricated using a double implantation MOS process to form p-base (DMOSFET) [52]. A diagram of a typi- I. Semiphysics-Based Models cal UMOSFET and DMOSFET are shown in Fig. 4. A 6H-SiC The conventional Shockley lateral MOSFET equations, DMOSFET was based on a 10-μm thick and 6.5×1015 cm−3 which can describe the static I–V characteristic curve, have doped n-type drift layer, which can support a reverse blocking been used to model a SiC vertical power MOSFET. These voltage of 760 V. Later on, DMOSFETs with higher reverse equations are implemented, for example, in the level 1 blocking voltages have been reported. A 10-kV 4H-SiC power MOSFET model in PSpice. Since the Shockley MOSFET DMOSFET was demonstrated [53]. This was the highest model was originally developed for lateral structure devices in reported blocking voltage for SiC power MOSFETs [53]. Si and germanium (Ge), many researchers have proposed some 430 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 2, FEBRUARY 2015

TABLE III TABLE III PUBLISHED SiC POWER MOSFET MODELS (CONTINUED.)PUBLISHED SiC POWER MOSFET MODELS

threshold voltage and device transconductance. The reduced carrier mobility in the drift layer and JFET region was considered in modeling ON-state resistance. This proposed model was validated from 25 °C to 200 °C. On the basis of the same model, Sun et al. [69] and Lu et al. [70] investigated a modified SiC MOSFET model that can simulate device behavior at low temperature (−25 °C). The effect of negative gate drive voltage on gate–source capacitance was also included in this proposed model. In [67], to account for the device self-heating effect, a Foster RC network was used for thermal modeling and coupled with the electri- cal model that used Shockley lateral MOSFET equations. Moreover, another large-signal model for 6H-SiC MOSFET with temperature compensation has been proposed [58]. The temperature-dependent compensating currents were considered to be in parallel with the MOS channel current between the drain and source. These three temperature-dependent currents were the body leakage current, channel current change due to modification to these equations for their proposed SiC vertical the gate threshold voltage variation and the channel current power MOSFET models. In [60], a simple SPICE model change due to drain, and source contact resistance variation. for SiC power DMOSFETs was proposed with some specific In [74], a temperature-dependent voltage source is added in modifications in the conventional Si lateral MOS channel mod- series with the gate of the standard MOSFET model, to sim- eling approach. Temperature-dependent voltage and current ulate the gate threshold voltage variation with operating tem- sources were added to describe the temperature-dependent gate perature. To include temperature-dependent carrier mobility MANTOOTH et al.: MODELING OF WIDE BANDGAP POWER SEMICONDUCTOR DEVICES—PART I 431

Fig. 4. (a) Cross-sectional views of SiC UMOSFET. (b) SiC DMOSFET [40]. behavior and avalanche effect, two parallel current sources are added in parallel with the standard MOSFET model. Sakurai and Newton [73] introduced a simple nth power law Fig. 5. Cross-sectional views of SiC DMOSFET for modeling. MOSFET model. This model had the excellent feature of fast parameter extraction, and was originally proposed for high power and temperature conditions. This poor inversion short-channel CMOS. In [62] and [66], this nth power law surface mobility is due to the large number of interface MOSFET model was used to simulate high-voltage SiC power defects during the MOS thermal oxidation process. A com- MOSFETs, improving the accuracy of forward I–V curves. prehensive physical model was given, incorporating interface trap densities, Coulombic interface trap scattering, surface J. Physics-Based Models roughness scattering, phonon scattering, velocity saturation, An analytical model for a DMOSFET was developed and so forth [61]. Coulomb scattering and surface roughness in [56] and [57]. This model was proposed based on regional scattering reduce surface mobility in the subthreshold and analysis of carrier transport in the channel and drift regions. linear region, whereas the saturation current is limited by The drift region was divided into three parts, as shown carrier saturation velocity. in Fig. 5: 1) an accumulation Region A; 2) a drift Region B with a varying cross section area; and 3) a drift Region C L. Numerical Models with a constant cross-region area. The voltage drops across A 2-D device model was created using the SILVACO these regions were calculated as a function of the electric ATLAS simulator to investigate a 4H-SiC 1200 V power field in these regions. Another physics-based model for a MOSFET [68]. This model included recombination effects, SiC DMOSFET was proposed in [63], where the nonuniform bandgap narrowing, impact ionization, and lattice heating. current distribution in the JFET region was modeled using A comprehensive numerical model considering carrier mobil- a nonlinear voltage source and a resistance network. One ity and interface states was established in [59]. The channel advantage of this novel DMOSFET model was that only a current distribution versus bias voltage was solved numerically single set of equations was used to describe device operation in two dimensions. in both the linear and saturation regions. McNutt et al. [54], [55] presented a compact model for SiC power MOSFET. The expression for the channel current IV. CONCLUSION in this model was the sum of two distinct components with This paper begins a comprehensive review of available different gate threshold voltages, providing additional flexi- devices and models in the power semiconductor space. The bility for device modeling. Due to the unique feature of the most prominent devices, the SiC diode and MOSFET, were channel current description, this model could reproduce the included here. Part II of this paper will complete the lesser gradual transition from linear to saturation region observed used SiC power devices and describe what is available in in SiC power MOSFETs. The parameter extraction was done GaN devices and models as well. using a software package called IMPACT. In [64] and [65], a new parameter extraction strategy for the McNutt model was REFERENCES introduced, which relied on the device datasheet data only, [1] J. L. Hudgins, G. S. Simin, E. Santi, and M. A. Khan, “An assessment of eliminating the need for experimental characterization. wide bandgap semiconductors for power devices,” IEEE Trans. Power Electron., vol. 18, no. 3, pp. 907–914, May 2003. [2]B.J.Baliga,Silicon Carbide Power Devices. Singapore: K. Seminumerical-Based Models World Scientific, 2005. [3] K. Shenai, P. G. Neudeck, M. Dudley, and R. F. Davis, “High-power Low channel mobility of electrons in the surface inversion switching in semiconductors—What is beyond silicon thyristor?” in layer is a severe limitation for a SiC MOSFET operating at Proc. IEEE Energytech, May 2011, pp. 1–6. 432 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 2, FEBRUARY 2015

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