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(12) United States Patent (10) Patent N0.: US 8,352,948 B2 Laviolette (45) Date of Patent: Jan

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(12) United States Patent (10) Patent N0.: US 8,352,948 B2 Laviolette (45) Date of Patent: Jan USOO8352948B2 (12) United States Patent (10) Patent N0.: US 8,352,948 B2 Laviolette (45) Date of Patent: Jan. 8, 2013 (54) METHOD TO AUTOMATICALLY REDIRECT (56) References Cited SRB ROUTINES TO A ZIIP ELIGIBLE ENCLAVE OTHER PUBLICATIONS IBM Readbooks (System programmer’s guide to: Workload Manger, (75) Inventor: Michel Laviolette, Cedar Park, TX (U S) Mar. 2008) (Hereinafter IBM).* MVS (MVS details, Mar. 2009, http://testa.r0berta.free.fr/ (73) Assignee: BMC Software, Inc., Houston, TX (U S) My%2OB00ks/Mainframe/j cl%2000b01%20tut0ria1s/MVSiDe tailsi-Partil .pdf). * (*) Notice: Subject to any disclaimer, the term of this U.S. Appl. No. 12/565,549 Non-Final Of?ce Action mailed Apr. 30, patent is extended or adjusted under 35 2012, 17 pages. U.S.C. 154(b) by 424 days. “Mainframe”, http://WWW.mainframe.eu/mvs38/asm/ Supervis0r%20(IEA)/IEAVELCR:2008). App1.No.: 12/582,296 (21) * cited by examiner Filed: Oct. 20, 2009 (22) Primary Examiner * Emerson Puente (65) Prior Publication Data Assistant Examiner * Sisley Kim US 2011/0072433 A1 Mar. 24, 2011 (57) ABSTRACT Related US. Application Data A Method to redirect SRB routines from otherwise non-ZIIP eligible processes on an IBM Z/ OS series mainframe to a ZIIP (63) Continuation-in-part of application No. 12/565,549, eligible enclave is disclosed. This redirection is achieved by ?led on Sep. 23, 2009. intercepting otherwise blocked operations and allowing them to complete processing Without errors imposed by the ZIIP (51) Int“ Cl“ processor con?guration. After appropriately intercepting and G06F 9/46 (200601) redirecting these blocked operations more processing may be (52) U-s- Cl- ---------- -- 718/102; 710/36; 710/51; 711/169; performed on the more ?nancially cost effective ZIIP proces 712/31 sor by users of mainframe computing environments. (58) Field of Classi?cation Search ...................... .. None See application ?le for complete search history. 25 Claims, 5 Drawing Sheets 4I0 / 400 IDENTIFY PREFIXED SAVE AREA (PSA) OR OTHER CONTROL BLOCK \4 (£6, SVT 0R ECVT) S 420 CREATE ZIIP ELIGIBLE ENCLAVE AND DISCOVER EIGHT BYTE UNIQUE / TOKEN IDENTIFIER I 430 STORE ORIGINAL POINTERS FOR SCHEDULE ADDRESSES + 440 PATCH IEAVELKR AND REPLACE EACH ADDRESS IN ALL PSAS WITH / CORRESPONDING ADDRESS POINTING TO INTERCEPTING SERVER ADDRESS SPACE I 450 WAIT FOR INVOCATION OF INTERCEPT ROUTINE PASS VALIDATION? 465 470 \ v SEND CALLER TO ORIGINAL REPLACE CALL TO SCHEDULE WITH CALL TO SAVED ADDRESS IEANSCHD AND LINK TO ENCLAVE US. Patent Jan. 8, 2013 Sheet 1 0f5 US 8,352,948 B2 l00 \ I20 I25 \ \ I I0 ./ MEMORY 2 1 I I5 G G I I J P P I I P P I30 CHANNEL UNIT / I = I35 I45 / UNKTO TELECOMM ANOTHER |40 MAINFRAME I50 DISK STORAGE TAPE STORAGE (DASD) FIGURE | US. Patent Jan. 8, 2013 Sheet 2 0f5 US 8,352,948 B2 OFFSET 000H 200 FIGURE 2 OFFSET B3CH _>ROUT|NE| OFFSET B40H _> ROUTINE 2 OFFSET B44H _>ROUT|NE 3 OFFSET B48H P ROUTINE 4 CONTROL BLOCK (e.g., PSA or SVT) OFFSET OOOH OFFSET B3CH —> SCHEDULE SCOPE=GLOBAL REPLACEMENT ROUTINE OFFSET B40H —> SCHEDULE SCOPE=GLOBAL, DISABLE REPLACEMENT ROUTINE OFFSET B44H —> SCHEDULE SCOPE=LOCAL REPLACEMENT ROUTINE OFFSET B48" —>SCHEDULE SCOPE=LOCAL, DISABLE REPLACEMENT ROUTINE PREFIXED SAVE |I|GURE 3A AREA (PSA) US. Patent Jan. 8, 2013 Sheet 3 0f5 US 8,352,948 B2 OFFSET 000H 350 OFFSET 240H > SCHEDULE SCOPE=GLOBAL WITH STOKEN _> —> OFFSET 24C" —> SCHEDULE SCOPE=LOCAL, DISABLE WITH STOKEN SUPERVISOR VECTOR HGURE 3B TABLE (SVT) US. Patent Jan. 8, 2013 Sheet 4 0f 5 US 8,352,948 B2 4IO / 400 IDENTIFY PREFIXED SAVE AREA (PSA) OR OTHER CONTROL BLOCK (£6, SVT 0R ECVT) U 420 CREATE ZIIP ELIGIBLE ENCLAVE AND DISCOVER EIGHT BYTE UNIQUE / TONEN IDENTIFIER L 430 / STORE ORIGINAL POINTERS FOR SCHEDULE ADDRESSES + 440 PATCH IEAVELNR AND REPLACE EACH ADDRESS IN ALL PSAS WITH / CORRESPONDING ADDRESS POINTING TO INTERCEPTING SERVER ADDRESS SPACE l 450 / WAIT FOR INVOCATION OF INTERCEPT ROUTINE PASS VALIDATION? 465 \ 470 SEND CALLER T0 ORIGINAL REPLACE CALL TO SCHEDULE WITH CALL TO SAVED ADDRESS IEAMSCHD AND LINK TO ENCLAVE FIGURE 4 US. Patent Jan. 8,2013 Sheet 5 0f5 US 8,352,948 B2 500 560 \I‘ 5I0 INPUT /550 f 57 I / __ 520 DISPLAY PU Input/ MEMORY PSD Output 540 / ’ NETWORK INTERFACE FIGURE 5 US 8,352,948 B2 1 2 METHOD TO AUTOMATICALLY REDIRECT products on the ZIIP. The details of this are known to those of SRB ROUTINES TO A ZIIP ELIGIBLE ordinary skill in the art and are not the topic of this disclosure. ENCLAVE Given these and other shortcomings, along with a potential ?nancial bene?t of utiliZing the ZIIP more generally, a method RELATED APPLICATIONS and system for implementing more general availability of the ZIIP is disclosed. Furthermore, typical multi processing com This disclosure is a continuation in part of US. Patent puters only include a plurality of a single type of processing Application Ser. No. 12/ 565,549 entitled “A Method to Auto unit or very different processing units. Therefore, software matically Redirect SRB Routines to a ZIIP Eligible Enclave,” developers faced with not only technical but ?nancial consid ?led 23 Sep. 2009, and which is incorporated by reference erations may bene?t from the embodiments disclosed herein. herein in its entirety. SUMMARY BACKGROUND In one embodiment, the scheduling of Service Request This disclosure relates generally to the ?eld of mainframe Block (SRB) work is intercepted such that application pro software management. More particularly, but not by way of grams are enabled to run on a more cost effective processor. limitation, this disclosure refers to a method of redirecting The cost effective processor was previously unavailable to Service Request Block (SRB) code from an otherwise ZIIP these application programs because of operating system limi ineligible process such that the process may execute properly tations. After redirecting the SCHEDULE service code to a on the ZIIP processor without incurring additional cost 20 different implementation of a scheduling routine the operat imposed by licensing agreements with International Business ing system limitations are circumvented. If no cost effective Machines Corp. (IBM) of Armonk NY. and/or other third processors are available for redirection then the application party software vendors. program may be directed back to the original processor for Referring now to FIG. 1, a high level block diagram of an timely completion. IBM ZSeries® mainframe computer 100 is shown. (ZSERIES 25 In another embodiment, a validation routine is run prior to is a registered trademark of the International Business redirecting application program requests such that only cer Machines Corporation.) The mainframe computer 100 con tain allowed application program requests may utilize the sists of memory 110, a processor frame 115, a plurality of redirection. General Processors (GPs) 120, a plurality of System Z Inte grated Information Processors (ZIIPs) 125, a channel unit 130 30 BRIEF DESCRIPTION OF THE DRAWINGS for processing Input/Output (I/O) requests, a connection to another mainframe 135 (which may be a network interface or FIG. 1 shows, in block diagram form, an exemplary IBM some other communication link such as a communication mainframe with GP processors and ZIIP processors. buss), a tape storage unit 140, a telecommunications link 145 FIG. 2 shows, in block diagram form, an example of an and a disk storage device 150 sometimes referred to as Direct 35 Operating System (OS) Control Block with pointers to OS Access Storage Device (DASD). routines. A single physical mainframe 100 may also be subdivided FIG. 3A shows, in block diagram form, one embodiment of into multiple Logical Partitions (LPARs). A LPAR is a logical intercepting otherwise non-eligible ZIIP functions from a Pre segmentation of a mainframe’s memory and other resources ?xed Save Area (PSA) and redirecting them to a ZIIP eligible that allows it to run its own copy of an operating system and 40 enclave. associated applications. LPAR’s may be enabled via special FIG. 3B shows, in block diagram form, one embodiment of hardware circuits or purely through software. LPAR’s may intercepting otherwise non-eligible ZIIP functions from a also allow multiple system images (of the same operating SupervisorVector Table (SVT) and redirecting them to a ZIIP system or different operating systems) to run in one machine. eligible enclave. Furthermore, each LPAR can execute one or more sub 45 FIG. 4 shows, in ?ow chart form, an example work?ow to systems within an operating system. A subsystem is a service intercept functions from a non-ZIIP eligible mainframe com provider that performs one or more functions, but does noth puter process and allow its execution to perform on the ZIIP ing until it is requested. Examples of mainframe subsystems without changing the processes code or recompilation of the include Customer Information Control System (CICS), Infor application representing the process. mation Management System (IMS), Resource Access Con 50 FIG. 5 shows, in block diagram form, an exemplary com trol Facility (RACF). When an LPAR is con?gured a system puting device comprised of a program control device. administrator may designate which physical hardware resources are available, either in whole or in part, to that DETAILED DESCRIPTION particular LPAR. In IBM System Z9 and successor mainframes, the System 55 Methods and systems to redirect workload from a GP to a Z Integrated Information Processor (ZIIP) is a special purpose ZIIP within an IBM ZSeries architecture are disclosed. An processor intended to o?Ioad the General Processor (GP) of IBM ZSeries mainframe may contain a plurality of processing the mainframe computer system. These processors appar units. The General Purpose (GP) processor has a run-time ently do not contain microcode or hardware features that cost associated with the amount of workload it performs.
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