Computing Research Association Annual Report
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Spreading Excellence Report
HIGH PERFORMANCE AND EMBEDDED ARCHITECTURE AND COMPILATION Project Acronym: HiPEAC Project full title: High Performance and Embedded Architecture and Compilation Grant agreement no: ICT-217068 DELIVERABLE 3.1 SPREADING EXCELLENCE REPORT 15/04/2009 Spreading Excellence Report 1 1. Summary on Spreading Excellence ................................................................................ 3 2. Task 3.1: Conference ........................................................................................................ 4 2.1. HiPEAC 2008 Conference, Goteborg ......................................................................... 4 2.2. HiPEAC 2009 Conference, Paphos ........................................................................... 10 2.3. Conference Ranking .................................................................................................. 16 3. Task 3.2: Summer School .............................................................................................. 16 th 3.1. 4 International Summer School – 2008 ................................................................... 16 th 3.2. 5 International Summer School – 2009 ................................................................... 21 4. Task 3.3: HiPEAC Journal ............................................................................................ 22 5. Task 3.4: HiPEAC Roadmap ........................................................................................ 23 6. Task 3.5: HiPEAC Newsletter ...................................................................................... -
A Compiler-Compiler for DSL Embedding
A Compiler-Compiler for DSL Embedding Amir Shaikhha Vojin Jovanovic Christoph Koch EPFL, Switzerland Oracle Labs EPFL, Switzerland {amir.shaikhha}@epfl.ch {vojin.jovanovic}@oracle.com {christoph.koch}@epfl.ch Abstract (EDSLs) [14] in the Scala programming language. DSL devel- In this paper, we present a framework to generate compil- opers define a DSL as a normal library in Scala. This plain ers for embedded domain-specific languages (EDSLs). This Scala implementation can be used for debugging purposes framework provides facilities to automatically generate the without worrying about the performance aspects (handled boilerplate code required for building DSL compilers on top separately by the DSL compiler). of extensible optimizing compilers. We evaluate the practi- Alchemy provides a customizable set of annotations for cality of our framework by demonstrating several use-cases encoding the domain knowledge in the optimizing compila- successfully built with it. tion frameworks. A DSL developer annotates the DSL library, from which Alchemy generates a DSL compiler that is built CCS Concepts • Software and its engineering → Soft- on top of an extensible optimizing compiler. As opposed to ware performance; Compilers; the existing compiler-compilers and language workbenches, Alchemy does not need a new meta-language for defining Keywords Domain-Specific Languages, Compiler-Compiler, a DSL; instead, Alchemy uses the reflection capabilities of Language Embedding Scala to treat the plain Scala code of the DSL library as the language specification. 1 Introduction A compiler expert can customize the behavior of the pre- Everything that happens once can never happen defined set of annotations based on the features provided by again. -
(URMD) Grad Cohort Workshop
MARCH 16-17, 2018 SAN DIEGO GRAD Cohort UnderrepresentedURMD Minorities & Persons with Disabilities 2018 www.cra.org Dear Grad Cohort Participant, We welcome you to the 2018 CRA Grad Cohort Workshop for Underrepresented Minorities + Persons with Disabilities 2018 (URMD)! The next few days are filled with sessions where 25 senior computing researchers and professionals will be sharing their strategies and experiences to help increase GradCohort your graduate school and career success. There will also be plenty of opportunities to meet and network with these successful researchers as well as with graduate students from other universities. We hope that you will take the utmost advantage of this unique experience by actively participating in discussions, developing peer networks, and building mentoring relationships. Since this is the inaugural URMD Grad Cohort Workshop, we are especially interested in hearing your feedback about the program and the experience. Please take time to complete the evaluation form provided after the workshop. We want to learn what you liked and did not like, as well as any suggestions you might have for improving the event in subsequent years. The 2018 CRA-URMD Workshop is made possible through generous contributions by the Computing Research Association, National Science Foundation, AccessComputing, Whova, Google and Association for Computing Machinery. Please join us in thanking them for their kind support. We hope that you take home many new insights and connections from this workshop to help you succeed in -
Entrepreneurship Opportunities & Skills
Entrepreneurship Opportunities & Skills Kunle Olukotun Stanford University 2019 CRA URMD Grad Cohort Workshop Kunle Olukotun • Professor of EE and CS at Stanford since 1992 – Cadence Design endowed chair • Computer architecture and parallel computing • Pioneer in CMP (multicore) processor design – Stanford Hydra project • Parallel programming for all programmers – Director of Pervasive Parallelism Lab (PPL) – High-performance Domain Specific Languages (DSLs) • Data Analytics for What’s Next (DAWN) – Democratizing machine learning Academic Research and Startups • When you can’t find an industrial partner for your ideas make one • Technology transfer by PhD – Understand the initial market for your product (technology) – What is your unfair advantage – More robust technology than research prototypes – Cost of schedule slip is much worse – You don’t have much time for research at a start-up • Pick your team wisely – Technical team (lab partners?) – Management team (who is making decisions) – Cap table • Funding issues – Investors (smart vs. dumb) – Angels vs Venture Capital firms Startup Pros/Cons Pros Cons • Don’t have to convince existing company to change • Have to convince investors course (until exit) (repeatedly) • Have to build a whole company, not just a development team • Finance, sales, marketing, … • Limited resources • Impatient capital Afara WebSystems • Founded in 1999 – Height of internet boom – Large web sites running out of power and space – Goal: Revolutionize internet data centers (multi-B $ market) – Goal: Approach: 10x -
Extraction and Use of Contextual Attributes for Theory Completion: an Integration of Explanation-Based and Similarity-Based Learning
Andrea Pohoreckyj Danyluk Department of Computer Science email: [email protected] 47 Lab Campus Drive Office: (413) 597-2178 Williams College FAX: (413) 597-4250 Williamstown, MA 01267 Education Columbia University, Ph.D. in Computer Science, May 1992. Dissertation: Extraction and Use of Contextual Attributes for Theory Completion: An Integration of Explanation-Based and Similarity-Based Learning. Advisors: Kathleen McKeown and Michael Lebowitz Columbia University, M.Phil. in Computer Science, June 1989. Columbia University, M.S. in Computer Science, January 1986. Vassar College, A.B. in Mathematics/Computer Science with Honors, May 1984. Professional Experience Northeastern University, Global Director of the Align Program and Visiting Professor (2018-2019). Williams College, Mary A. and William Wirt Warren Professor of Computer Science (2018-), Dennis A. Meenan ’54 Third Century Professor of Computer Science (2012-2018), Professor of Computer Science (2006-2012), Associate Professor of Computer Science (2001-2006), Assistant Professor of Computer Science (1993-2001), Department Chair (2005-2008). Williams College Acting Dean of the Faculty (August 2009-March 2010), Associate Dean of the Faculty (April-June 2010). Williams College, Cognitive Science Program Chair (2005-2006). New York University, Visiting Scholar (Fall 2015). Bell Atlantic Science and Technology, White Plains, NY. Research Consultant, 1997-1998. NYNEX Science and Technology, Inc., White Plains, NY. Member of Technical Staff, 1990-1994. Columbia University, Department -
COMPUTING RESEARCH NEWS CRN At-A-Glance
COMPUTING RESEARCH NEWS Computing Research Association Uniting Industry, Academia and Government to Advance Computing Research and Change the World. JANUARY 2018 Vol. 30 / No. 1 CRN At-A-Glance 2018 Conference at Snowbird In This Issue Preliminary Agenda 2 2018 Conference at Snowbird Preliminary Agenda The biennial CRA Conference at Snowbird is the flagship invitation-only conference 4 2018 Nominations for CRA Board; for the leadership of the North American computing research community. Petition Nominees Sought 5 2018 Outstanding Undergraduate This year at Snowbird: Researcher Award Winners The 2018 CRA Conference at Snowbird is co-chaired by Kim Hazelwood, 9 CRA-E Professional Development Workshop Facebook, and Vivek Sarkar, Georgia Tech. Plenary sessions will feature for Teaching-Track Faculty former CRA Chair David Patterson, University of California-Berkeley and Raquel 10 Videos Now Available from the CRA Summit on Urtasun, University of Toronto and Uber Advanced Technologies Group. A Technology and Jobs major focus of the conference will be diversity in computing, and additional 12 CRA Taulbee Survey Update parallel session topics include faculty recruiting, department rankings, and 13 Meeting the Needs of Individuals with Disabilities- new models for industrial research in CS. Accessible Computing 15 Nominations Sought for New CCC Council Members See page 2 for full article. 16 Security and Privacy for Democracy Panel 18 Microsoft Research Podcast on How Programming Languages Quietly Run the World with CCC Exec Member Ben Zorn 2018 Nominees for CRA Board; 18 Two Hardware Security Design Flaws Affect Billions Petition Nominees Sought of Computers 20 Get Involved with CRA-Women Activities 21 Expanding the Pipeline: CRA-W at 2017 Grace Hopper CRA is pleased to announce the 2018 Election Committee’s slate of nominees Celebration of Women in Computing for the CRA Board. -
Implementing and Evaluating Nested Parallel Transactions in Software Transactional Memory
Implementing and Evaluating Nested Parallel Transactions in Software Transactional Memory Woongki Baek, Nathan Bronson, Christos Kozyrakis, Kunle Olukotun Computer Systems Laboratory Stanford University Stanford, CA 94305 {wkbaek,nbronson,kozyraki,kunle}@stanford.edu ABSTRACT 1. INTRODUCTION Transactional Memory (TM) is a promising technique that sim- Transactional Memory (TM) [13] has surfaced as a promising plifies parallel programming for shared-memory applications. To technique to simplify parallel programming. TM addresses the dif- date, most TM systems have been designed to efficiently support ficulty of lock-based synchronization by allowing programmers to single-level parallelism. To achieve widespread use and maximize simply declare certain code segments as transactions that execute performance gains, TM must support nested parallelism available in an atomic and isolated way with respect to other code. TM takes in many applications and supported by several programming mod- responsibility for all concurrency control. The potential of TM els. has motivated extensive research on hardware, software, and hy- We present NesTM, a software TM (STM) system that supports brid implementations. We focus on software TM (STM) [8,11,19], closed-nested parallel transactions. NesTM is based on a high- because it is the only approach compatible with existing and up- performance, blocking STM that uses eager version management coming multicore chips. and word-granularity conflict detection. Its algorithm targets the Most TM systems, thus far, have assumed that the code within state and runtime overheads of nested parallel transactions. We a transaction executes sequentially. However, real world applica- also describe several subtle correctness issues in supporting nested tions often include the potential for nested parallelism in various parallel transactions in NesTM and discuss their performance im- forms such as nested parallel loops, recursive function calls, and pact. -
Ecpe Connections
alumni newsletter fall 2 011 volume 28 issue 1 ecpe connections alum helps bring trees to 9/11 memorial plaza more inside ... • computer engineering student attends google camp • faculty makes breakthroughs in bandwidth recycling • alum becomes new ecpe external advisory board leader www.ece.iastate.edu learn invent impact department news letter from the chair in this issue am pleased to be able to share exciting news about the growth department news ........................ 3-6 and continued success of the Department of Electrical and Com- new faculty and staff • distinguished lecture puter Engineering (ECpE) and report on the accomplishments of I series • new bio-electrical engineering our students, faculty and staff, and alumni, as I begin my second course • faculty and staff recognitions • year as the Palmer Department Chair in Electrical and Computer new online graduate certificate Engineering. With 1,259 undergraduate students enrolled in our electrical, alumni news .............................. 7-10 computer, and software engineering programs, our department is murray harpole’s legacy remembered • in contributing to Iowa State University’s enrollment memoriam • new leader of external advisory Fall Student Enrollment being at an all-time high this fall. Our graduate board • advisory board members • alumni programs also are maintaining strong enrollment, with awards • alum helps bring trees to 9/11 335 students in master’s and PhD programs. Graduate memorial plaza We continue to develop our curriculum to meet Students: 335 the needs of our growing population, and have student news ......................... 12-14 introduced a new bio-electrical engineering course for Undergraduate information assurance student group • wind undergraduates and a new online graduate certificate Students: 1,259 energy research summer program • student in nondestructive evaluation (page 6). -
Kunle Olukotun Cadence Design Systems Professor and Professor of Electrical Engineering
Kunle Olukotun Cadence Design Systems Professor and Professor of Electrical Engineering CONTACT INFORMATION • Administrative Contact Kathy Robinson - Administrative Associate Email [email protected] Tel (650) 723-1430 Bio BIO Kunle Olukotun is the Cadence Design Systems Professor in the School of Engineering and Professor of Electrical Engineering and Computer Science at Stanford University. Olukotun is well known as a pioneer in multicore processor design and the leader of the Stanford Hydra chip multiprocessor (CMP) research project. Olukotun founded Afara Websystems to develop high-throughput, low-power multicore processors for server systems. The Afara multicore processor, called Niagara, was acquired by Sun Microsystems. Niagara derived processors now power all Oracle SPARC-based servers. Olukotun currently directs the Stanford Pervasive Parallelism Lab (PPL), which seeks to proliferate the use of heterogeneous parallelism in all application areas using Domain Specific Languages (DSLs). ACADEMIC APPOINTMENTS • Professor, Electrical Engineering • Professor, Computer Science • Faculty Affiliate, Institute for Human-Centered Artificial Intelligence (HAI) • Member, Wu Tsai Neurosciences Institute HONORS AND AWARDS • Fellow, ACM (2007) • Fellow, IEEE (2007) PROFESSIONAL EDUCATION • PhD, Michigan (1991) LINKS • Personal Site: http://arsenalfc.stanford.edu/kunle/ Teaching COURSES 2021-22 Page 1 of 2 Kunle Olukotun http://cap.stanford.edu/profiles/Oyekunle_Olukotun/ • Digital Systems Design Lab: EE 109 (Spr) • Parallel Computing: CS 149 -
Energy-Efficient Abundant-Data Computing: the N3XT 1,000X
COVER FEATURE REBOOTING COMPUTING Energy-Efficient Abundant-Data Computing: The N3XT 1,000× Mohamed M. Sabry Aly, Mingyu Gao, Gage Hills, Chi-Shuen Lee, Greg Pitner, Max M. Shulaker, Tony F. Wu, and Mehdi Asheghi, Stanford University Jeff Bokor, University of California, Berkeley Franz Franchetti, Carnegie Mellon University Kenneth E. Goodson and Christos Kozyrakis, Stanford University Igor Markov, University of Michigan, Ann Arbor Kunle Olukotun, Stanford University Larry Pileggi, Carnegie Mellon University Eric Pop, Stanford University Jan Rabaey, University of California, Berkeley Christopher Ré, H.-S. Philip Wong, and Subhasish Mitra, Stanford University Next-generation information technologies will process unprecedented amounts of loosely structured data that overwhelm existing computing systems. N3XT improves the energy efficiency of abundant-data applications 1,000-fold by using new logic and memory technologies, 3D integration with fine-grained connectivity, and new architectures for computation immersed in memory. 24 COMPUTER PUBLISHED BY THE IEEE COMPUTER SOCIETY 0018-9162/15/$31.00 © 2015 IEEE he rising demand for high- new system technology that promises enabled by low-temperature performance IT services with to breathe new life into computing. layer transfer techniques. This human-like interfaces is driv- Key N3XT components include the unique approach decouples ing the quest for the next gen- following: high-temperature nanoma- Teration of energy-efficient computers. terial synthesis (to achieve These computers will operate on abun- › High-performance and energy- high- quality materials) from dant data that can be highly unstruc- efficient field-effect transistors low-temperature monolithic 3D tured and often streamed in terabytes. (FETs) based on atomic-scale integration. -
News from SCS Networks
SCS Newsletter | March 2016 News from SCS Networks IN THIS ISSUE AUSTECH 2015, THE FIRST AUST INTERNATIONAL CONFERENCE News from IN TECHNOLOGY 01 SCS Networks Mamadou Kaba Traoré Upcoming Conferences Department of Mathematics & Computer Science 03 African University of Science & Technology (AUST) The African University of Science and Technology (AUST) International Conference in Technology 2015 (AUSTECH’15) was conducted October 12-14, 2015, on AUST campus at Abuja, Nigeria. AUSTECH is an annual event by AUST which focuses on current developments in Engineering technologies, scientific and industrial applications for development in Sub-Saharan Africa. It has a multi-Conference format, with 3 symposia reflecting the core technological areas developed at AUST: • Petroleum Engineering Symposium (PES), chaired this year by D. OGBE, AUST (Nigeria). • Materials Science and Engineering Symposium (MSES), chaired this year by P. ONWUALU, AUST (Nigeria). • Computer Science Symposium (CSS), chaired this year by M.K. TRAORE, AUST and Blaise Pascal University (France), who also chaired the overall multi-conference. AUSTECH’15 program included a world-class selection of invited speakers and panels. It also promoted a Ph.D. Colloquium and Poster sessions, fora where opportunity was given to students to showcase their work in progress and link with their peers. Many people deserve credits for the success of AUSTECH’15. This includes the organization teams in the symposia and the overall multi- 2 conference, the authors, the reviewers, the panelists, and attendees who contributed to memorable cross-fertilization. The conference has Theme 2: MOBILE & TELECOM been sponsored by the ACBF (African Capacity Building Foundation). • Advances in Video Production, Application Generation and A special emphasis has to be done here on the Computer Science Telecommunications, contribution of Michael Adeyeye, University of Symposium, which focused on Theories, Technologies and Applications West Australia. -
Multicore Cpus: Processor Proliferation - IEEE Spectrum 2/15/11 1:51 PM
Multicore CPUs: Processor Proliferation - IEEE Spectrum 2/15/11 1:51 PM SEMICONDUCTORS / PROCESSORS FEATURE Multicore CPUs: Processor Proliferation From multicore to many-core to hard-to-describe-in-a-single-word core By SAMUEL K. MOORE / JANUARY 2011 This is part of IEEE Spectrum's special report: Top 11 Technologies of the Decade Back in 1994, programmers figured that whatever code they wrote would run at least 50 percent faster on a 1995 machine and 50 percent faster still on a '96 system. Coding would continue as it always had, with instructions designed to be executed one after the other. But Kunle Olukotun, then a newly minted professor of electrical engineering at Stanford, saw that the party couldn't go on forever. The microprocessors of the day couldn't scale up as efficiently as you'd expect through the mere addition of ever more and ever faster transistors, the two things that Moore's Law provided. To solve that problem, Olukotun and his students designed the first general-purpose multicore CPU. This idea, more than any other in the past decade, is what has kept the semiconductor industry climbing the Moore's Law performance curve. Without multicore chips, the computing capability of everything from Illustration: Frank Chimero servers to netbooks would not be much better than it was a decade ago. Everyone's happy—except perhaps for the programmers, who must now write code with threads of instructions that must be executed together—in pairs, quartets, or even larger groupings. It's not that old, single-core CPUs weren't already doing some parallel processing.