DOCSLIB.ORG

Ecpe Connections

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Ecpe Connections alumni newsletter fall 2 011 volume 28 issue 1 ecpe connections alum helps bring trees to 9/11 memorial plaza more inside ... • computer engineering student attends google camp • faculty makes breakthroughs in bandwidth recycling • alum becomes new ecpe external advisory board leader www.ece.iastate.edu learn invent impact department news letter from the chair in this issue am pleased to be able to share exciting news about the growth department news ........................ 3-6 and continued success of the Department of Electrical and Com- new faculty and staff • distinguished lecture puter Engineering (ECpE) and report on the accomplishments of I series • new bio-electrical engineering our students, faculty and staff, and alumni, as I begin my second course • faculty and staff recognitions • year as the Palmer Department Chair in Electrical and Computer new online graduate certificate Engineering. With 1,259 undergraduate students enrolled in our electrical, alumni news .............................. 7-10 computer, and software engineering programs, our department is murray harpole’s legacy remembered • in contributing to Iowa State University’s enrollment memoriam • new leader of external advisory Fall Student Enrollment being at an all-time high this fall. Our graduate board • advisory board members • alumni programs also are maintaining strong enrollment, with awards • alum helps bring trees to 9/11 335 students in master’s and PhD programs. Graduate memorial plaza We continue to develop our curriculum to meet Students: 335 the needs of our growing population, and have student news ......................... 12-14 introduced a new bio-electrical engineering course for Undergraduate information assurance student group • wind undergraduates and a new online graduate certificate Students: 1,259 energy research summer program • student in nondestructive evaluation (page 6). awards • cpre student attends google Not only are our student numbers increasing android camp rapidly, but our faculty and staff is growing as well. We have many new faces in the department (page 3), research news ......................... 15-20 including Ian Dobson, the inaugural recipient of the Arend J. and Verna V. Sandbulte research in brief • ibm faculty award • Professorship in Engineering, and Assistant Professor Faxian Xiu. Additionally, software helping biologists understand micro- engineering faculty members Samik Basu and David Weiss received joint appointments organisms • improving wireless networks • with the Department of Electrical and Computer Engineering and the Department of dean’s research initiatives • nsf awards for Computer Science. materials, devices, and circuits research • As we grow our department, research efforts continue to increase and strengthen bandwidth recycling • nsf career award • our reputation. Several faculty members recently received prestigious grants and awards strengthening the professoriate to fund their research. Vikram Dalal, Thomas M. Whitney Professor in Electrical En- gineering, received a 2011 IBM Faculty Award for his work in advancing solar energy (page 16) and Northrop Grumman Assistant Professor Sumit Chaudhary received a Na- tional Science Foundation (NSF) CAREER Award to improve organic solar cell efficiency about this issue (page 19). Assistant Professors Ayman Fayed and Liang Dong also each received NSF grants to fund groundbreaking research projects they are leading (page 18). Additionally, Fall 2011 • Volume 28 • Issue 1 James McCalley received an NSF Integrative Graduate Education and Research Trainee- Department Chair: David C. Jiles ship Program award, which you can read more about online at www.ece.iastate.edu. Newsletter Coordinator: Kenzie Brennan Many of our alumni also are being recognized for their career achievements, includ- ing Chris Holland, whose company developed equipment to plant trees in the 9/11 This newsletter is published twice a year by Memorial Plaza (page 10), and Bruce Trump, who is leading ECpE’s External Advisory the Department of Electrical and Computer Board (page 8). Engineering, Iowa State University, I am pleased to have been able to renew many acquaintances this year and look 2215 Coover Hall, Ames, IA 50011-3060, forward to connecting with more of our alumni this fall. I welcome you to join us www.ece.iastate.edu; [email protected], October 22 for Homecoming Weekend, or anytime you have a chance to return to your 515 294-1097. © 2011 alma mater. To give a gift to the ECpE department, visit Kind regards, www.foundation.iastate.edu or call the ISU Foundation at 515 294-2416. David C. Jiles Iowa State University does not discriminate Palmer Department Chair in Electrical and Computer Engineering on the basis of race, color, age, religion, Anson Marston Distinguished Professor national origin, sexual orientation, gender identity, sex, marital status, disability, or status as a U.S. veteran. Inquiries about the cover photo can be directed to the Director of Equal The 9/11 Memorial Plaza and equipment an ECpE alumnus created to plant trees on the Opportunity and Diversity, 3280 Beardshear plaza. Memorial photo courtesy of National September 11 Memorial & Museum, created Hall, 515 294-7612. by Squared Design Lab. Equipment photo courtesy of Chris Holland and Natalie Hammer. 2 ecpe connections department news ecpe welcomes new faculty and staff Virginia “Ginny” Anderson became the bachelor’s degree from Mid-America Nazarene University. program assistant for the Information Assurance Center and ECpE department in Colin Christy (MSEE ’90) came to ECpE in April. She also assists the Security and May as the program manager of the EPRC Software Engineering Research Center. and as an energy systems specialist for the Anderson had served as a secretary in the Center for Industrial Research and Service department since 2001. (CIRAS). At the EPRC, Christy works with member companies to select and fund electric power systems research and coordinates short Samik Basu began a three-year appoint- courses. At CIRAS, he works with industrial ment in January as director of the software companies on energy management issues. He received his bach- engineering program, a joint position in the elor’s and PhD degrees in electrical engineering from the Univer- ECpE and computer science departments. sity of Missouri–Rolla and Kansas State University, respectively. Basu joined the Department of Computer Science in 2003, where he currently serves as Ian Dobson joined ECpE this fall as the inau- an associate professor. gural recipient of the Arend J. and Verna V. Sandbulte Professorship in Engineering. He Paula Beckman (BS JLMC ’92) joined ECpE has a bachelor’s degree in mathematics from Student Services as a secretary in February. Cambridge University and a PhD in electrical She helps plan student events and schedules engineering from Cornell University. For more graduate exams and advising appointments. than 20 years, he was a faculty member in the Beckman has worked for Iowa State for 17 electrical and computer engineering depart- years. She currently is working on an associ- ment at the University of Wisconsin–Madison. He is a Fellow of ate’s degree in criminal justice at Des Moines IEEE, and is a member of ISU’s electric power and energy systems Area Community College (DMACC). research group and energy infrastructure strategic research area. Lucky Bene started in February as an ac- Hazel Peterson began as ECpE’s secretary in countant. He prepares budgets and processes January. She schedules lectures, assists in fac- reimbursements and student time sheets. He ulty searches, reserves conference rooms, and previously was an accountant and accounting more for the department. Peterson previously officer in Nigeria. Bene received a diploma worked for 10 years as the secretary for ISU in accountancy and a postgraduate diploma Extension and Outreach’s Communications in business studies in Nigeria. He also has an and External Relations unit. Peterson has an associate’s degree in accounting information associate’s degree from DMACC. systems and an accounting paraprofessional degree from DMACC. David Weiss received a joint appointment Barbara Brown is the administrative special- in the ECpE and computer science depart- ist for the Electric Power Research Center ments in August. He joined the Department (EPRC) and Power Systems Engineering of Computer Science in 2009 as the inaugural Research Center. Her duties include budget- Lanh and Oanh Nguyen Endowed Chair in ing, processing reimbursements, managing Software Engineering. He served in several in- accounts, and organizing activities for the dustry positions before coming to Iowa State. Wind Energy Science, Engineering, and Pol- icy undergraduate research experience. She Faxian Xiu joined this fall as an assistant previously was an assistant to the area vice president at Ecolab. professor. Xiu has bachelor’s and master’s She has an associate’s degree from Baptist Bible College. degrees in materials science and engineer- ing from the Harbin Institute of Technology Jenifer Bungert started in May as the pro- gram assistant for research and graduate and the University of California, Los Angeles education. Her responsibilities include pre- (UCLA), respectively, and a PhD in electrical proposal preparation, and graduate student engineering from the University of California, admissions and recruiting. She previously Riverside. He previously worked as a staff was a grant writer for Youth and Shelter research associate at UCLA. He is a member of ISU’s
Load more

Recommended publications
  • Spreading Excellence Report
    HIGH PERFORMANCE AND EMBEDDED ARCHITECTURE AND COMPILATION Project Acronym: HiPEAC Project full title: High Performance and Embedded Architecture and Compilation Grant agreement no: ICT-217068 DELIVERABLE 3.1 SPREADING EXCELLENCE REPORT 15/04/2009 Spreading Excellence Report 1 1. Summary on Spreading Excellence ................................................................................ 3 2. Task 3.1: Conference ........................................................................................................ 4 2.1. HiPEAC 2008 Conference, Goteborg ......................................................................... 4 2.2. HiPEAC 2009 Conference, Paphos ........................................................................... 10 2.3. Conference Ranking .................................................................................................. 16 3. Task 3.2: Summer School .............................................................................................. 16 th 3.1. 4 International Summer School – 2008 ................................................................... 16 th 3.2. 5 International Summer School – 2009 ................................................................... 21 4. Task 3.3: HiPEAC Journal ............................................................................................ 22 5. Task 3.4: HiPEAC Roadmap ........................................................................................ 23 6. Task 3.5: HiPEAC Newsletter ......................................................................................
    [Show full text]
  • A Compiler-Compiler for DSL Embedding
    A Compiler-Compiler for DSL Embedding Amir Shaikhha Vojin Jovanovic Christoph Koch EPFL, Switzerland Oracle Labs EPFL, Switzerland {amir.shaikhha}@epfl.ch {vojin.jovanovic}@oracle.com {christoph.koch}@epfl.ch Abstract (EDSLs) [14] in the Scala programming language. DSL devel- In this paper, we present a framework to generate compil- opers define a DSL as a normal library in Scala. This plain ers for embedded domain-specific languages (EDSLs). This Scala implementation can be used for debugging purposes framework provides facilities to automatically generate the without worrying about the performance aspects (handled boilerplate code required for building DSL compilers on top separately by the DSL compiler). of extensible optimizing compilers. We evaluate the practi- Alchemy provides a customizable set of annotations for cality of our framework by demonstrating several use-cases encoding the domain knowledge in the optimizing compila- successfully built with it. tion frameworks. A DSL developer annotates the DSL library, from which Alchemy generates a DSL compiler that is built CCS Concepts • Software and its engineering → Soft- on top of an extensible optimizing compiler. As opposed to ware performance; Compilers; the existing compiler-compilers and language workbenches, Alchemy does not need a new meta-language for defining Keywords Domain-Specific Languages, Compiler-Compiler, a DSL; instead, Alchemy uses the reflection capabilities of Language Embedding Scala to treat the plain Scala code of the DSL library as the language specification. 1 Introduction A compiler expert can customize the behavior of the pre- Everything that happens once can never happen defined set of annotations based on the features provided by again.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • (URMD) Grad Cohort Workshop
    MARCH 16-17, 2018 SAN DIEGO GRAD Cohort UnderrepresentedURMD Minorities & Persons with Disabilities 2018 www.cra.org Dear Grad Cohort Participant, We welcome you to the 2018 CRA Grad Cohort Workshop for Underrepresented Minorities + Persons with Disabilities 2018 (URMD)! The next few days are filled with sessions where 25 senior computing researchers and professionals will be sharing their strategies and experiences to help increase GradCohort your graduate school and career success. There will also be plenty of opportunities to meet and network with these successful researchers as well as with graduate students from other universities. We hope that you will take the utmost advantage of this unique experience by actively participating in discussions, developing peer networks, and building mentoring relationships. Since this is the inaugural URMD Grad Cohort Workshop, we are especially interested in hearing your feedback about the program and the experience. Please take time to complete the evaluation form provided after the workshop. We want to learn what you liked and did not like, as well as any suggestions you might have for improving the event in subsequent years. The 2018 CRA-URMD Workshop is made possible through generous contributions by the Computing Research Association, National Science Foundation, AccessComputing, Whova, Google and Association for Computing Machinery. Please join us in thanking them for their kind support. We hope that you take home many new insights and connections from this workshop to help you succeed in
    [Show full text]
  • Entrepreneurship Opportunities & Skills
    Entrepreneurship Opportunities & Skills Kunle Olukotun Stanford University 2019 CRA URMD Grad Cohort Workshop Kunle Olukotun • Professor of EE and CS at Stanford since 1992 – Cadence Design endowed chair • Computer architecture and parallel computing • Pioneer in CMP (multicore) processor design – Stanford Hydra project • Parallel programming for all programmers – Director of Pervasive Parallelism Lab (PPL) – High-performance Domain Specific Languages (DSLs) • Data Analytics for What’s Next (DAWN) – Democratizing machine learning Academic Research and Startups • When you can’t find an industrial partner for your ideas make one • Technology transfer by PhD – Understand the initial market for your product (technology) – What is your unfair advantage – More robust technology than research prototypes – Cost of schedule slip is much worse – You don’t have much time for research at a start-up • Pick your team wisely – Technical team (lab partners?) – Management team (who is making decisions) – Cap table • Funding issues – Investors (smart vs. dumb) – Angels vs Venture Capital firms Startup Pros/Cons Pros Cons • Don’t have to convince existing company to change • Have to convince investors course (until exit) (repeatedly) • Have to build a whole company, not just a development team • Finance, sales, marketing, … • Limited resources • Impatient capital Afara WebSystems • Founded in 1999 – Height of internet boom – Large web sites running out of power and space – Goal: Revolutionize internet data centers (multi-B $ market) – Goal: Approach: 10x
    [Show full text]
  • Implementing and Evaluating Nested Parallel Transactions in Software Transactional Memory
    Implementing and Evaluating Nested Parallel Transactions in Software Transactional Memory Woongki Baek, Nathan Bronson, Christos Kozyrakis, Kunle Olukotun Computer Systems Laboratory Stanford University Stanford, CA 94305 {wkbaek,nbronson,kozyraki,kunle}@stanford.edu ABSTRACT 1. INTRODUCTION Transactional Memory (TM) is a promising technique that sim- Transactional Memory (TM) [13] has surfaced as a promising plifies parallel programming for shared-memory applications. To technique to simplify parallel programming. TM addresses the dif- date, most TM systems have been designed to efficiently support ficulty of lock-based synchronization by allowing programmers to single-level parallelism. To achieve widespread use and maximize simply declare certain code segments as transactions that execute performance gains, TM must support nested parallelism available in an atomic and isolated way with respect to other code. TM takes in many applications and supported by several programming mod- responsibility for all concurrency control. The potential of TM els. has motivated extensive research on hardware, software, and hy- We present NesTM, a software TM (STM) system that supports brid implementations. We focus on software TM (STM) [8,11,19], closed-nested parallel transactions. NesTM is based on a high- because it is the only approach compatible with existing and up- performance, blocking STM that uses eager version management coming multicore chips. and word-granularity conflict detection. Its algorithm targets the Most TM systems, thus far, have assumed that the code within state and runtime overheads of nested parallel transactions. We a transaction executes sequentially. However, real world applica- also describe several subtle correctness issues in supporting nested tions often include the potential for nested parallelism in various parallel transactions in NesTM and discuss their performance im- forms such as nested parallel loops, recursive function calls, and pact.
    [Show full text]
  • Ultrasparc T1 (Niagara)
    UltraSPARC T1 (Niagara) Vortrag im Rahmen des Seminars „Ausgewählte Themen in Hardwareentwurf und Optik“ HWS 06 Universität Mannheim Jochen Kinzel 1 Inhalt Überblick Core Crossbar Level 2-Cache DRAM-Controller Floating-Point-Unit Abschließende Bemerkungen Ausblick: Niagara II 2 Überblick 3 Der Weg zum UltraSPARC T1 Ursprüngliche Idee von Afara Websystems Inc. Übernahme durch Sun Microsystems Inc. Aug 2004: Präsentation des Niagara auf der HotChips 16 Nov 2005: UltraSPARC T1 ist fertig Dez 2005: Erste Server mit UltraSPARC T1 März 2006: OpenSPARC T1 veröffentlicht 4 Facts 64 Bit Multicore-Prozessor Verfügbar mit 4, 6 und 8 Cores Pro Core: 4 Threads 16 KBytes L1-ICache, 8 KByte L1-DCache 3 MByte Level 2-Cache Max. 1,2 GHz 72 Watt Leistungsbedarf 90nm-Technologie, 9 Layer 5 Anwendungsgebiete Parallele Anwendungen Zentral synchrone Dezentral asynchrone Anwendungen mit Anwendungen mit strukturierter Kontrollflussparallelität Datenflussparallelität Bsp.: Transaktionssysteme, Bsp.: Wettersimulation Webserver-, Datenbankanwendungen Geeignete Systeme: z.B. BlueGene von IBM Geeignete Systeme: z.B. FireT2000 von Sun mit UltraSPARC T1 Prozessor 6 Quelle: [1] 7 Core 8 Die Pipeline Quelle: [1] 9 Instruction Fetch Unit (IFU) Level 1 – Instruction Cache 16 KByte groß 4-fach assoziativ 32 Byte große Cache Line Instruction Fill Queue (IFQ) Missed Instruction List (MIL) Außerdem: Instruction Table Lookaside Buffer 10 IFU und Thread-Select Quelle: [1] 11 Thread-Select (TS) 2 Instruktionsregister pro Thread Program Counter (PC) pro Thread In jedem Takt: Erneute
    [Show full text]
  • Kunle Olukotun Cadence Design Systems Professor and Professor of Electrical Engineering
    Kunle Olukotun Cadence Design Systems Professor and Professor of Electrical Engineering CONTACT INFORMATION • Administrative Contact Kathy Robinson - Administrative Associate Email [email protected] Tel (650) 723-1430 Bio BIO Kunle Olukotun is the Cadence Design Systems Professor in the School of Engineering and Professor of Electrical Engineering and Computer Science at Stanford University. Olukotun is well known as a pioneer in multicore processor design and the leader of the Stanford Hydra chip multiprocessor (CMP) research project. Olukotun founded Afara Websystems to develop high-throughput, low-power multicore processors for server systems. The Afara multicore processor, called Niagara, was acquired by Sun Microsystems. Niagara derived processors now power all Oracle SPARC-based servers. Olukotun currently directs the Stanford Pervasive Parallelism Lab (PPL), which seeks to proliferate the use of heterogeneous parallelism in all application areas using Domain Specific Languages (DSLs). ACADEMIC APPOINTMENTS • Professor, Electrical Engineering • Professor, Computer Science • Faculty Affiliate, Institute for Human-Centered Artificial Intelligence (HAI) • Member, Wu Tsai Neurosciences Institute HONORS AND AWARDS • Fellow, ACM (2007) • Fellow, IEEE (2007) PROFESSIONAL EDUCATION • PhD, Michigan (1991) LINKS • Personal Site: http://arsenalfc.stanford.edu/kunle/ Teaching COURSES 2021-22 Page 1 of 2 Kunle Olukotun http://cap.stanford.edu/profiles/Oyekunle_Olukotun/ • Digital Systems Design Lab: EE 109 (Spr) • Parallel Computing: CS 149
    [Show full text]
  • Sun's Big Splash
    WINNER INTEGRATED CIRCUITS Sun’s Big Splash THE NIAGARA MICROPROCESSOR CHIP IS SUN’S BEST HOPE FOR A COMEBACK BY LINDA GEPPERT he Sunnyvale, Calif., campus of Sun But Sun, headquartered in Santa Clara, Calif., is still far from its glory days of the last decade. It could use a Microsystems Inc. is a quiet and small miracle to get back solidly on its feet, and at last the company may have one: a new microprocessor chip peaceful place with six low-rise build- intended for the volume servers that are the heart of ings connected by tree-lined walkways. data centers running the information and Web pro- cessing for businesses, universities, hospitals, factories, TBut the tranquility masks a frightening real- and the like. Sun’s engineers have had working chips since last spring and are now heavily into testing and ity—Sun is in serious economic trouble. The debugging them and making design changes for the next company was badly splattered by the burst of fabrication run in early 2005. The server business generates $50 billion a year, the dot-com bubble of 2000. Revenues for according to Jessica Yang, a research analyst at IDC, Framingham, Mass., and Sun’s share recently is about this once towering colossus of the server 12 percent—down from 17 percent just four years ago. Sun’s new chip, called Niagara for the torrent of data industry went south, and its stock plunged and instructions that flow between the chip and its from more than US $60 in 2000 to less than memory, was designed from the ground up to do away with the impact of latency—the idle time a micropro- $3 in 2002.
    [Show full text]
  • Energy-Efficient Abundant-Data Computing: the N3XT 1,000X
    COVER FEATURE REBOOTING COMPUTING Energy-Efficient Abundant-Data Computing: The N3XT 1,000× Mohamed M. Sabry Aly, Mingyu Gao, Gage Hills, Chi-Shuen Lee, Greg Pitner, Max M. Shulaker, Tony F. Wu, and Mehdi Asheghi, Stanford University Jeff Bokor, University of California, Berkeley Franz Franchetti, Carnegie Mellon University Kenneth E. Goodson and Christos Kozyrakis, Stanford University Igor Markov, University of Michigan, Ann Arbor Kunle Olukotun, Stanford University Larry Pileggi, Carnegie Mellon University Eric Pop, Stanford University Jan Rabaey, University of California, Berkeley Christopher Ré, H.-S. Philip Wong, and Subhasish Mitra, Stanford University Next-generation information technologies will process unprecedented amounts of loosely structured data that overwhelm existing computing systems. N3XT improves the energy efficiency of abundant-data applications 1,000-fold by using new logic and memory technologies, 3D integration with fine-grained connectivity, and new architectures for computation immersed in memory. 24 COMPUTER PUBLISHED BY THE IEEE COMPUTER SOCIETY 0018-9162/15/$31.00 © 2015 IEEE he rising demand for high- new system technology that promises enabled by low-temperature performance IT services with to breathe new life into computing. layer transfer techniques. This human-like interfaces is driv- Key N3XT components include the unique approach decouples ing the quest for the next gen- following: high-temperature nanoma- Teration of energy-efficient computers. terial synthesis (to achieve These computers will operate on abun- › High-performance and energy- high- quality materials) from dant data that can be highly unstruc- efficient field-effect transistors low-temperature monolithic 3D tured and often streamed in terabytes. (FETs) based on atomic-scale integration.
    [Show full text]
  • Understanding SPARC Processor Performance
    Understanding SPARC Processor Performance MAY 15 & 16, 2019 CLEVELAND PUBLIC AUDITORIUM, CLEVELAND, OHIO WWW.NEOOUG.ORG/GLOC About the Speaker • Akiva Lichtner • Physics background • Twenty years experience in IT • Enterprise production support analyst • Java developer • Oracle query plan manager … • Spoke here at G.L.O.C. about TDD and Java dynamic tracing Audience • Developers • System administrators • Tech support analysts • IT managers Motivation • I have been working in tech support for a large application • We have run SPARC T4 servers and now we run T7 servers • Application servers, database servers • Environments are all different • Users complained for years about “environment X” being slow, finally figured out why • What I learned can be very useful for users of SPARC servers What is SPARC? • First released in 1987, created by Sun Microsystems to replace the Motorola 68000 in its workstation products • During the .com boom Solaris/SPARC and Windows/Intel were the only supported platforms for the JVM • In 2000 the bubble burst and Sun server sales plunged • Sun acquired Afara Websystems, which had built an interesting new processor, and renamed it the UltraSPARC T1 • Was followed by T2 through M8, evolutions of the same design • More recently Oracle has added significant new functionality Processor Design • High core count (even in the early days) • Many threads per core • “Barrel” processor • Designed to switch efficiently • Non-uniform memory access • Per-processor shared cache • Core-level shared cache A picture speaks a thousand
    [Show full text]
  • Advanced Multipurpose Microprocessor
    © 2014 IJIRT | Volume 1 Issue 5 | ISSN : 2349-6002 ADVANCED MULTIPURPOSE MICROPROCESSOR Pankaj Gupta, Ravi Sangwan IT Department, mdu university Abstract- the Next Generation Multipurpose European Deep Sub-Micron (DSM) technology in order Microprocessor (NGMP) is a SPARC V8 (E) there have to meet increasing requirements on performance and to been three major revisions of the architecture. The first ensure the supply of European space processors. published revision was the 32-bit SPARC Version 7 (V7) in II. ARCHITECTURAL OVERVIEW 1986. SPARC Version 8 (V8), the main differences between V7 and V8 were the addition of integer multiply and divide It should be noted that this paper describes the current instructions, and an upgrade from 80-bit "extended state of the NGMP. The specification has been frozen and precision" floating-point arithmetic to 128-bit "quad- the activity is currently in its architectural design phase. precision" arithmetic. This paper describes the baseline SPARC machines have generally used Sun's SunOS, architecture, points out key choices that have been made and emphasises design decisions that are still open. The Solaris or Open Solaris, but other operating systems such software tools and operating systems that will be available as Next STEP, RTEMS, FreeBSD, OpenBSD, NetBSD, for the NGMP, together with a general overview of the new and Linux have also been used. LEON4FT microprocessor, are also described. Fig. 1 depicts an overview of the NGMP architecture. The system will consist of five AHB buses; one 128-bit I. BACKGROUND Processor bus, one 128-bit Memory bus, two 32-bit I/O The LEON project was started by the European Space buses and one 32-bit Debug bus.
    [Show full text]