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Ultrasparc T1 (Niagara) UltraSPARC T1 (Niagara) Vortrag im Rahmen des Seminars „Ausgewählte Themen in Hardwareentwurf und Optik“ HWS 06 Universität Mannheim Jochen Kinzel 1 Inhalt Überblick Core Crossbar Level 2-Cache DRAM-Controller Floating-Point-Unit Abschließende Bemerkungen Ausblick: Niagara II 2 Überblick 3 Der Weg zum UltraSPARC T1 Ursprüngliche Idee von Afara Websystems Inc. Übernahme durch Sun Microsystems Inc. Aug 2004: Präsentation des Niagara auf der HotChips 16 Nov 2005: UltraSPARC T1 ist fertig Dez 2005: Erste Server mit UltraSPARC T1 März 2006: OpenSPARC T1 veröffentlicht 4 Facts 64 Bit Multicore-Prozessor Verfügbar mit 4, 6 und 8 Cores Pro Core: 4 Threads 16 KBytes L1-ICache, 8 KByte L1-DCache 3 MByte Level 2-Cache Max. 1,2 GHz 72 Watt Leistungsbedarf 90nm-Technologie, 9 Layer 5 Anwendungsgebiete Parallele Anwendungen Zentral synchrone Dezentral asynchrone Anwendungen mit Anwendungen mit strukturierter Kontrollflussparallelität Datenflussparallelität Bsp.: Transaktionssysteme, Bsp.: Wettersimulation Webserver-, Datenbankanwendungen Geeignete Systeme: z.B. BlueGene von IBM Geeignete Systeme: z.B. FireT2000 von Sun mit UltraSPARC T1 Prozessor 6 Quelle: [1] 7 Core 8 Die Pipeline Quelle: [1] 9 Instruction Fetch Unit (IFU) Level 1 – Instruction Cache 16 KByte groß 4-fach assoziativ 32 Byte große Cache Line Instruction Fill Queue (IFQ) Missed Instruction List (MIL) Außerdem: Instruction Table Lookaside Buffer 10 IFU und Thread-Select Quelle: [1] 11 Thread-Select (TS) 2 Instruktionsregister pro Thread Program Counter (PC) pro Thread In jedem Takt: Erneute Auswahl des zu bearbeitenden Threads 12 Integer Register File Quelle: [1] 13 Load/Store Unit (LSU) Schnittstelle zw. Core und Crossbar Level 1 – Data Cache 8 KByte groß 4-fach assoziativ 16 Byte große Cache line Write Through Policy (!!!) Puffert 8 Stores und 1 Load pro Thread 14 Floating-Point Frontend Unit Decodiert Floating-Point Instruktionen Einfache Instruktionen werden hier erledigt Komplizierte Instruktionen werden an die globale Floating-Point Unit geschickt Floating-Point Register File 15 Memory Management Unit Translation Lookaside Buffer: ITLB in der IFU, DTLB in der LSU Beide enthalten 64 Einträge 48 Bit virtueller Adressraum 40 Bit physischer Adressraum Unterstützt zweite Virtualisierungsschicht für bis zu acht nebenläufige Betriebssysteme 16 Der Core enthält außerdem: Execute Unit Stream Processing Unit Multiplier Unit Trap Logic Unit 17 Crossbar 18 Der Crossbar Der Crossbar besteht aus zwei Teilen: Dem Processor-Cache-Crossbar ... Quelle: [1] ... und dem Cache-Processor-Crossbar Quelle: [1] 19 PCX – Data Flow 123 104 103 64 63 0 Ctrl Addr. Data Quelle: [1] 20 PCX – Control Flow Quelle: [1] 21 Level 2-Cache 22 Level 2-Cache – Überblick 4 Bänke Interleaved in 64 Byte Schritten Cache Line Größe: 64 Byte 12-fach assoziativ Gesamtgröße von 3 MByte, 768 KByte pro Bank Ersetzung: Pseudo Least Recently Used Directory-Struktur für Cache-Kohärenz mit den Level 1-Caches 23 Quelle: [1] 24 L2-Tag, -VAUD, -DATA L2-Tag: Hält 22 Bit der Adressen Single Ported L2-VAUD Bits: Valid, Allocated, Used, Dirty L2-Data: Lesezugriff von 16 oder 64 Byte Schreibzugriff von 64 Byte 25 Miss-, Fill-, Writeback-Buffer Miss-Buffer Puffer mit 16 Einträgen Speichert Cache-Miss-Instruktionen Fill-Buffer Puffer mit 8 Einträgen Speichert Load-Instruktionen, die gerade vom DRAM-Controller bearbeitet werden Writeback-Buffer Puffer mit 8 Einträgen, je 64 Byte Speichert auszulagernde (dirty) Cache Lines 26 Directory Directory zum Wahrung der Cache- Kohärenz Ein Directory mit 2048 Einträgen pro Bank 1024 für L1-ICaches, 1024 für L1-DCaches Sorgt dafür, dass L1-ICaches und L1- DCaches niemals die selben Daten halten Schickt Invalidierungspakete an die L1- Caches 27 DRAM-Controller 28 DRAM-Controller Unterstützt DDR2-DIMMs Taktfrequenz: 125 MHz bis 200 MHz Frequenz des Datenflusses: 250 oder 400 MHz 37 Bits Adressbreite für max. 128 GByte Speicher pro Controller Max. Bandbreite: 23 GByte/s (bei 200 MHz) 29 Floating-Point-Unit 30 Floating-Point-Unit Quelle: [1] 31 Input FIFO 2 FIFOs à 8 Einträge 155 Bit pro Eintrag Max. eine Instruktion pro Takt aus den FIFOs in die Pipelines DIV-Instruktionen haben die höchste Priorität 32 Pipelines (1/2) Floating-Point Adder: 4-stufige Pipeline Feste Latenz von 4 bzw. 5 Takten Durchsatz: 0,5 - 1 Instruktionen pro Takt Floating-Point Multipier: 6-stufige Pipeline Feste Latenz von 7 Takten Durchsatz: 0,5 Instruktionen pro Takt 33 Pipelines (2/2) Floating-Point Divider: 7-stufige Pipeline Keine feste Latenz, abhängig von den Operanden (!!!) Latenz (Single Precision): 9 – 32 Takte Latenz (Douple Precision): 9 – 61 Takte 34 Output Arbiter Schickt Ergebnisse über CPX zurück zu den Cores Keine FIFO-Queue, kein Puffer! DIV-Ergebnisse haben Priorität 35 Abschließende Bemerkungen 36 Abschließende Bemerkungen Pro Sehr niedrige Verlustleistung Hohe Nebenläufigkeit durch 32 Threads Hoher Datendurchsatz Kontra Nur eine Floating-Point-Unit Kleine Caches Nicht für Multiprozessorsysteme mit Shared- Memory geeignet 37 Ausblick: Der Niagara II 38 Niagara II (1/2) Erstmals vorgestellt auf der HotChips 18 Neuerungen am Core: Weiterhin 8 Cores Jetzt 2 Threadgruppen à 4 Threads pro Core Zwei Execute-Units pro Core Eine FGU pro Core L1-ICache jetzt 8-fach assoziativ 39 Niagara II (2/2) Weitere Neuerungen: L2-Cache jetzt 4 MByte groß Zwei 10 GBit Ethernet Ports PCI-Express x8 Port Vier FB-DIMM Controller Wird in 65nm-Technologie gefertigt Kommt voraussichtlich in der zweiten Jahreshälfte 2007 auf den Markt 40 Gibt es Fragen? 41 Einsatz bei Die Firma Strato AG ist zweitgrößter Webhoster Europas. „Einsatz von Sun Fire T2000 Servern bei Anwendungen mit hohem Datendurchsatz sowie Sun X4200 Servern für rechenintensive Anwendungen mit häufigen Gleitkommaberechnungen.“ „Durch den Einsatz der Sun Fire T2000 Internetserver konnte der Energiebedarf um ein Zehntel und der Platzbedarf im Rechenzentrum auf ein Fünftel gesenkt werden.“ „Unter unseren Anwendungen, egal ob Web- oder E- Mail-Server, entspricht die Leistung eines einzigen Sun Fire T2000 Servers mit nur einem T1 Prozessor der vergleichbaren Leistung eines 32-Prozessor-Systems.“ 42 Quellenangaben (1/3) [1] OpenSPARC T1 Micro Architecture Specification http://opensparc-t1.sunsource.net/specs/OpenSPARCT1_Micro_Arch.pdf [2] UltraSPARC Architecture 2005 http://opensparc-t1.sunsource.net/specs/UA2005-current-draft-P-EXT.pdf [3] UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005 http://opensparc-t1.sunsource.net/specs/UST1-UASuppl-current-draft-P-EXT.pdf [4] A 32-way Multithreaded SPARC® Processor Autor: Poonacha Kongetira http://www.hotchips.org/archives/hc16/3_Tue/14_HC16_Sess10_Pres2_bw.pdf [5] Niagara: A 32-way Multithreaded SPARC® Processor Autoren: Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun http://ogun.stanford.edu/~kunle/publications/niagra_micro.pdf [6] Sun's Big Splash Autor: Linda Geppert http://ogun.stanford.edu/~kunle/publications/niagra_spectrum.pdf 43 Quellenangaben (2/3) [7] Sun stellt den UltraSPARC T1 mit CoolThreads vor Autor: Christian Vilsbeck http://www.tecchannel.de/news/themen/server/433065/index.html [8] Sun stellt neuen Multi-Core Prozessor UltraSPARC T1 vor http://de.sun.com/company/press-releases/2005/pm_087.html [9] Sun stellt mit Sun Fire T1000 und T2000 erste Systeme mit UltraSPARC T1 CoolThreads Technologie vor http://de.sun.com/company/press-releases/2005/pm_096.html [10] Sun Newsflash: Sun gibt Design für den UltraSPARC T1 Prozessor unter GPL Lizenz frei http://de.sun.com/company/press-releases/2006/pm_028.html [11] Sun will Veröffentlichung des Niagara-Chips vorziehen Autor: Stephen Shankland http://www.zdnet.de/news/hardware/0,39023109,39132763,00.htm [12] The Real Story about Sun's CoolThreads (aka Niagara) http://h71028.www7.hp.com/ERC/cache/280124-0-0-0-121.html?ERL=true 44 Quellenangaben (3/3) [13] AMD Opteron Processor Product Data Sheet http://www.amd.com/us- en/assets/content_type/white_papers_and_tech_docs/23932.pdf [14] FB-DIMM: Revolutionärer Speicher für Server http://www.tecchannel.de/server/hardware/402269/ [15] Niagara-2: A Highly Threaded Server-on-a-Chip Autor: Greg Grohoski http://www.opensparc.net/pubs/preszo/06/HotChips06_09_ppt_master.pdf [16] HOT CHIPS: Sun Niagara 2 mit 64 Threads Autor: Christian Vilsbeck http://www.tecchannel.de/news/themen/server/446213/ [17] Sun's Niagara 2 doubles down with twice the threads Autor: Stephen Shankland http://news.com.com/Suns+Niagara+2+doubles+down+with+twice+the+threads/ 2100-1006_3-6108880.html [18] Strato verbessert Energiebilanz um den Faktor zehn http://apps.sun.de/sunrdb/servlets/GetFile/192/1658_AB_Strato.pdf 45.
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